1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
| 1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
|
32 * $FreeBSD: head/sys/pci/if_wb.c 50477 1999-08-28 01:08:13Z peter $
| 32 * $FreeBSD: head/sys/pci/if_wb.c 50675 1999-08-30 23:08:32Z wpaul $
|
33 */
34
35/*
36 * Winbond fast ethernet PCI NIC driver
37 *
38 * Supports various cheap network adapters based on the Winbond W89C840F
39 * fast ethernet controller chip. This includes adapters manufactured by
40 * Winbond itself and some made by Linksys.
41 *
42 * Written by Bill Paul <wpaul@ctr.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
45 */
46
47/*
48 * The Winbond W89C840F chip is a bus master; in some ways it resembles
49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
50 * one major difference which is that while the registers do many of
51 * the same things as a tulip adapter, the offsets are different: where
52 * tulip registers are typically spaced 8 bytes apart, the Winbond
53 * registers are spaced 4 bytes apart. The receiver filter is also
54 * programmed differently.
55 *
56 * Like the tulip, the Winbond chip uses small descriptors containing
57 * a status word, a control word and 32-bit areas that can either be used
58 * to point to two external data blocks, or to point to a single block
59 * and another descriptor in a linked list. Descriptors can be grouped
60 * together in blocks to form fixed length rings or can be chained
61 * together in linked lists. A single packet may be spread out over
62 * several descriptors if necessary.
63 *
64 * For the receive ring, this driver uses a linked list of descriptors,
65 * each pointing to a single mbuf cluster buffer, which us large enough
66 * to hold an entire packet. The link list is looped back to created a
67 * closed ring.
68 *
69 * For transmission, the driver creates a linked list of 'super descriptors'
70 * which each contain several individual descriptors linked toghether.
71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
72 * abuse as fragment pointers. This allows us to use a buffer managment
73 * scheme very similar to that used in the ThunderLAN and Etherlink XL
74 * drivers.
75 *
76 * Autonegotiation is performed using the external PHY via the MII bus.
77 * The sample boards I have all use a Davicom PHY.
78 *
79 * Note: the author of the Linux driver for the Winbond chip alludes
80 * to some sort of flaw in the chip's design that seems to mandate some
81 * drastic workaround which signigicantly impairs transmit performance.
82 * I have no idea what he's on about: transmit performance with all
83 * three of my test boards seems fine.
84 */
85
86#include "bpf.h"
87#include "opt_bdg.h"
88
89#include <sys/param.h>
90#include <sys/systm.h>
91#include <sys/sockio.h>
92#include <sys/mbuf.h>
93#include <sys/malloc.h>
94#include <sys/kernel.h>
95#include <sys/socket.h>
| 33 */
34
35/*
36 * Winbond fast ethernet PCI NIC driver
37 *
38 * Supports various cheap network adapters based on the Winbond W89C840F
39 * fast ethernet controller chip. This includes adapters manufactured by
40 * Winbond itself and some made by Linksys.
41 *
42 * Written by Bill Paul <wpaul@ctr.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
45 */
46
47/*
48 * The Winbond W89C840F chip is a bus master; in some ways it resembles
49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
50 * one major difference which is that while the registers do many of
51 * the same things as a tulip adapter, the offsets are different: where
52 * tulip registers are typically spaced 8 bytes apart, the Winbond
53 * registers are spaced 4 bytes apart. The receiver filter is also
54 * programmed differently.
55 *
56 * Like the tulip, the Winbond chip uses small descriptors containing
57 * a status word, a control word and 32-bit areas that can either be used
58 * to point to two external data blocks, or to point to a single block
59 * and another descriptor in a linked list. Descriptors can be grouped
60 * together in blocks to form fixed length rings or can be chained
61 * together in linked lists. A single packet may be spread out over
62 * several descriptors if necessary.
63 *
64 * For the receive ring, this driver uses a linked list of descriptors,
65 * each pointing to a single mbuf cluster buffer, which us large enough
66 * to hold an entire packet. The link list is looped back to created a
67 * closed ring.
68 *
69 * For transmission, the driver creates a linked list of 'super descriptors'
70 * which each contain several individual descriptors linked toghether.
71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
72 * abuse as fragment pointers. This allows us to use a buffer managment
73 * scheme very similar to that used in the ThunderLAN and Etherlink XL
74 * drivers.
75 *
76 * Autonegotiation is performed using the external PHY via the MII bus.
77 * The sample boards I have all use a Davicom PHY.
78 *
79 * Note: the author of the Linux driver for the Winbond chip alludes
80 * to some sort of flaw in the chip's design that seems to mandate some
81 * drastic workaround which signigicantly impairs transmit performance.
82 * I have no idea what he's on about: transmit performance with all
83 * three of my test boards seems fine.
84 */
85
86#include "bpf.h"
87#include "opt_bdg.h"
88
89#include <sys/param.h>
90#include <sys/systm.h>
91#include <sys/sockio.h>
92#include <sys/mbuf.h>
93#include <sys/malloc.h>
94#include <sys/kernel.h>
95#include <sys/socket.h>
|
| 96#include <sys/queue.h>
|
96
97#include <net/if.h>
98#include <net/if_arp.h>
99#include <net/ethernet.h>
100#include <net/if_dl.h>
101#include <net/if_media.h>
102
103#if NBPF > 0
104#include <net/bpf.h>
105#endif
106
107#ifdef BRIDGE
108#include <net/bridge.h>
109#endif
110
111#include <vm/vm.h> /* for vtophys */
112#include <vm/pmap.h> /* for vtophys */
113#include <machine/clock.h> /* for DELAY */
114#include <machine/bus_memio.h>
115#include <machine/bus_pio.h>
116#include <machine/bus.h>
117#include <machine/resource.h>
118#include <sys/bus.h>
119#include <sys/rman.h>
120
121#include <pci/pcireg.h>
122#include <pci/pcivar.h>
123
| 97
98#include <net/if.h>
99#include <net/if_arp.h>
100#include <net/ethernet.h>
101#include <net/if_dl.h>
102#include <net/if_media.h>
103
104#if NBPF > 0
105#include <net/bpf.h>
106#endif
107
108#ifdef BRIDGE
109#include <net/bridge.h>
110#endif
111
112#include <vm/vm.h> /* for vtophys */
113#include <vm/pmap.h> /* for vtophys */
114#include <machine/clock.h> /* for DELAY */
115#include <machine/bus_memio.h>
116#include <machine/bus_pio.h>
117#include <machine/bus.h>
118#include <machine/resource.h>
119#include <sys/bus.h>
120#include <sys/rman.h>
121
122#include <pci/pcireg.h>
123#include <pci/pcivar.h>
124
|
124#define WB_USEIOSPACE
| 125#include <dev/mii/mii.h>
126#include <dev/mii/miivar.h>
|
125
| 127
|
126/* #define WB_BACKGROUND_AUTONEG */
| 128#include "miibus_if.h"
|
127
| 129
|
| 130#define WB_USEIOSPACE
131
|
128#include <pci/if_wbreg.h>
129
130#ifndef lint
131static const char rcsid[] =
| 132#include <pci/if_wbreg.h>
133
134#ifndef lint
135static const char rcsid[] =
|
132 "$FreeBSD: head/sys/pci/if_wb.c 50477 1999-08-28 01:08:13Z peter $";
| 136 "$FreeBSD: head/sys/pci/if_wb.c 50675 1999-08-30 23:08:32Z wpaul $";
|
133#endif
134
135/*
136 * Various supported device vendors/types and their names.
137 */
138static struct wb_type wb_devs[] = {
139 { WB_VENDORID, WB_DEVICEID_840F,
140 "Winbond W89C840F 10/100BaseTX" },
141 { CP_VENDORID, CP_DEVICEID_RL100,
142 "Compex RL100-ATX 10/100baseTX" },
143 { 0, 0, NULL }
144};
145
| 137#endif
138
139/*
140 * Various supported device vendors/types and their names.
141 */
142static struct wb_type wb_devs[] = {
143 { WB_VENDORID, WB_DEVICEID_840F,
144 "Winbond W89C840F 10/100BaseTX" },
145 { CP_VENDORID, CP_DEVICEID_RL100,
146 "Compex RL100-ATX 10/100baseTX" },
147 { 0, 0, NULL }
148};
149
|
146/*
147 * Various supported PHY vendors/types and their names. Note that
148 * this driver will work with pretty much any MII-compliant PHY,
149 * so failure to positively identify the chip is not a fatal error.
150 */
151
152static struct wb_type wb_phys[] = {
153 { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" },
154 { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" },
155 { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"},
156 { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" },
157 { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" },
158 { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" },
159 { 0, 0, "<MII-compliant physical interface>" }
160};
161
| |
162static int wb_probe __P((device_t));
163static int wb_attach __P((device_t));
164static int wb_detach __P((device_t));
165
| 150static int wb_probe __P((device_t));
151static int wb_attach __P((device_t));
152static int wb_detach __P((device_t));
153
|
| 154static void wb_bfree __P((caddr_t, u_int));
|
166static int wb_newbuf __P((struct wb_softc *,
167 struct wb_chain_onefrag *,
168 struct mbuf *));
169static int wb_encap __P((struct wb_softc *, struct wb_chain *,
| 155static int wb_newbuf __P((struct wb_softc *,
156 struct wb_chain_onefrag *,
157 struct mbuf *));
158static int wb_encap __P((struct wb_softc *, struct wb_chain *,
|
170 struct mbuf *));
| 159 struct mbuf *));
|
171
172static void wb_rxeof __P((struct wb_softc *));
173static void wb_rxeoc __P((struct wb_softc *));
174static void wb_txeof __P((struct wb_softc *));
175static void wb_txeoc __P((struct wb_softc *));
176static void wb_intr __P((void *));
| 160
161static void wb_rxeof __P((struct wb_softc *));
162static void wb_rxeoc __P((struct wb_softc *));
163static void wb_txeof __P((struct wb_softc *));
164static void wb_txeoc __P((struct wb_softc *));
165static void wb_intr __P((void *));
|
| 166static void wb_tick __P((void *));
|
177static void wb_start __P((struct ifnet *));
178static int wb_ioctl __P((struct ifnet *, u_long, caddr_t));
179static void wb_init __P((void *));
180static void wb_stop __P((struct wb_softc *));
181static void wb_watchdog __P((struct ifnet *));
182static void wb_shutdown __P((device_t));
183static int wb_ifmedia_upd __P((struct ifnet *));
184static void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
185
186static void wb_eeprom_putbyte __P((struct wb_softc *, int));
187static void wb_eeprom_getword __P((struct wb_softc *, int, u_int16_t *));
188static void wb_read_eeprom __P((struct wb_softc *, caddr_t, int,
189 int, int));
190static void wb_mii_sync __P((struct wb_softc *));
191static void wb_mii_send __P((struct wb_softc *, u_int32_t, int));
192static int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *));
193static int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *));
| 167static void wb_start __P((struct ifnet *));
168static int wb_ioctl __P((struct ifnet *, u_long, caddr_t));
169static void wb_init __P((void *));
170static void wb_stop __P((struct wb_softc *));
171static void wb_watchdog __P((struct ifnet *));
172static void wb_shutdown __P((device_t));
173static int wb_ifmedia_upd __P((struct ifnet *));
174static void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
175
176static void wb_eeprom_putbyte __P((struct wb_softc *, int));
177static void wb_eeprom_getword __P((struct wb_softc *, int, u_int16_t *));
178static void wb_read_eeprom __P((struct wb_softc *, caddr_t, int,
179 int, int));
180static void wb_mii_sync __P((struct wb_softc *));
181static void wb_mii_send __P((struct wb_softc *, u_int32_t, int));
182static int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *));
183static int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *));
|
194static u_int16_t wb_phy_readreg __P((struct wb_softc *, int));
195static void wb_phy_writereg __P((struct wb_softc *, int, int));
| |
196
| 184
|
197static void wb_autoneg_xmit __P((struct wb_softc *));
198static void wb_autoneg_mii __P((struct wb_softc *, int, int));
199static void wb_setmode_mii __P((struct wb_softc *, int));
200static void wb_getmode_mii __P((struct wb_softc *));
201static void wb_setcfg __P((struct wb_softc *, int));
| 185static void wb_setcfg __P((struct wb_softc *, u_int32_t));
|
202static u_int8_t wb_calchash __P((caddr_t));
203static void wb_setmulti __P((struct wb_softc *));
204static void wb_reset __P((struct wb_softc *));
| 186static u_int8_t wb_calchash __P((caddr_t));
187static void wb_setmulti __P((struct wb_softc *));
188static void wb_reset __P((struct wb_softc *));
|
| 189static void wb_fixmedia __P((struct wb_softc *));
|
205static int wb_list_rx_init __P((struct wb_softc *));
206static int wb_list_tx_init __P((struct wb_softc *));
207
| 190static int wb_list_rx_init __P((struct wb_softc *));
191static int wb_list_tx_init __P((struct wb_softc *));
192
|
| 193static int wb_miibus_readreg __P((device_t, int, int));
194static int wb_miibus_writereg __P((device_t, int, int, int));
195static void wb_miibus_statchg __P((device_t));
196
|
208#ifdef WB_USEIOSPACE
209#define WB_RES SYS_RES_IOPORT
210#define WB_RID WB_PCI_LOIO
211#else
212#define WB_RES SYS_RES_MEMORY
213#define WB_RID WB_PCI_LOMEM
214#endif
215
216static device_method_t wb_methods[] = {
217 /* Device interface */
218 DEVMETHOD(device_probe, wb_probe),
219 DEVMETHOD(device_attach, wb_attach),
220 DEVMETHOD(device_detach, wb_detach),
221 DEVMETHOD(device_shutdown, wb_shutdown),
| 197#ifdef WB_USEIOSPACE
198#define WB_RES SYS_RES_IOPORT
199#define WB_RID WB_PCI_LOIO
200#else
201#define WB_RES SYS_RES_MEMORY
202#define WB_RID WB_PCI_LOMEM
203#endif
204
205static device_method_t wb_methods[] = {
206 /* Device interface */
207 DEVMETHOD(device_probe, wb_probe),
208 DEVMETHOD(device_attach, wb_attach),
209 DEVMETHOD(device_detach, wb_detach),
210 DEVMETHOD(device_shutdown, wb_shutdown),
|
| 211
212 /* bus interface, for miibus */
213 DEVMETHOD(bus_print_child, bus_generic_print_child),
214 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
215
216 /* MII interface */
217 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
218 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
219 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
|
222 { 0, 0 }
223};
224
225static driver_t wb_driver = {
226 "wb",
227 wb_methods,
228 sizeof(struct wb_softc)
229};
230
231static devclass_t wb_devclass;
232
233DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0);
| 220 { 0, 0 }
221};
222
223static driver_t wb_driver = {
224 "wb",
225 wb_methods,
226 sizeof(struct wb_softc)
227};
228
229static devclass_t wb_devclass;
230
231DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0);
|
| 232DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
|
234
235#define WB_SETBIT(sc, reg, x) \
236 CSR_WRITE_4(sc, reg, \
237 CSR_READ_4(sc, reg) | x)
238
239#define WB_CLRBIT(sc, reg, x) \
240 CSR_WRITE_4(sc, reg, \
241 CSR_READ_4(sc, reg) & ~x)
242
243#define SIO_SET(x) \
244 CSR_WRITE_4(sc, WB_SIO, \
245 CSR_READ_4(sc, WB_SIO) | x)
246
247#define SIO_CLR(x) \
248 CSR_WRITE_4(sc, WB_SIO, \
249 CSR_READ_4(sc, WB_SIO) & ~x)
250
251/*
252 * Send a read command and address to the EEPROM, check for ACK.
253 */
254static void wb_eeprom_putbyte(sc, addr)
255 struct wb_softc *sc;
256 int addr;
257{
258 register int d, i;
259
260 d = addr | WB_EECMD_READ;
261
262 /*
263 * Feed in each bit and stobe the clock.
264 */
265 for (i = 0x400; i; i >>= 1) {
266 if (d & i) {
267 SIO_SET(WB_SIO_EE_DATAIN);
268 } else {
269 SIO_CLR(WB_SIO_EE_DATAIN);
270 }
271 DELAY(100);
272 SIO_SET(WB_SIO_EE_CLK);
273 DELAY(150);
274 SIO_CLR(WB_SIO_EE_CLK);
275 DELAY(100);
276 }
277
278 return;
279}
280
281/*
282 * Read a word of data stored in the EEPROM at address 'addr.'
283 */
284static void wb_eeprom_getword(sc, addr, dest)
285 struct wb_softc *sc;
286 int addr;
287 u_int16_t *dest;
288{
289 register int i;
290 u_int16_t word = 0;
291
292 /* Enter EEPROM access mode. */
293 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
294
295 /*
296 * Send address of word we want to read.
297 */
298 wb_eeprom_putbyte(sc, addr);
299
300 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
301
302 /*
303 * Start reading bits from EEPROM.
304 */
305 for (i = 0x8000; i; i >>= 1) {
306 SIO_SET(WB_SIO_EE_CLK);
307 DELAY(100);
308 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
309 word |= i;
310 SIO_CLR(WB_SIO_EE_CLK);
311 DELAY(100);
312 }
313
314 /* Turn off EEPROM access mode. */
315 CSR_WRITE_4(sc, WB_SIO, 0);
316
317 *dest = word;
318
319 return;
320}
321
322/*
323 * Read a sequence of words from the EEPROM.
324 */
325static void wb_read_eeprom(sc, dest, off, cnt, swap)
326 struct wb_softc *sc;
327 caddr_t dest;
328 int off;
329 int cnt;
330 int swap;
331{
332 int i;
333 u_int16_t word = 0, *ptr;
334
335 for (i = 0; i < cnt; i++) {
336 wb_eeprom_getword(sc, off + i, &word);
337 ptr = (u_int16_t *)(dest + (i * 2));
338 if (swap)
339 *ptr = ntohs(word);
340 else
341 *ptr = word;
342 }
343
344 return;
345}
346
347/*
348 * Sync the PHYs by setting data bit and strobing the clock 32 times.
349 */
350static void wb_mii_sync(sc)
351 struct wb_softc *sc;
352{
353 register int i;
354
355 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
356
357 for (i = 0; i < 32; i++) {
358 SIO_SET(WB_SIO_MII_CLK);
359 DELAY(1);
360 SIO_CLR(WB_SIO_MII_CLK);
361 DELAY(1);
362 }
363
364 return;
365}
366
367/*
368 * Clock a series of bits through the MII.
369 */
370static void wb_mii_send(sc, bits, cnt)
371 struct wb_softc *sc;
372 u_int32_t bits;
373 int cnt;
374{
375 int i;
376
377 SIO_CLR(WB_SIO_MII_CLK);
378
379 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
380 if (bits & i) {
381 SIO_SET(WB_SIO_MII_DATAIN);
382 } else {
383 SIO_CLR(WB_SIO_MII_DATAIN);
384 }
385 DELAY(1);
386 SIO_CLR(WB_SIO_MII_CLK);
387 DELAY(1);
388 SIO_SET(WB_SIO_MII_CLK);
389 }
390}
391
392/*
393 * Read an PHY register through the MII.
394 */
395static int wb_mii_readreg(sc, frame)
396 struct wb_softc *sc;
397 struct wb_mii_frame *frame;
398
399{
400 int i, ack, s;
401
402 s = splimp();
403
404 /*
405 * Set up frame for RX.
406 */
407 frame->mii_stdelim = WB_MII_STARTDELIM;
408 frame->mii_opcode = WB_MII_READOP;
409 frame->mii_turnaround = 0;
410 frame->mii_data = 0;
411
412 CSR_WRITE_4(sc, WB_SIO, 0);
413
414 /*
415 * Turn on data xmit.
416 */
417 SIO_SET(WB_SIO_MII_DIR);
418
419 wb_mii_sync(sc);
420
421 /*
422 * Send command/address info.
423 */
424 wb_mii_send(sc, frame->mii_stdelim, 2);
425 wb_mii_send(sc, frame->mii_opcode, 2);
426 wb_mii_send(sc, frame->mii_phyaddr, 5);
427 wb_mii_send(sc, frame->mii_regaddr, 5);
428
429 /* Idle bit */
430 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
431 DELAY(1);
432 SIO_SET(WB_SIO_MII_CLK);
433 DELAY(1);
434
435 /* Turn off xmit. */
436 SIO_CLR(WB_SIO_MII_DIR);
437 /* Check for ack */
438 SIO_CLR(WB_SIO_MII_CLK);
439 DELAY(1);
440 SIO_SET(WB_SIO_MII_CLK);
441 DELAY(1);
442 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
443 SIO_CLR(WB_SIO_MII_CLK);
444 DELAY(1);
445 SIO_SET(WB_SIO_MII_CLK);
446 DELAY(1);
447
448 /*
449 * Now try reading data bits. If the ack failed, we still
450 * need to clock through 16 cycles to keep the PHY(s) in sync.
451 */
452 if (ack) {
453 for(i = 0; i < 16; i++) {
454 SIO_CLR(WB_SIO_MII_CLK);
455 DELAY(1);
456 SIO_SET(WB_SIO_MII_CLK);
457 DELAY(1);
458 }
459 goto fail;
460 }
461
462 for (i = 0x8000; i; i >>= 1) {
463 SIO_CLR(WB_SIO_MII_CLK);
464 DELAY(1);
465 if (!ack) {
466 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
467 frame->mii_data |= i;
468 DELAY(1);
469 }
470 SIO_SET(WB_SIO_MII_CLK);
471 DELAY(1);
472 }
473
474fail:
475
476 SIO_CLR(WB_SIO_MII_CLK);
477 DELAY(1);
478 SIO_SET(WB_SIO_MII_CLK);
479 DELAY(1);
480
481 splx(s);
482
483 if (ack)
484 return(1);
485 return(0);
486}
487
488/*
489 * Write to a PHY register through the MII.
490 */
491static int wb_mii_writereg(sc, frame)
492 struct wb_softc *sc;
493 struct wb_mii_frame *frame;
494
495{
496 int s;
497
498 s = splimp();
499 /*
500 * Set up frame for TX.
501 */
502
503 frame->mii_stdelim = WB_MII_STARTDELIM;
504 frame->mii_opcode = WB_MII_WRITEOP;
505 frame->mii_turnaround = WB_MII_TURNAROUND;
506
507 /*
508 * Turn on data output.
509 */
510 SIO_SET(WB_SIO_MII_DIR);
511
512 wb_mii_sync(sc);
513
514 wb_mii_send(sc, frame->mii_stdelim, 2);
515 wb_mii_send(sc, frame->mii_opcode, 2);
516 wb_mii_send(sc, frame->mii_phyaddr, 5);
517 wb_mii_send(sc, frame->mii_regaddr, 5);
518 wb_mii_send(sc, frame->mii_turnaround, 2);
519 wb_mii_send(sc, frame->mii_data, 16);
520
521 /* Idle bit. */
522 SIO_SET(WB_SIO_MII_CLK);
523 DELAY(1);
524 SIO_CLR(WB_SIO_MII_CLK);
525 DELAY(1);
526
527 /*
528 * Turn off xmit.
529 */
530 SIO_CLR(WB_SIO_MII_DIR);
531
532 splx(s);
533
534 return(0);
535}
536
| 233
234#define WB_SETBIT(sc, reg, x) \
235 CSR_WRITE_4(sc, reg, \
236 CSR_READ_4(sc, reg) | x)
237
238#define WB_CLRBIT(sc, reg, x) \
239 CSR_WRITE_4(sc, reg, \
240 CSR_READ_4(sc, reg) & ~x)
241
242#define SIO_SET(x) \
243 CSR_WRITE_4(sc, WB_SIO, \
244 CSR_READ_4(sc, WB_SIO) | x)
245
246#define SIO_CLR(x) \
247 CSR_WRITE_4(sc, WB_SIO, \
248 CSR_READ_4(sc, WB_SIO) & ~x)
249
250/*
251 * Send a read command and address to the EEPROM, check for ACK.
252 */
253static void wb_eeprom_putbyte(sc, addr)
254 struct wb_softc *sc;
255 int addr;
256{
257 register int d, i;
258
259 d = addr | WB_EECMD_READ;
260
261 /*
262 * Feed in each bit and stobe the clock.
263 */
264 for (i = 0x400; i; i >>= 1) {
265 if (d & i) {
266 SIO_SET(WB_SIO_EE_DATAIN);
267 } else {
268 SIO_CLR(WB_SIO_EE_DATAIN);
269 }
270 DELAY(100);
271 SIO_SET(WB_SIO_EE_CLK);
272 DELAY(150);
273 SIO_CLR(WB_SIO_EE_CLK);
274 DELAY(100);
275 }
276
277 return;
278}
279
280/*
281 * Read a word of data stored in the EEPROM at address 'addr.'
282 */
283static void wb_eeprom_getword(sc, addr, dest)
284 struct wb_softc *sc;
285 int addr;
286 u_int16_t *dest;
287{
288 register int i;
289 u_int16_t word = 0;
290
291 /* Enter EEPROM access mode. */
292 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
293
294 /*
295 * Send address of word we want to read.
296 */
297 wb_eeprom_putbyte(sc, addr);
298
299 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
300
301 /*
302 * Start reading bits from EEPROM.
303 */
304 for (i = 0x8000; i; i >>= 1) {
305 SIO_SET(WB_SIO_EE_CLK);
306 DELAY(100);
307 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
308 word |= i;
309 SIO_CLR(WB_SIO_EE_CLK);
310 DELAY(100);
311 }
312
313 /* Turn off EEPROM access mode. */
314 CSR_WRITE_4(sc, WB_SIO, 0);
315
316 *dest = word;
317
318 return;
319}
320
321/*
322 * Read a sequence of words from the EEPROM.
323 */
324static void wb_read_eeprom(sc, dest, off, cnt, swap)
325 struct wb_softc *sc;
326 caddr_t dest;
327 int off;
328 int cnt;
329 int swap;
330{
331 int i;
332 u_int16_t word = 0, *ptr;
333
334 for (i = 0; i < cnt; i++) {
335 wb_eeprom_getword(sc, off + i, &word);
336 ptr = (u_int16_t *)(dest + (i * 2));
337 if (swap)
338 *ptr = ntohs(word);
339 else
340 *ptr = word;
341 }
342
343 return;
344}
345
346/*
347 * Sync the PHYs by setting data bit and strobing the clock 32 times.
348 */
349static void wb_mii_sync(sc)
350 struct wb_softc *sc;
351{
352 register int i;
353
354 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
355
356 for (i = 0; i < 32; i++) {
357 SIO_SET(WB_SIO_MII_CLK);
358 DELAY(1);
359 SIO_CLR(WB_SIO_MII_CLK);
360 DELAY(1);
361 }
362
363 return;
364}
365
366/*
367 * Clock a series of bits through the MII.
368 */
369static void wb_mii_send(sc, bits, cnt)
370 struct wb_softc *sc;
371 u_int32_t bits;
372 int cnt;
373{
374 int i;
375
376 SIO_CLR(WB_SIO_MII_CLK);
377
378 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
379 if (bits & i) {
380 SIO_SET(WB_SIO_MII_DATAIN);
381 } else {
382 SIO_CLR(WB_SIO_MII_DATAIN);
383 }
384 DELAY(1);
385 SIO_CLR(WB_SIO_MII_CLK);
386 DELAY(1);
387 SIO_SET(WB_SIO_MII_CLK);
388 }
389}
390
391/*
392 * Read an PHY register through the MII.
393 */
394static int wb_mii_readreg(sc, frame)
395 struct wb_softc *sc;
396 struct wb_mii_frame *frame;
397
398{
399 int i, ack, s;
400
401 s = splimp();
402
403 /*
404 * Set up frame for RX.
405 */
406 frame->mii_stdelim = WB_MII_STARTDELIM;
407 frame->mii_opcode = WB_MII_READOP;
408 frame->mii_turnaround = 0;
409 frame->mii_data = 0;
410
411 CSR_WRITE_4(sc, WB_SIO, 0);
412
413 /*
414 * Turn on data xmit.
415 */
416 SIO_SET(WB_SIO_MII_DIR);
417
418 wb_mii_sync(sc);
419
420 /*
421 * Send command/address info.
422 */
423 wb_mii_send(sc, frame->mii_stdelim, 2);
424 wb_mii_send(sc, frame->mii_opcode, 2);
425 wb_mii_send(sc, frame->mii_phyaddr, 5);
426 wb_mii_send(sc, frame->mii_regaddr, 5);
427
428 /* Idle bit */
429 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
430 DELAY(1);
431 SIO_SET(WB_SIO_MII_CLK);
432 DELAY(1);
433
434 /* Turn off xmit. */
435 SIO_CLR(WB_SIO_MII_DIR);
436 /* Check for ack */
437 SIO_CLR(WB_SIO_MII_CLK);
438 DELAY(1);
439 SIO_SET(WB_SIO_MII_CLK);
440 DELAY(1);
441 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
442 SIO_CLR(WB_SIO_MII_CLK);
443 DELAY(1);
444 SIO_SET(WB_SIO_MII_CLK);
445 DELAY(1);
446
447 /*
448 * Now try reading data bits. If the ack failed, we still
449 * need to clock through 16 cycles to keep the PHY(s) in sync.
450 */
451 if (ack) {
452 for(i = 0; i < 16; i++) {
453 SIO_CLR(WB_SIO_MII_CLK);
454 DELAY(1);
455 SIO_SET(WB_SIO_MII_CLK);
456 DELAY(1);
457 }
458 goto fail;
459 }
460
461 for (i = 0x8000; i; i >>= 1) {
462 SIO_CLR(WB_SIO_MII_CLK);
463 DELAY(1);
464 if (!ack) {
465 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
466 frame->mii_data |= i;
467 DELAY(1);
468 }
469 SIO_SET(WB_SIO_MII_CLK);
470 DELAY(1);
471 }
472
473fail:
474
475 SIO_CLR(WB_SIO_MII_CLK);
476 DELAY(1);
477 SIO_SET(WB_SIO_MII_CLK);
478 DELAY(1);
479
480 splx(s);
481
482 if (ack)
483 return(1);
484 return(0);
485}
486
487/*
488 * Write to a PHY register through the MII.
489 */
490static int wb_mii_writereg(sc, frame)
491 struct wb_softc *sc;
492 struct wb_mii_frame *frame;
493
494{
495 int s;
496
497 s = splimp();
498 /*
499 * Set up frame for TX.
500 */
501
502 frame->mii_stdelim = WB_MII_STARTDELIM;
503 frame->mii_opcode = WB_MII_WRITEOP;
504 frame->mii_turnaround = WB_MII_TURNAROUND;
505
506 /*
507 * Turn on data output.
508 */
509 SIO_SET(WB_SIO_MII_DIR);
510
511 wb_mii_sync(sc);
512
513 wb_mii_send(sc, frame->mii_stdelim, 2);
514 wb_mii_send(sc, frame->mii_opcode, 2);
515 wb_mii_send(sc, frame->mii_phyaddr, 5);
516 wb_mii_send(sc, frame->mii_regaddr, 5);
517 wb_mii_send(sc, frame->mii_turnaround, 2);
518 wb_mii_send(sc, frame->mii_data, 16);
519
520 /* Idle bit. */
521 SIO_SET(WB_SIO_MII_CLK);
522 DELAY(1);
523 SIO_CLR(WB_SIO_MII_CLK);
524 DELAY(1);
525
526 /*
527 * Turn off xmit.
528 */
529 SIO_CLR(WB_SIO_MII_DIR);
530
531 splx(s);
532
533 return(0);
534}
535
|
537static u_int16_t wb_phy_readreg(sc, reg)
538 struct wb_softc *sc;
539 int reg;
| 536static int wb_miibus_readreg(dev, phy, reg)
537 device_t dev;
538 int phy, reg;
|
540{
| 539{
|
| 540 struct wb_softc *sc;
|
541 struct wb_mii_frame frame;
542
| 541 struct wb_mii_frame frame;
542
|
| 543 sc = device_get_softc(dev);
544
|
543 bzero((char *)&frame, sizeof(frame));
544
| 545 bzero((char *)&frame, sizeof(frame));
546
|
545 frame.mii_phyaddr = sc->wb_phy_addr;
| 547 frame.mii_phyaddr = phy;
|
546 frame.mii_regaddr = reg;
547 wb_mii_readreg(sc, &frame);
548
549 return(frame.mii_data);
550}
551
| 548 frame.mii_regaddr = reg;
549 wb_mii_readreg(sc, &frame);
550
551 return(frame.mii_data);
552}
553
|
552static void wb_phy_writereg(sc, reg, data)
553 struct wb_softc *sc;
554 int reg;
555 int data;
| 554static int wb_miibus_writereg(dev, phy, reg, data)
555 device_t dev;
556 int phy, reg, data;
|
556{
| 557{
|
| 558 struct wb_softc *sc;
|
557 struct wb_mii_frame frame;
558
| 559 struct wb_mii_frame frame;
560
|
| 561 sc = device_get_softc(dev);
562
|
559 bzero((char *)&frame, sizeof(frame));
560
| 563 bzero((char *)&frame, sizeof(frame));
564
|
561 frame.mii_phyaddr = sc->wb_phy_addr;
| 565 frame.mii_phyaddr = phy;
|
562 frame.mii_regaddr = reg;
563 frame.mii_data = data;
564
565 wb_mii_writereg(sc, &frame);
566
| 566 frame.mii_regaddr = reg;
567 frame.mii_data = data;
568
569 wb_mii_writereg(sc, &frame);
570
|
| 571 return(0);
572}
573
574static void wb_miibus_statchg(dev)
575 device_t dev;
576{
577 struct wb_softc *sc;
578 struct mii_data *mii;
579
580 sc = device_get_softc(dev);
581 mii = device_get_softc(sc->wb_miibus);
582 wb_setcfg(sc, mii->mii_media_active);
583
|
567 return;
568}
569
570static u_int8_t wb_calchash(addr)
571 caddr_t addr;
572{
573 u_int32_t crc, carry;
574 int i, j;
575 u_int8_t c;
576
577 /* Compute CRC for the address value. */
578 crc = 0xFFFFFFFF; /* initial value */
579
580 for (i = 0; i < 6; i++) {
581 c = *(addr + i);
582 for (j = 0; j < 8; j++) {
583 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
584 crc <<= 1;
585 c >>= 1;
586 if (carry)
587 crc = (crc ^ 0x04c11db6) | carry;
588 }
589 }
590
591 /*
592 * return the filter bit position
593 * Note: I arrived at the following nonsense
594 * through experimentation. It's not the usual way to
595 * generate the bit position but it's the only thing
596 * I could come up with that works.
597 */
598 return(~(crc >> 26) & 0x0000003F);
599}
600
601/*
602 * Program the 64-bit multicast hash filter.
603 */
604static void wb_setmulti(sc)
605 struct wb_softc *sc;
606{
607 struct ifnet *ifp;
608 int h = 0;
609 u_int32_t hashes[2] = { 0, 0 };
610 struct ifmultiaddr *ifma;
611 u_int32_t rxfilt;
612 int mcnt = 0;
613
614 ifp = &sc->arpcom.ac_if;
615
616 rxfilt = CSR_READ_4(sc, WB_NETCFG);
617
618 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
619 rxfilt |= WB_NETCFG_RX_MULTI;
620 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
621 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
622 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
623 return;
624 }
625
626 /* first, zot all the existing hash bits */
627 CSR_WRITE_4(sc, WB_MAR0, 0);
628 CSR_WRITE_4(sc, WB_MAR1, 0);
629
630 /* now program new ones */
631 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
632 ifma = ifma->ifma_link.le_next) {
633 if (ifma->ifma_addr->sa_family != AF_LINK)
634 continue;
635 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
636 if (h < 32)
637 hashes[0] |= (1 << h);
638 else
639 hashes[1] |= (1 << (h - 32));
640 mcnt++;
641 }
642
643 if (mcnt)
644 rxfilt |= WB_NETCFG_RX_MULTI;
645 else
646 rxfilt &= ~WB_NETCFG_RX_MULTI;
647
648 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
649 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
650 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
651
652 return;
653}
654
655/*
| 584 return;
585}
586
587static u_int8_t wb_calchash(addr)
588 caddr_t addr;
589{
590 u_int32_t crc, carry;
591 int i, j;
592 u_int8_t c;
593
594 /* Compute CRC for the address value. */
595 crc = 0xFFFFFFFF; /* initial value */
596
597 for (i = 0; i < 6; i++) {
598 c = *(addr + i);
599 for (j = 0; j < 8; j++) {
600 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
601 crc <<= 1;
602 c >>= 1;
603 if (carry)
604 crc = (crc ^ 0x04c11db6) | carry;
605 }
606 }
607
608 /*
609 * return the filter bit position
610 * Note: I arrived at the following nonsense
611 * through experimentation. It's not the usual way to
612 * generate the bit position but it's the only thing
613 * I could come up with that works.
614 */
615 return(~(crc >> 26) & 0x0000003F);
616}
617
618/*
619 * Program the 64-bit multicast hash filter.
620 */
621static void wb_setmulti(sc)
622 struct wb_softc *sc;
623{
624 struct ifnet *ifp;
625 int h = 0;
626 u_int32_t hashes[2] = { 0, 0 };
627 struct ifmultiaddr *ifma;
628 u_int32_t rxfilt;
629 int mcnt = 0;
630
631 ifp = &sc->arpcom.ac_if;
632
633 rxfilt = CSR_READ_4(sc, WB_NETCFG);
634
635 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
636 rxfilt |= WB_NETCFG_RX_MULTI;
637 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
638 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
639 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
640 return;
641 }
642
643 /* first, zot all the existing hash bits */
644 CSR_WRITE_4(sc, WB_MAR0, 0);
645 CSR_WRITE_4(sc, WB_MAR1, 0);
646
647 /* now program new ones */
648 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
649 ifma = ifma->ifma_link.le_next) {
650 if (ifma->ifma_addr->sa_family != AF_LINK)
651 continue;
652 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
653 if (h < 32)
654 hashes[0] |= (1 << h);
655 else
656 hashes[1] |= (1 << (h - 32));
657 mcnt++;
658 }
659
660 if (mcnt)
661 rxfilt |= WB_NETCFG_RX_MULTI;
662 else
663 rxfilt &= ~WB_NETCFG_RX_MULTI;
664
665 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
666 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
667 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
668
669 return;
670}
671
672/*
|
656 * Initiate an autonegotiation session.
657 */
658static void wb_autoneg_xmit(sc)
659 struct wb_softc *sc;
660{
661 u_int16_t phy_sts;
662
663 wb_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
664 DELAY(500);
665 while(wb_phy_readreg(sc, PHY_BMCR)
666 & PHY_BMCR_RESET);
667
668 phy_sts = wb_phy_readreg(sc, PHY_BMCR);
669 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
670 wb_phy_writereg(sc, PHY_BMCR, phy_sts);
671
672 return;
673}
674
675/*
676 * Invoke autonegotiation on a PHY.
677 */
678static void wb_autoneg_mii(sc, flag, verbose)
679 struct wb_softc *sc;
680 int flag;
681 int verbose;
682{
683 u_int16_t phy_sts = 0, media, advert, ability;
684 struct ifnet *ifp;
685 struct ifmedia *ifm;
686
687 ifm = &sc->ifmedia;
688 ifp = &sc->arpcom.ac_if;
689
690 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
691
692 /*
693 * The 100baseT4 PHY on the 3c905-T4 has the 'autoneg supported'
694 * bit cleared in the status register, but has the 'autoneg enabled'
695 * bit set in the control register. This is a contradiction, and
696 * I'm not sure how to handle it. If you want to force an attempt
697 * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR
698 * and see what happens.
699 */
700#ifndef FORCE_AUTONEG_TFOUR
701 /*
702 * First, see if autoneg is supported. If not, there's
703 * no point in continuing.
704 */
705 phy_sts = wb_phy_readreg(sc, PHY_BMSR);
706 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
707 if (verbose)
708 printf("wb%d: autonegotiation not supported\n",
709 sc->wb_unit);
710 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
711 return;
712 }
713#endif
714
715 switch (flag) {
716 case WB_FLAG_FORCEDELAY:
717 /*
718 * XXX Never use this option anywhere but in the probe
719 * routine: making the kernel stop dead in its tracks
720 * for three whole seconds after we've gone multi-user
721 * is really bad manners.
722 */
723 wb_autoneg_xmit(sc);
724 DELAY(5000000);
725 break;
726 case WB_FLAG_SCHEDDELAY:
727 /*
728 * Wait for the transmitter to go idle before starting
729 * an autoneg session, otherwise wb_start() may clobber
730 * our timeout, and we don't want to allow transmission
731 * during an autoneg session since that can screw it up.
732 */
733 if (sc->wb_cdata.wb_tx_head != NULL) {
734 sc->wb_want_auto = 1;
735 return;
736 }
737 wb_autoneg_xmit(sc);
738 ifp->if_timer = 5;
739 sc->wb_autoneg = 1;
740 sc->wb_want_auto = 0;
741 return;
742 break;
743 case WB_FLAG_DELAYTIMEO:
744 ifp->if_timer = 0;
745 sc->wb_autoneg = 0;
746 break;
747 default:
748 printf("wb%d: invalid autoneg flag: %d\n", sc->wb_unit, flag);
749 return;
750 }
751
752 if (wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
753 if (verbose)
754 printf("wb%d: autoneg complete, ", sc->wb_unit);
755 phy_sts = wb_phy_readreg(sc, PHY_BMSR);
756 } else {
757 if (verbose)
758 printf("wb%d: autoneg not complete, ", sc->wb_unit);
759 }
760
761 media = wb_phy_readreg(sc, PHY_BMCR);
762
763 /* Link is good. Report modes and set duplex mode. */
764 if (wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
765 if (verbose)
766 printf("link status good ");
767 advert = wb_phy_readreg(sc, PHY_ANAR);
768 ability = wb_phy_readreg(sc, PHY_LPAR);
769
770 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
771 ifm->ifm_media = IFM_ETHER|IFM_100_T4;
772 media |= PHY_BMCR_SPEEDSEL;
773 media &= ~PHY_BMCR_DUPLEX;
774 printf("(100baseT4)\n");
775 } else if (advert & PHY_ANAR_100BTXFULL &&
776 ability & PHY_ANAR_100BTXFULL) {
777 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
778 media |= PHY_BMCR_SPEEDSEL;
779 media |= PHY_BMCR_DUPLEX;
780 printf("(full-duplex, 100Mbps)\n");
781 } else if (advert & PHY_ANAR_100BTXHALF &&
782 ability & PHY_ANAR_100BTXHALF) {
783 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
784 media |= PHY_BMCR_SPEEDSEL;
785 media &= ~PHY_BMCR_DUPLEX;
786 printf("(half-duplex, 100Mbps)\n");
787 } else if (advert & PHY_ANAR_10BTFULL &&
788 ability & PHY_ANAR_10BTFULL) {
789 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
790 media &= ~PHY_BMCR_SPEEDSEL;
791 media |= PHY_BMCR_DUPLEX;
792 printf("(full-duplex, 10Mbps)\n");
793 } else /* if (advert & PHY_ANAR_10BTHALF &&
794 ability & PHY_ANAR_10BTHALF) */ {
795 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
796 media &= ~PHY_BMCR_SPEEDSEL;
797 media &= ~PHY_BMCR_DUPLEX;
798 printf("(half-duplex, 10Mbps)\n");
799 }
800
801 media &= ~PHY_BMCR_AUTONEGENBL;
802
803 /* Set ASIC's duplex mode to match the PHY. */
804 wb_setcfg(sc, media);
805 wb_phy_writereg(sc, PHY_BMCR, media);
806 } else {
807 if (verbose)
808 printf("no carrier\n");
809 }
810
811 wb_init(sc);
812
813 if (sc->wb_tx_pend) {
814 sc->wb_autoneg = 0;
815 sc->wb_tx_pend = 0;
816 wb_start(ifp);
817 }
818
819 return;
820}
821
822static void wb_getmode_mii(sc)
823 struct wb_softc *sc;
824{
825 u_int16_t bmsr;
826 struct ifnet *ifp;
827
828 ifp = &sc->arpcom.ac_if;
829
830 bmsr = wb_phy_readreg(sc, PHY_BMSR);
831 if (bootverbose)
832 printf("wb%d: PHY status word: %x\n", sc->wb_unit, bmsr);
833
834 /* fallback */
835 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
836
837 if (bmsr & PHY_BMSR_10BTHALF) {
838 if (bootverbose)
839 printf("wb%d: 10Mbps half-duplex mode supported\n",
840 sc->wb_unit);
841 ifmedia_add(&sc->ifmedia,
842 IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
843 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
844 }
845
846 if (bmsr & PHY_BMSR_10BTFULL) {
847 if (bootverbose)
848 printf("wb%d: 10Mbps full-duplex mode supported\n",
849 sc->wb_unit);
850 ifmedia_add(&sc->ifmedia,
851 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
852 sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
853 }
854
855 if (bmsr & PHY_BMSR_100BTXHALF) {
856 if (bootverbose)
857 printf("wb%d: 100Mbps half-duplex mode supported\n",
858 sc->wb_unit);
859 ifp->if_baudrate = 100000000;
860 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
861 ifmedia_add(&sc->ifmedia,
862 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
863 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
864 }
865
866 if (bmsr & PHY_BMSR_100BTXFULL) {
867 if (bootverbose)
868 printf("wb%d: 100Mbps full-duplex mode supported\n",
869 sc->wb_unit);
870 ifp->if_baudrate = 100000000;
871 ifmedia_add(&sc->ifmedia,
872 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
873 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
874 }
875
876 /* Some also support 100BaseT4. */
877 if (bmsr & PHY_BMSR_100BT4) {
878 if (bootverbose)
879 printf("wb%d: 100baseT4 mode supported\n", sc->wb_unit);
880 ifp->if_baudrate = 100000000;
881 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL);
882 sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4;
883#ifdef FORCE_AUTONEG_TFOUR
884 if (bootverbose)
885 printf("wb%d: forcing on autoneg support for BT4\n",
886 sc->wb_unit);
887 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL):
888 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
889#endif
890 }
891
892 if (bmsr & PHY_BMSR_CANAUTONEG) {
893 if (bootverbose)
894 printf("wb%d: autoneg supported\n", sc->wb_unit);
895 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
896 sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO;
897 }
898
899 return;
900}
901
902/*
903 * Set speed and duplex mode.
904 */
905static void wb_setmode_mii(sc, media)
906 struct wb_softc *sc;
907 int media;
908{
909 u_int16_t bmcr;
910 struct ifnet *ifp;
911
912 ifp = &sc->arpcom.ac_if;
913
914 /*
915 * If an autoneg session is in progress, stop it.
916 */
917 if (sc->wb_autoneg) {
918 printf("wb%d: canceling autoneg session\n", sc->wb_unit);
919 ifp->if_timer = sc->wb_autoneg = sc->wb_want_auto = 0;
920 bmcr = wb_phy_readreg(sc, PHY_BMCR);
921 bmcr &= ~PHY_BMCR_AUTONEGENBL;
922 wb_phy_writereg(sc, PHY_BMCR, bmcr);
923 }
924
925 printf("wb%d: selecting MII, ", sc->wb_unit);
926
927 bmcr = wb_phy_readreg(sc, PHY_BMCR);
928
929 bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL|
930 PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK);
931
932 if (IFM_SUBTYPE(media) == IFM_100_T4) {
933 printf("100Mbps/T4, half-duplex\n");
934 bmcr |= PHY_BMCR_SPEEDSEL;
935 bmcr &= ~PHY_BMCR_DUPLEX;
936 }
937
938 if (IFM_SUBTYPE(media) == IFM_100_TX) {
939 printf("100Mbps, ");
940 bmcr |= PHY_BMCR_SPEEDSEL;
941 }
942
943 if (IFM_SUBTYPE(media) == IFM_10_T) {
944 printf("10Mbps, ");
945 bmcr &= ~PHY_BMCR_SPEEDSEL;
946 }
947
948 if ((media & IFM_GMASK) == IFM_FDX) {
949 printf("full duplex\n");
950 bmcr |= PHY_BMCR_DUPLEX;
951 } else {
952 printf("half duplex\n");
953 bmcr &= ~PHY_BMCR_DUPLEX;
954 }
955
956 wb_setcfg(sc, bmcr);
957 wb_phy_writereg(sc, PHY_BMCR, bmcr);
958
959 return;
960}
961
962/*
| |
963 * The Winbond manual states that in order to fiddle with the
964 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
965 * first have to put the transmit and/or receive logic in the idle state.
966 */
| 673 * The Winbond manual states that in order to fiddle with the
674 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
675 * first have to put the transmit and/or receive logic in the idle state.
676 */
|
967static void wb_setcfg(sc, bmcr)
| 677static void wb_setcfg(sc, media)
|
968 struct wb_softc *sc;
| 678 struct wb_softc *sc;
|
969 int bmcr;
| 679 u_int32_t media;
|
970{
971 int i, restart = 0;
972
973 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
974 restart = 1;
975 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
976
977 for (i = 0; i < WB_TIMEOUT; i++) {
978 DELAY(10);
979 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
980 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
981 break;
982 }
983
984 if (i == WB_TIMEOUT)
985 printf("wb%d: failed to force tx and "
986 "rx to idle state\n", sc->wb_unit);
987 }
988
| 680{
681 int i, restart = 0;
682
683 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
684 restart = 1;
685 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
686
687 for (i = 0; i < WB_TIMEOUT; i++) {
688 DELAY(10);
689 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
690 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
691 break;
692 }
693
694 if (i == WB_TIMEOUT)
695 printf("wb%d: failed to force tx and "
696 "rx to idle state\n", sc->wb_unit);
697 }
698
|
989 if (bmcr & PHY_BMCR_SPEEDSEL)
990 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
991 else
| 699 if (IFM_SUBTYPE(media) == IFM_10_T)
|
992 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
| 700 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
|
| 701 else
702 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
|
993
| 703
|
994 if (bmcr & PHY_BMCR_DUPLEX)
| 704 if ((media & IFM_GMASK) == IFM_FDX)
|
995 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
996 else
997 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
998
999 if (restart)
1000 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
1001
1002 return;
1003}
1004
1005static void wb_reset(sc)
1006 struct wb_softc *sc;
1007{
1008 register int i;
| 705 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
706 else
707 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
708
709 if (restart)
710 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
711
712 return;
713}
714
715static void wb_reset(sc)
716 struct wb_softc *sc;
717{
718 register int i;
|
| 719 struct mii_data *mii;
|
1009
| 720
|
| 721 CSR_WRITE_4(sc, WB_NETCFG, 0);
722 CSR_WRITE_4(sc, WB_BUSCTL, 0);
723 CSR_WRITE_4(sc, WB_TXADDR, 0);
724 CSR_WRITE_4(sc, WB_RXADDR, 0);
725
|
1010 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
| 726 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
|
| 727 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
|
1011
1012 for (i = 0; i < WB_TIMEOUT; i++) {
1013 DELAY(10);
1014 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
1015 break;
1016 }
1017 if (i == WB_TIMEOUT)
1018 printf("wb%d: reset never completed!\n", sc->wb_unit);
1019
1020 /* Wait a little while for the chip to get its brains in order. */
1021 DELAY(1000);
1022
| 728
729 for (i = 0; i < WB_TIMEOUT; i++) {
730 DELAY(10);
731 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
732 break;
733 }
734 if (i == WB_TIMEOUT)
735 printf("wb%d: reset never completed!\n", sc->wb_unit);
736
737 /* Wait a little while for the chip to get its brains in order. */
738 DELAY(1000);
739
|
1023 /* Reset the damn PHY too. */
1024 if (sc->wb_pinfo != NULL)
1025 wb_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
| 740 if (sc->wb_miibus == NULL)
741 return;
|
1026
| 742
|
| 743 mii = device_get_softc(sc->wb_miibus);
744 if (mii == NULL)
745 return;
746
747 if (mii->mii_instance) {
748 struct mii_softc *miisc;
749 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
750 miisc = LIST_NEXT(miisc, mii_list))
751 mii_phy_reset(miisc);
752 }
753
|
1027 return;
1028}
1029
| 754 return;
755}
756
|
| 757static void wb_fixmedia(sc)
758 struct wb_softc *sc;
759{
760 struct mii_data *mii = NULL;
761 struct ifnet *ifp;
762 u_int32_t media;
763
764 if (sc->wb_miibus == NULL)
765 return;
766
767 mii = device_get_softc(sc->wb_miibus);
768 ifp = &sc->arpcom.ac_if;
769
770 mii_pollstat(mii);
771 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
772 media = mii->mii_media_active & ~IFM_10_T;
773 media |= IFM_100_TX;
774 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
775 media = mii->mii_media_active & ~IFM_100_TX;
776 media |= IFM_10_T;
777 } else
778 return;
779
780 ifmedia_set(&mii->mii_media, media);
781
782 return;
783}
784
|
1030/*
1031 * Probe for a Winbond chip. Check the PCI vendor and device
1032 * IDs against our list and return a device name if we find a match.
1033 */
1034static int wb_probe(dev)
1035 device_t dev;
1036{
1037 struct wb_type *t;
1038
1039 t = wb_devs;
1040
1041 while(t->wb_name != NULL) {
1042 if ((pci_get_vendor(dev) == t->wb_vid) &&
1043 (pci_get_device(dev) == t->wb_did)) {
1044 device_set_desc(dev, t->wb_name);
1045 return(0);
1046 }
1047 t++;
1048 }
1049
1050 return(ENXIO);
1051}
1052
1053/*
1054 * Attach the interface. Allocate softc structures, do ifmedia
1055 * setup and ethernet/BPF attach.
1056 */
1057static int wb_attach(dev)
1058 device_t dev;
1059{
| 785/*
786 * Probe for a Winbond chip. Check the PCI vendor and device
787 * IDs against our list and return a device name if we find a match.
788 */
789static int wb_probe(dev)
790 device_t dev;
791{
792 struct wb_type *t;
793
794 t = wb_devs;
795
796 while(t->wb_name != NULL) {
797 if ((pci_get_vendor(dev) == t->wb_vid) &&
798 (pci_get_device(dev) == t->wb_did)) {
799 device_set_desc(dev, t->wb_name);
800 return(0);
801 }
802 t++;
803 }
804
805 return(ENXIO);
806}
807
808/*
809 * Attach the interface. Allocate softc structures, do ifmedia
810 * setup and ethernet/BPF attach.
811 */
812static int wb_attach(dev)
813 device_t dev;
814{
|
1060 int s, i;
| 815 int s;
|
1061 u_char eaddr[ETHER_ADDR_LEN];
1062 u_int32_t command;
1063 struct wb_softc *sc;
1064 struct ifnet *ifp;
| 816 u_char eaddr[ETHER_ADDR_LEN];
817 u_int32_t command;
818 struct wb_softc *sc;
819 struct ifnet *ifp;
|
1065 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1066 unsigned int round;
1067 caddr_t roundptr;
1068 struct wb_type *p;
1069 u_int16_t phy_vid, phy_did, phy_sts;
| |
1070 int unit, error = 0, rid;
1071
1072 s = splimp();
1073
1074 sc = device_get_softc(dev);
1075 unit = device_get_unit(dev);
| 820 int unit, error = 0, rid;
821
822 s = splimp();
823
824 sc = device_get_softc(dev);
825 unit = device_get_unit(dev);
|
1076 bzero(sc, sizeof(struct wb_softc));
| |
1077
1078 /*
1079 * Handle power management nonsense.
1080 */
1081
1082 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF;
1083 if (command == 0x01) {
1084
1085 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4);
1086 if (command & WB_PSTATE_MASK) {
1087 u_int32_t iobase, membase, irq;
1088
1089 /* Save important PCI config data. */
1090 iobase = pci_read_config(dev, WB_PCI_LOIO, 4);
1091 membase = pci_read_config(dev, WB_PCI_LOMEM, 4);
1092 irq = pci_read_config(dev, WB_PCI_INTLINE, 4);
1093
1094 /* Reset the power state. */
1095 printf("wb%d: chip is in D%d power mode "
1096 "-- setting to D0\n", unit, command & WB_PSTATE_MASK);
1097 command &= 0xFFFFFFFC;
1098 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4);
1099
1100 /* Restore PCI config data. */
1101 pci_write_config(dev, WB_PCI_LOIO, iobase, 4);
1102 pci_write_config(dev, WB_PCI_LOMEM, membase, 4);
1103 pci_write_config(dev, WB_PCI_INTLINE, irq, 4);
1104 }
1105 }
1106
1107 /*
1108 * Map control/status registers.
1109 */
1110 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
1111 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1112 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4);
1113 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
1114
1115#ifdef WB_USEIOSPACE
1116 if (!(command & PCIM_CMD_PORTEN)) {
1117 printf("wb%d: failed to enable I/O ports!\n", unit);
1118 error = ENXIO;
1119 goto fail;
1120 }
1121#else
1122 if (!(command & PCIM_CMD_MEMEN)) {
1123 printf("wb%d: failed to enable memory mapping!\n", unit);
1124 error = ENXIO;
1125 goto fail;
1126 }
1127#endif
1128
1129 rid = WB_RID;
1130 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid,
1131 0, ~0, 1, RF_ACTIVE);
1132
1133 if (sc->wb_res == NULL) {
1134 printf("wb%d: couldn't map ports/memory\n", unit);
1135 error = ENXIO;
1136 goto fail;
1137 }
1138
1139 sc->wb_btag = rman_get_bustag(sc->wb_res);
1140 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
1141
1142 /* Allocate interrupt */
1143 rid = 0;
1144 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1145 RF_SHAREABLE | RF_ACTIVE);
1146
1147 if (sc->wb_irq == NULL) {
1148 printf("wb%d: couldn't map interrupt\n", unit);
1149 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
1150 error = ENXIO;
1151 goto fail;
1152 }
1153
1154 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET,
1155 wb_intr, sc, &sc->wb_intrhand);
1156
1157 if (error) {
1158 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
1159 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
1160 printf("wb%d: couldn't set up irq\n", unit);
1161 goto fail;
1162 }
| 826
827 /*
828 * Handle power management nonsense.
829 */
830
831 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF;
832 if (command == 0x01) {
833
834 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4);
835 if (command & WB_PSTATE_MASK) {
836 u_int32_t iobase, membase, irq;
837
838 /* Save important PCI config data. */
839 iobase = pci_read_config(dev, WB_PCI_LOIO, 4);
840 membase = pci_read_config(dev, WB_PCI_LOMEM, 4);
841 irq = pci_read_config(dev, WB_PCI_INTLINE, 4);
842
843 /* Reset the power state. */
844 printf("wb%d: chip is in D%d power mode "
845 "-- setting to D0\n", unit, command & WB_PSTATE_MASK);
846 command &= 0xFFFFFFFC;
847 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4);
848
849 /* Restore PCI config data. */
850 pci_write_config(dev, WB_PCI_LOIO, iobase, 4);
851 pci_write_config(dev, WB_PCI_LOMEM, membase, 4);
852 pci_write_config(dev, WB_PCI_INTLINE, irq, 4);
853 }
854 }
855
856 /*
857 * Map control/status registers.
858 */
859 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
860 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
861 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4);
862 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
863
864#ifdef WB_USEIOSPACE
865 if (!(command & PCIM_CMD_PORTEN)) {
866 printf("wb%d: failed to enable I/O ports!\n", unit);
867 error = ENXIO;
868 goto fail;
869 }
870#else
871 if (!(command & PCIM_CMD_MEMEN)) {
872 printf("wb%d: failed to enable memory mapping!\n", unit);
873 error = ENXIO;
874 goto fail;
875 }
876#endif
877
878 rid = WB_RID;
879 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid,
880 0, ~0, 1, RF_ACTIVE);
881
882 if (sc->wb_res == NULL) {
883 printf("wb%d: couldn't map ports/memory\n", unit);
884 error = ENXIO;
885 goto fail;
886 }
887
888 sc->wb_btag = rman_get_bustag(sc->wb_res);
889 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
890
891 /* Allocate interrupt */
892 rid = 0;
893 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
894 RF_SHAREABLE | RF_ACTIVE);
895
896 if (sc->wb_irq == NULL) {
897 printf("wb%d: couldn't map interrupt\n", unit);
898 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
899 error = ENXIO;
900 goto fail;
901 }
902
903 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET,
904 wb_intr, sc, &sc->wb_intrhand);
905
906 if (error) {
907 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
908 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
909 printf("wb%d: couldn't set up irq\n", unit);
910 goto fail;
911 }
|
1163
| 912
913 /* Save the cache line size. */
914 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
915
|
1164 /* Reset the adapter. */
1165 wb_reset(sc);
1166
1167 /*
1168 * Get station address from the EEPROM.
1169 */
1170 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
1171
1172 /*
1173 * A Winbond chip was detected. Inform the world.
1174 */
1175 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":");
1176
1177 sc->wb_unit = unit;
1178 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1179
| 916 /* Reset the adapter. */
917 wb_reset(sc);
918
919 /*
920 * Get station address from the EEPROM.
921 */
922 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
923
924 /*
925 * A Winbond chip was detected. Inform the world.
926 */
927 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":");
928
929 sc->wb_unit = unit;
930 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
931
|
1180 sc->wb_ldata_ptr = malloc(sizeof(struct wb_list_data) + 8,
1181 M_DEVBUF, M_NOWAIT);
1182 if (sc->wb_ldata_ptr == NULL) {
| 932 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
933 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0);
934
935 if (sc->wb_ldata == NULL) {
|
1183 printf("wb%d: no memory for list buffers!\n", unit);
1184 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
1185 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
1186 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
1187 error = ENXIO;
1188 goto fail;
1189 }
1190
| 936 printf("wb%d: no memory for list buffers!\n", unit);
937 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
938 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
939 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
940 error = ENXIO;
941 goto fail;
942 }
943
|
1191 sc->wb_ldata = (struct wb_list_data *)sc->wb_ldata_ptr;
1192 round = (uintptr_t)sc->wb_ldata_ptr & 0xF;
1193 roundptr = sc->wb_ldata_ptr;
1194 for (i = 0; i < 8; i++) {
1195 if (round % 8) {
1196 round++;
1197 roundptr++;
1198 } else
1199 break;
1200 }
1201 sc->wb_ldata = (struct wb_list_data *)roundptr;
| |
1202 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
1203
1204 ifp = &sc->arpcom.ac_if;
1205 ifp->if_softc = sc;
1206 ifp->if_unit = unit;
1207 ifp->if_name = "wb";
1208 ifp->if_mtu = ETHERMTU;
1209 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1210 ifp->if_ioctl = wb_ioctl;
1211 ifp->if_output = ether_output;
1212 ifp->if_start = wb_start;
1213 ifp->if_watchdog = wb_watchdog;
1214 ifp->if_init = wb_init;
1215 ifp->if_baudrate = 10000000;
1216 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
1217
| 944 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
945
946 ifp = &sc->arpcom.ac_if;
947 ifp->if_softc = sc;
948 ifp->if_unit = unit;
949 ifp->if_name = "wb";
950 ifp->if_mtu = ETHERMTU;
951 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
952 ifp->if_ioctl = wb_ioctl;
953 ifp->if_output = ether_output;
954 ifp->if_start = wb_start;
955 ifp->if_watchdog = wb_watchdog;
956 ifp->if_init = wb_init;
957 ifp->if_baudrate = 10000000;
958 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
959
|
1218 if (bootverbose)
1219 printf("wb%d: probing for a PHY\n", sc->wb_unit);
1220 for (i = WB_PHYADDR_MIN; i < WB_PHYADDR_MAX + 1; i++) {
1221 if (bootverbose)
1222 printf("wb%d: checking address: %d\n",
1223 sc->wb_unit, i);
1224 sc->wb_phy_addr = i;
1225 wb_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
1226 DELAY(500);
1227 while(wb_phy_readreg(sc, PHY_BMCR)
1228 & PHY_BMCR_RESET);
1229 if ((phy_sts = wb_phy_readreg(sc, PHY_BMSR)))
1230 break;
1231 }
1232 if (phy_sts) {
1233 phy_vid = wb_phy_readreg(sc, PHY_VENID);
1234 phy_did = wb_phy_readreg(sc, PHY_DEVID);
1235 if (bootverbose)
1236 printf("wb%d: found PHY at address %d, ",
1237 sc->wb_unit, sc->wb_phy_addr);
1238 if (bootverbose)
1239 printf("vendor id: %x device id: %x\n",
1240 phy_vid, phy_did);
1241 p = wb_phys;
1242 while(p->wb_vid) {
1243 if (phy_vid == p->wb_vid &&
1244 (phy_did | 0x000F) == p->wb_did) {
1245 sc->wb_pinfo = p;
1246 break;
1247 }
1248 p++;
1249 }
1250 if (sc->wb_pinfo == NULL)
1251 sc->wb_pinfo = &wb_phys[PHY_UNKNOWN];
1252 if (bootverbose)
1253 printf("wb%d: PHY type: %s\n",
1254 sc->wb_unit, sc->wb_pinfo->wb_name);
1255 } else {
1256 printf("wb%d: MII without any phy!\n", sc->wb_unit);
| 960 /*
961 * Do MII setup.
962 */
963 if (mii_phy_probe(dev, &sc->wb_miibus,
964 wb_ifmedia_upd, wb_ifmedia_sts)) {
|
1257 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
1258 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
1259 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
1260 free(sc->wb_ldata_ptr, M_DEVBUF);
1261 error = ENXIO;
1262 goto fail;
1263 }
1264
1265 /*
| 965 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
966 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
967 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
968 free(sc->wb_ldata_ptr, M_DEVBUF);
969 error = ENXIO;
970 goto fail;
971 }
972
973 /*
|
1266 * Do ifmedia setup.
1267 */
1268 ifmedia_init(&sc->ifmedia, 0, wb_ifmedia_upd, wb_ifmedia_sts);
1269
1270 wb_getmode_mii(sc);
1271 if (cold) {
1272 wb_autoneg_mii(sc, WB_FLAG_FORCEDELAY, 1);
1273 wb_stop(sc);
1274 } else {
1275 wb_init(sc);
1276 wb_autoneg_mii(sc, WB_FLAG_SCHEDDELAY, 1);
1277 }
1278 media = sc->ifmedia.ifm_media;
1279
1280 ifmedia_set(&sc->ifmedia, media);
1281
1282 /*
| |
1283 * Call MI attach routines.
1284 */
1285 if_attach(ifp);
1286 ether_ifattach(ifp);
1287
1288#if NBPF > 0
1289 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1290#endif
1291
1292fail:
| 974 * Call MI attach routines.
975 */
976 if_attach(ifp);
977 ether_ifattach(ifp);
978
979#if NBPF > 0
980 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
981#endif
982
983fail:
|
| 984 if (error)
985 device_delete_child(dev, sc->wb_miibus);
|
1293 splx(s);
| 986 splx(s);
|
| 987
|
1294 return(error);
1295}
1296
1297static int wb_detach(dev)
1298 device_t dev;
1299{
1300 struct wb_softc *sc;
1301 struct ifnet *ifp;
1302 int s;
1303
1304 s = splimp();
1305
1306 sc = device_get_softc(dev);
1307 ifp = &sc->arpcom.ac_if;
1308
1309 wb_stop(sc);
1310 if_detach(ifp);
1311
| 988 return(error);
989}
990
991static int wb_detach(dev)
992 device_t dev;
993{
994 struct wb_softc *sc;
995 struct ifnet *ifp;
996 int s;
997
998 s = splimp();
999
1000 sc = device_get_softc(dev);
1001 ifp = &sc->arpcom.ac_if;
1002
1003 wb_stop(sc);
1004 if_detach(ifp);
1005
|
| 1006 /* Delete any miibus and phy devices attached to this interface */
1007 bus_generic_detach(dev);
1008 device_delete_child(dev, sc->wb_miibus);
1009
|
1312 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
1313 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
1314 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
1315
1316 free(sc->wb_ldata_ptr, M_DEVBUF);
| 1010 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
1011 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
1012 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
1013
1014 free(sc->wb_ldata_ptr, M_DEVBUF);
|
1317 ifmedia_removeall(&sc->ifmedia);
| |
1318
1319 splx(s);
1320
1321 return(0);
1322}
1323
1324/*
1325 * Initialize the transmit descriptors.
1326 */
1327static int wb_list_tx_init(sc)
1328 struct wb_softc *sc;
1329{
1330 struct wb_chain_data *cd;
1331 struct wb_list_data *ld;
1332 int i;
1333
1334 cd = &sc->wb_cdata;
1335 ld = sc->wb_ldata;
1336
1337 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1338 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
1339 if (i == (WB_TX_LIST_CNT - 1)) {
1340 cd->wb_tx_chain[i].wb_nextdesc =
1341 &cd->wb_tx_chain[0];
1342 } else {
1343 cd->wb_tx_chain[i].wb_nextdesc =
1344 &cd->wb_tx_chain[i + 1];
1345 }
1346 }
1347
1348 cd->wb_tx_free = &cd->wb_tx_chain[0];
1349 cd->wb_tx_tail = cd->wb_tx_head = NULL;
1350
1351 return(0);
1352}
1353
1354
1355/*
1356 * Initialize the RX descriptors and allocate mbufs for them. Note that
1357 * we arrange the descriptors in a closed ring, so that the last descriptor
1358 * points back to the first.
1359 */
1360static int wb_list_rx_init(sc)
1361 struct wb_softc *sc;
1362{
1363 struct wb_chain_data *cd;
1364 struct wb_list_data *ld;
1365 int i;
1366
1367 cd = &sc->wb_cdata;
1368 ld = sc->wb_ldata;
1369
1370 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1371 cd->wb_rx_chain[i].wb_ptr =
1372 (struct wb_desc *)&ld->wb_rx_list[i];
| 1015
1016 splx(s);
1017
1018 return(0);
1019}
1020
1021/*
1022 * Initialize the transmit descriptors.
1023 */
1024static int wb_list_tx_init(sc)
1025 struct wb_softc *sc;
1026{
1027 struct wb_chain_data *cd;
1028 struct wb_list_data *ld;
1029 int i;
1030
1031 cd = &sc->wb_cdata;
1032 ld = sc->wb_ldata;
1033
1034 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1035 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
1036 if (i == (WB_TX_LIST_CNT - 1)) {
1037 cd->wb_tx_chain[i].wb_nextdesc =
1038 &cd->wb_tx_chain[0];
1039 } else {
1040 cd->wb_tx_chain[i].wb_nextdesc =
1041 &cd->wb_tx_chain[i + 1];
1042 }
1043 }
1044
1045 cd->wb_tx_free = &cd->wb_tx_chain[0];
1046 cd->wb_tx_tail = cd->wb_tx_head = NULL;
1047
1048 return(0);
1049}
1050
1051
1052/*
1053 * Initialize the RX descriptors and allocate mbufs for them. Note that
1054 * we arrange the descriptors in a closed ring, so that the last descriptor
1055 * points back to the first.
1056 */
1057static int wb_list_rx_init(sc)
1058 struct wb_softc *sc;
1059{
1060 struct wb_chain_data *cd;
1061 struct wb_list_data *ld;
1062 int i;
1063
1064 cd = &sc->wb_cdata;
1065 ld = sc->wb_ldata;
1066
1067 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1068 cd->wb_rx_chain[i].wb_ptr =
1069 (struct wb_desc *)&ld->wb_rx_list[i];
|
| 1070 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
|
1373 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
1374 return(ENOBUFS);
1375 if (i == (WB_RX_LIST_CNT - 1)) {
1376 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
1377 ld->wb_rx_list[i].wb_next =
1378 vtophys(&ld->wb_rx_list[0]);
1379 } else {
1380 cd->wb_rx_chain[i].wb_nextdesc =
1381 &cd->wb_rx_chain[i + 1];
1382 ld->wb_rx_list[i].wb_next =
1383 vtophys(&ld->wb_rx_list[i + 1]);
1384 }
1385 }
1386
1387 cd->wb_rx_head = &cd->wb_rx_chain[0];
1388
1389 return(0);
1390}
1391
| 1071 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
1072 return(ENOBUFS);
1073 if (i == (WB_RX_LIST_CNT - 1)) {
1074 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
1075 ld->wb_rx_list[i].wb_next =
1076 vtophys(&ld->wb_rx_list[0]);
1077 } else {
1078 cd->wb_rx_chain[i].wb_nextdesc =
1079 &cd->wb_rx_chain[i + 1];
1080 ld->wb_rx_list[i].wb_next =
1081 vtophys(&ld->wb_rx_list[i + 1]);
1082 }
1083 }
1084
1085 cd->wb_rx_head = &cd->wb_rx_chain[0];
1086
1087 return(0);
1088}
1089
|
| 1090static void wb_bfree(buf, size)
1091 caddr_t buf;
1092 u_int size;
1093{
1094 return;
1095}
1096
|
1392/*
1393 * Initialize an RX descriptor and attach an MBUF cluster.
1394 */
1395static int wb_newbuf(sc, c, m)
1396 struct wb_softc *sc;
1397 struct wb_chain_onefrag *c;
1398 struct mbuf *m;
1399{
1400 struct mbuf *m_new = NULL;
1401
1402 if (m == NULL) {
1403 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1404 if (m_new == NULL) {
1405 printf("wb%d: no memory for rx "
1406 "list -- packet dropped!\n", sc->wb_unit);
1407 return(ENOBUFS);
1408 }
1409
| 1097/*
1098 * Initialize an RX descriptor and attach an MBUF cluster.
1099 */
1100static int wb_newbuf(sc, c, m)
1101 struct wb_softc *sc;
1102 struct wb_chain_onefrag *c;
1103 struct mbuf *m;
1104{
1105 struct mbuf *m_new = NULL;
1106
1107 if (m == NULL) {
1108 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1109 if (m_new == NULL) {
1110 printf("wb%d: no memory for rx "
1111 "list -- packet dropped!\n", sc->wb_unit);
1112 return(ENOBUFS);
1113 }
1114
|
1410 MCLGET(m_new, M_DONTWAIT);
1411 if (!(m_new->m_flags & M_EXT)) {
1412 printf("wb%d: no memory for rx "
1413 "list -- packet dropped!\n", sc->wb_unit);
1414 m_freem(m_new);
1415 return(ENOBUFS);
1416 }
1417 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
| 1115 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf;
1116 m_new->m_flags |= M_EXT;
1117 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
1118 m_new->m_len = WB_BUFBYTES;
1119 m_new->m_ext.ext_free = wb_bfree;
1120 m_new->m_ext.ext_ref = wb_bfree;
|
1418 } else {
1419 m_new = m;
| 1121 } else {
1122 m_new = m;
|
1420 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
| 1123 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
|
1421 m_new->m_data = m_new->m_ext.ext_buf;
1422 }
1423
1424 m_adj(m_new, sizeof(u_int64_t));
1425
1426 c->wb_mbuf = m_new;
1427 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
| 1124 m_new->m_data = m_new->m_ext.ext_buf;
1125 }
1126
1127 m_adj(m_new, sizeof(u_int64_t));
1128
1129 c->wb_mbuf = m_new;
1130 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
|
1428 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | (MCLBYTES - 1);
| 1131 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
|
1429 c->wb_ptr->wb_status = WB_RXSTAT;
1430
1431 return(0);
1432}
1433
1434/*
1435 * A frame has been uploaded: pass the resulting mbuf chain up to
1436 * the higher level protocols.
1437 */
1438static void wb_rxeof(sc)
1439 struct wb_softc *sc;
1440{
1441 struct ether_header *eh;
| 1132 c->wb_ptr->wb_status = WB_RXSTAT;
1133
1134 return(0);
1135}
1136
1137/*
1138 * A frame has been uploaded: pass the resulting mbuf chain up to
1139 * the higher level protocols.
1140 */
1141static void wb_rxeof(sc)
1142 struct wb_softc *sc;
1143{
1144 struct ether_header *eh;
|
1442 struct mbuf *m;
| 1145 struct mbuf *m = NULL;
|
1443 struct ifnet *ifp;
1444 struct wb_chain_onefrag *cur_rx;
1445 int total_len = 0;
1446 u_int32_t rxstat;
1447
1448 ifp = &sc->arpcom.ac_if;
1449
1450 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
1451 WB_RXSTAT_OWN)) {
1452 struct mbuf *m0 = NULL;
1453
1454 cur_rx = sc->wb_cdata.wb_rx_head;
1455 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
| 1146 struct ifnet *ifp;
1147 struct wb_chain_onefrag *cur_rx;
1148 int total_len = 0;
1149 u_int32_t rxstat;
1150
1151 ifp = &sc->arpcom.ac_if;
1152
1153 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
1154 WB_RXSTAT_OWN)) {
1155 struct mbuf *m0 = NULL;
1156
1157 cur_rx = sc->wb_cdata.wb_rx_head;
1158 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
|
| 1159
|
1456 m = cur_rx->wb_mbuf;
1457
| 1160 m = cur_rx->wb_mbuf;
1161
|
1458 if ((rxstat & WB_RXSTAT_MIIERR)
1459 || WB_RXBYTES(cur_rx->wb_ptr->wb_status) == 0) {
| 1162 if ((rxstat & WB_RXSTAT_MIIERR) ||
1163 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
1164 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
1165 !(rxstat & WB_RXSTAT_LASTFRAG) ||
1166 !(rxstat & WB_RXSTAT_RXCMP)) {
|
1460 ifp->if_ierrors++;
| 1167 ifp->if_ierrors++;
|
1461 wb_reset(sc);
| 1168 wb_newbuf(sc, cur_rx, m);
|
1462 printf("wb%x: receiver babbling: possible chip "
1463 "bug, forcing reset\n", sc->wb_unit);
| 1169 printf("wb%x: receiver babbling: possible chip "
1170 "bug, forcing reset\n", sc->wb_unit);
|
1464 ifp->if_flags |= IFF_OACTIVE;
1465 ifp->if_timer = 2;
| 1171 wb_fixmedia(sc);
1172 wb_reset(sc);
1173 wb_init(sc);
|
1466 return;
1467 }
1468
1469 if (rxstat & WB_RXSTAT_RXERR) {
1470 ifp->if_ierrors++;
1471 wb_newbuf(sc, cur_rx, m);
| 1174 return;
1175 }
1176
1177 if (rxstat & WB_RXSTAT_RXERR) {
1178 ifp->if_ierrors++;
1179 wb_newbuf(sc, cur_rx, m);
|
1472 continue;
| 1180 break;
|
1473 }
1474
1475 /* No errors; receive the packet. */
1476 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1477
1478 /*
1479 * XXX The Winbond chip includes the CRC with every
1480 * received frame, and there's no way to turn this
1481 * behavior off (at least, I can't find anything in
1482 * the manual that explains how to do it) so we have
1483 * to trim off the CRC manually.
1484 */
1485 total_len -= ETHER_CRC_LEN;
1486
1487 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1488 total_len + ETHER_ALIGN, 0, ifp, NULL);
1489 wb_newbuf(sc, cur_rx, m);
1490 if (m0 == NULL) {
1491 ifp->if_ierrors++;
| 1181 }
1182
1183 /* No errors; receive the packet. */
1184 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1185
1186 /*
1187 * XXX The Winbond chip includes the CRC with every
1188 * received frame, and there's no way to turn this
1189 * behavior off (at least, I can't find anything in
1190 * the manual that explains how to do it) so we have
1191 * to trim off the CRC manually.
1192 */
1193 total_len -= ETHER_CRC_LEN;
1194
1195 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1196 total_len + ETHER_ALIGN, 0, ifp, NULL);
1197 wb_newbuf(sc, cur_rx, m);
1198 if (m0 == NULL) {
1199 ifp->if_ierrors++;
|
1492 continue;
| 1200 break;
|
1493 }
1494 m_adj(m0, ETHER_ALIGN);
1495 m = m0;
1496
1497 ifp->if_ipackets++;
1498 eh = mtod(m, struct ether_header *);
1499
1500#ifdef BRIDGE
1501 if (do_bridge) {
1502 struct ifnet *bdg_ifp;
1503 bdg_ifp = bridge_in(m);
1504 if (bdg_ifp != BDG_LOCAL && bdg_ifp != BDG_DROP)
1505 bdg_forward(&m, bdg_ifp);
1506 if (((bdg_ifp != BDG_LOCAL) && (bdg_ifp != BDG_BCAST) &&
1507 (bdg_ifp != BDG_MCAST)) || bdg_ifp == BDG_DROP) {
1508 m_freem(m);
| 1201 }
1202 m_adj(m0, ETHER_ALIGN);
1203 m = m0;
1204
1205 ifp->if_ipackets++;
1206 eh = mtod(m, struct ether_header *);
1207
1208#ifdef BRIDGE
1209 if (do_bridge) {
1210 struct ifnet *bdg_ifp;
1211 bdg_ifp = bridge_in(m);
1212 if (bdg_ifp != BDG_LOCAL && bdg_ifp != BDG_DROP)
1213 bdg_forward(&m, bdg_ifp);
1214 if (((bdg_ifp != BDG_LOCAL) && (bdg_ifp != BDG_BCAST) &&
1215 (bdg_ifp != BDG_MCAST)) || bdg_ifp == BDG_DROP) {
1216 m_freem(m);
|
1509 continue;
| 1217 break;
|
1510 }
1511 }
1512#endif
1513
1514#if NBPF > 0
1515 /*
1516 * Handle BPF listeners. Let the BPF user see the packet, but
1517 * don't pass it up to the ether_input() layer unless it's
1518 * a broadcast packet, multicast packet, matches our ethernet
1519 * address or the interface is in promiscuous mode.
1520 */
1521 if (ifp->if_bpf) {
1522 bpf_mtap(ifp, m);
1523 if (ifp->if_flags & IFF_PROMISC &&
1524 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1525 ETHER_ADDR_LEN) &&
1526 (eh->ether_dhost[0] & 1) == 0)) {
1527 m_freem(m);
| 1218 }
1219 }
1220#endif
1221
1222#if NBPF > 0
1223 /*
1224 * Handle BPF listeners. Let the BPF user see the packet, but
1225 * don't pass it up to the ether_input() layer unless it's
1226 * a broadcast packet, multicast packet, matches our ethernet
1227 * address or the interface is in promiscuous mode.
1228 */
1229 if (ifp->if_bpf) {
1230 bpf_mtap(ifp, m);
1231 if (ifp->if_flags & IFF_PROMISC &&
1232 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1233 ETHER_ADDR_LEN) &&
1234 (eh->ether_dhost[0] & 1) == 0)) {
1235 m_freem(m);
|
1528 continue;
| 1236 break;
|
1529 }
1530 }
1531#endif
1532 /* Remove header from mbuf and pass it on. */
1533 m_adj(m, sizeof(struct ether_header));
1534 ether_input(ifp, eh, m);
1535 }
1536
1537 return;
1538}
1539
1540void wb_rxeoc(sc)
1541 struct wb_softc *sc;
1542{
1543 wb_rxeof(sc);
1544
1545 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1546 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1547 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1548 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1549 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1550
1551 return;
1552}
1553
1554/*
1555 * A frame was downloaded to the chip. It's safe for us to clean up
1556 * the list buffers.
1557 */
1558static void wb_txeof(sc)
1559 struct wb_softc *sc;
1560{
1561 struct wb_chain *cur_tx;
1562 struct ifnet *ifp;
1563
1564 ifp = &sc->arpcom.ac_if;
1565
1566 /* Clear the timeout timer. */
1567 ifp->if_timer = 0;
1568
1569 if (sc->wb_cdata.wb_tx_head == NULL)
1570 return;
1571
1572 /*
1573 * Go through our tx list and free mbufs for those
1574 * frames that have been transmitted.
1575 */
1576 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1577 u_int32_t txstat;
1578
1579 cur_tx = sc->wb_cdata.wb_tx_head;
1580 txstat = WB_TXSTATUS(cur_tx);
1581
1582 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1583 break;
1584
1585 if (txstat & WB_TXSTAT_TXERR) {
1586 ifp->if_oerrors++;
1587 if (txstat & WB_TXSTAT_ABORT)
1588 ifp->if_collisions++;
1589 if (txstat & WB_TXSTAT_LATECOLL)
1590 ifp->if_collisions++;
1591 }
1592
1593 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1594
1595 ifp->if_opackets++;
1596 m_freem(cur_tx->wb_mbuf);
1597 cur_tx->wb_mbuf = NULL;
1598
1599 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1600 sc->wb_cdata.wb_tx_head = NULL;
1601 sc->wb_cdata.wb_tx_tail = NULL;
1602 break;
1603 }
1604
1605 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1606 }
1607
1608 return;
1609}
1610
1611/*
1612 * TX 'end of channel' interrupt handler.
1613 */
1614static void wb_txeoc(sc)
1615 struct wb_softc *sc;
1616{
1617 struct ifnet *ifp;
1618
1619 ifp = &sc->arpcom.ac_if;
1620
1621 ifp->if_timer = 0;
1622
1623 if (sc->wb_cdata.wb_tx_head == NULL) {
1624 ifp->if_flags &= ~IFF_OACTIVE;
1625 sc->wb_cdata.wb_tx_tail = NULL;
| 1237 }
1238 }
1239#endif
1240 /* Remove header from mbuf and pass it on. */
1241 m_adj(m, sizeof(struct ether_header));
1242 ether_input(ifp, eh, m);
1243 }
1244
1245 return;
1246}
1247
1248void wb_rxeoc(sc)
1249 struct wb_softc *sc;
1250{
1251 wb_rxeof(sc);
1252
1253 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1254 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1255 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1256 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1257 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1258
1259 return;
1260}
1261
1262/*
1263 * A frame was downloaded to the chip. It's safe for us to clean up
1264 * the list buffers.
1265 */
1266static void wb_txeof(sc)
1267 struct wb_softc *sc;
1268{
1269 struct wb_chain *cur_tx;
1270 struct ifnet *ifp;
1271
1272 ifp = &sc->arpcom.ac_if;
1273
1274 /* Clear the timeout timer. */
1275 ifp->if_timer = 0;
1276
1277 if (sc->wb_cdata.wb_tx_head == NULL)
1278 return;
1279
1280 /*
1281 * Go through our tx list and free mbufs for those
1282 * frames that have been transmitted.
1283 */
1284 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1285 u_int32_t txstat;
1286
1287 cur_tx = sc->wb_cdata.wb_tx_head;
1288 txstat = WB_TXSTATUS(cur_tx);
1289
1290 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1291 break;
1292
1293 if (txstat & WB_TXSTAT_TXERR) {
1294 ifp->if_oerrors++;
1295 if (txstat & WB_TXSTAT_ABORT)
1296 ifp->if_collisions++;
1297 if (txstat & WB_TXSTAT_LATECOLL)
1298 ifp->if_collisions++;
1299 }
1300
1301 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1302
1303 ifp->if_opackets++;
1304 m_freem(cur_tx->wb_mbuf);
1305 cur_tx->wb_mbuf = NULL;
1306
1307 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1308 sc->wb_cdata.wb_tx_head = NULL;
1309 sc->wb_cdata.wb_tx_tail = NULL;
1310 break;
1311 }
1312
1313 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1314 }
1315
1316 return;
1317}
1318
1319/*
1320 * TX 'end of channel' interrupt handler.
1321 */
1322static void wb_txeoc(sc)
1323 struct wb_softc *sc;
1324{
1325 struct ifnet *ifp;
1326
1327 ifp = &sc->arpcom.ac_if;
1328
1329 ifp->if_timer = 0;
1330
1331 if (sc->wb_cdata.wb_tx_head == NULL) {
1332 ifp->if_flags &= ~IFF_OACTIVE;
1333 sc->wb_cdata.wb_tx_tail = NULL;
|
1626 if (sc->wb_want_auto)
1627 wb_autoneg_mii(sc, WB_FLAG_SCHEDDELAY, 1);
| |
1628 } else {
1629 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1630 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1631 ifp->if_timer = 5;
1632 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1633 }
1634 }
1635
1636 return;
1637}
1638
1639static void wb_intr(arg)
1640 void *arg;
1641{
1642 struct wb_softc *sc;
1643 struct ifnet *ifp;
1644 u_int32_t status;
1645
1646 sc = arg;
1647 ifp = &sc->arpcom.ac_if;
1648
1649 if (!(ifp->if_flags & IFF_UP))
1650 return;
1651
1652 /* Disable interrupts. */
1653 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1654
1655 for (;;) {
1656
1657 status = CSR_READ_4(sc, WB_ISR);
1658 if (status)
1659 CSR_WRITE_4(sc, WB_ISR, status);
1660
1661 if ((status & WB_INTRS) == 0)
1662 break;
1663
| 1334 } else {
1335 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1336 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1337 ifp->if_timer = 5;
1338 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1339 }
1340 }
1341
1342 return;
1343}
1344
1345static void wb_intr(arg)
1346 void *arg;
1347{
1348 struct wb_softc *sc;
1349 struct ifnet *ifp;
1350 u_int32_t status;
1351
1352 sc = arg;
1353 ifp = &sc->arpcom.ac_if;
1354
1355 if (!(ifp->if_flags & IFF_UP))
1356 return;
1357
1358 /* Disable interrupts. */
1359 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1360
1361 for (;;) {
1362
1363 status = CSR_READ_4(sc, WB_ISR);
1364 if (status)
1365 CSR_WRITE_4(sc, WB_ISR, status);
1366
1367 if ((status & WB_INTRS) == 0)
1368 break;
1369
|
1664 if (status & WB_ISR_RX_OK)
1665 wb_rxeof(sc);
1666
1667 if (status & WB_ISR_RX_IDLE)
1668 wb_rxeoc(sc);
1669
| |
1670 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1671 ifp->if_ierrors++;
| 1370 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1371 ifp->if_ierrors++;
|
1672#ifdef foo
1673 wb_stop(sc);
| |
1674 wb_reset(sc);
| 1372 wb_reset(sc);
|
| 1373 if (status & WB_ISR_RX_ERR)
1374 wb_fixmedia(sc);
|
1675 wb_init(sc);
| 1375 wb_init(sc);
|
1676#endif
| 1376 continue;
|
1677 }
1678
| 1377 }
1378
|
| 1379 if (status & WB_ISR_RX_OK)
1380 wb_rxeof(sc);
1381
1382 if (status & WB_ISR_RX_IDLE)
1383 wb_rxeoc(sc);
1384
|
1679 if (status & WB_ISR_TX_OK)
1680 wb_txeof(sc);
1681
1682 if (status & WB_ISR_TX_NOBUF)
1683 wb_txeoc(sc);
1684
1685 if (status & WB_ISR_TX_IDLE) {
1686 wb_txeof(sc);
1687 if (sc->wb_cdata.wb_tx_head != NULL) {
1688 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1689 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1690 }
1691 }
1692
1693 if (status & WB_ISR_TX_UNDERRUN) {
1694 ifp->if_oerrors++;
1695 wb_txeof(sc);
1696 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1697 /* Jack up TX threshold */
1698 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1699 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1700 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1701 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1702 }
1703
1704 if (status & WB_ISR_BUS_ERR) {
1705 wb_reset(sc);
1706 wb_init(sc);
1707 }
1708
1709 }
1710
1711 /* Re-enable interrupts. */
1712 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1713
1714 if (ifp->if_snd.ifq_head != NULL) {
1715 wb_start(ifp);
1716 }
1717
1718 return;
1719}
1720
| 1385 if (status & WB_ISR_TX_OK)
1386 wb_txeof(sc);
1387
1388 if (status & WB_ISR_TX_NOBUF)
1389 wb_txeoc(sc);
1390
1391 if (status & WB_ISR_TX_IDLE) {
1392 wb_txeof(sc);
1393 if (sc->wb_cdata.wb_tx_head != NULL) {
1394 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1395 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1396 }
1397 }
1398
1399 if (status & WB_ISR_TX_UNDERRUN) {
1400 ifp->if_oerrors++;
1401 wb_txeof(sc);
1402 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1403 /* Jack up TX threshold */
1404 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1405 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1406 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1407 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1408 }
1409
1410 if (status & WB_ISR_BUS_ERR) {
1411 wb_reset(sc);
1412 wb_init(sc);
1413 }
1414
1415 }
1416
1417 /* Re-enable interrupts. */
1418 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1419
1420 if (ifp->if_snd.ifq_head != NULL) {
1421 wb_start(ifp);
1422 }
1423
1424 return;
1425}
1426
|
| 1427static void wb_tick(xsc)
1428 void *xsc;
1429{
1430 struct wb_softc *sc;
1431 struct mii_data *mii;
1432
1433 sc = xsc;
1434 mii = device_get_softc(sc->wb_miibus);
1435
1436 mii_tick(mii);
1437
1438 sc->wb_stat_ch = timeout(wb_tick, sc, hz);
1439
1440 return;
1441}
1442
|
1721/*
1722 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1723 * pointers to the fragment pointers.
1724 */
1725static int wb_encap(sc, c, m_head)
1726 struct wb_softc *sc;
1727 struct wb_chain *c;
1728 struct mbuf *m_head;
1729{
1730 int frag = 0;
1731 struct wb_desc *f = NULL;
1732 int total_len;
1733 struct mbuf *m;
1734
1735 /*
1736 * Start packing the mbufs in this chain into
1737 * the fragment pointers. Stop when we run out
1738 * of fragments or hit the end of the mbuf chain.
1739 */
1740 m = m_head;
1741 total_len = 0;
1742
1743 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1744 if (m->m_len != 0) {
1745 if (frag == WB_MAXFRAGS)
1746 break;
1747 total_len += m->m_len;
1748 f = &c->wb_ptr->wb_frag[frag];
1749 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1750 if (frag == 0) {
1751 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1752 f->wb_status = 0;
1753 } else
1754 f->wb_status = WB_TXSTAT_OWN;
1755 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1756 f->wb_data = vtophys(mtod(m, vm_offset_t));
1757 frag++;
1758 }
1759 }
1760
1761 /*
1762 * Handle special case: we used up all 16 fragments,
1763 * but we have more mbufs left in the chain. Copy the
1764 * data into an mbuf cluster. Note that we don't
1765 * bother clearing the values in the other fragment
1766 * pointers/counters; it wouldn't gain us anything,
1767 * and would waste cycles.
1768 */
1769 if (m != NULL) {
1770 struct mbuf *m_new = NULL;
1771
1772 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1773 if (m_new == NULL) {
1774 printf("wb%d: no memory for tx list", sc->wb_unit);
1775 return(1);
1776 }
1777 if (m_head->m_pkthdr.len > MHLEN) {
1778 MCLGET(m_new, M_DONTWAIT);
1779 if (!(m_new->m_flags & M_EXT)) {
1780 m_freem(m_new);
1781 printf("wb%d: no memory for tx list",
1782 sc->wb_unit);
1783 return(1);
1784 }
1785 }
1786 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1787 mtod(m_new, caddr_t));
1788 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1789 m_freem(m_head);
1790 m_head = m_new;
1791 f = &c->wb_ptr->wb_frag[0];
1792 f->wb_status = 0;
1793 f->wb_data = vtophys(mtod(m_new, caddr_t));
1794 f->wb_ctl = total_len = m_new->m_len;
1795 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1796 frag = 1;
1797 }
1798
1799 if (total_len < WB_MIN_FRAMELEN) {
1800 f = &c->wb_ptr->wb_frag[frag];
1801 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1802 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1803 f->wb_ctl |= WB_TXCTL_TLINK;
1804 f->wb_status = WB_TXSTAT_OWN;
1805 frag++;
1806 }
1807
1808 c->wb_mbuf = m_head;
1809 c->wb_lastdesc = frag - 1;
1810 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1811 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1812
1813 return(0);
1814}
1815
1816/*
1817 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1818 * to the mbuf data regions directly in the transmit lists. We also save a
1819 * copy of the pointers since the transmit list fragment pointers are
1820 * physical addresses.
1821 */
1822
1823static void wb_start(ifp)
1824 struct ifnet *ifp;
1825{
1826 struct wb_softc *sc;
1827 struct mbuf *m_head = NULL;
1828 struct wb_chain *cur_tx = NULL, *start_tx;
1829
1830 sc = ifp->if_softc;
1831
| 1443/*
1444 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1445 * pointers to the fragment pointers.
1446 */
1447static int wb_encap(sc, c, m_head)
1448 struct wb_softc *sc;
1449 struct wb_chain *c;
1450 struct mbuf *m_head;
1451{
1452 int frag = 0;
1453 struct wb_desc *f = NULL;
1454 int total_len;
1455 struct mbuf *m;
1456
1457 /*
1458 * Start packing the mbufs in this chain into
1459 * the fragment pointers. Stop when we run out
1460 * of fragments or hit the end of the mbuf chain.
1461 */
1462 m = m_head;
1463 total_len = 0;
1464
1465 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1466 if (m->m_len != 0) {
1467 if (frag == WB_MAXFRAGS)
1468 break;
1469 total_len += m->m_len;
1470 f = &c->wb_ptr->wb_frag[frag];
1471 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1472 if (frag == 0) {
1473 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1474 f->wb_status = 0;
1475 } else
1476 f->wb_status = WB_TXSTAT_OWN;
1477 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1478 f->wb_data = vtophys(mtod(m, vm_offset_t));
1479 frag++;
1480 }
1481 }
1482
1483 /*
1484 * Handle special case: we used up all 16 fragments,
1485 * but we have more mbufs left in the chain. Copy the
1486 * data into an mbuf cluster. Note that we don't
1487 * bother clearing the values in the other fragment
1488 * pointers/counters; it wouldn't gain us anything,
1489 * and would waste cycles.
1490 */
1491 if (m != NULL) {
1492 struct mbuf *m_new = NULL;
1493
1494 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1495 if (m_new == NULL) {
1496 printf("wb%d: no memory for tx list", sc->wb_unit);
1497 return(1);
1498 }
1499 if (m_head->m_pkthdr.len > MHLEN) {
1500 MCLGET(m_new, M_DONTWAIT);
1501 if (!(m_new->m_flags & M_EXT)) {
1502 m_freem(m_new);
1503 printf("wb%d: no memory for tx list",
1504 sc->wb_unit);
1505 return(1);
1506 }
1507 }
1508 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1509 mtod(m_new, caddr_t));
1510 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1511 m_freem(m_head);
1512 m_head = m_new;
1513 f = &c->wb_ptr->wb_frag[0];
1514 f->wb_status = 0;
1515 f->wb_data = vtophys(mtod(m_new, caddr_t));
1516 f->wb_ctl = total_len = m_new->m_len;
1517 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1518 frag = 1;
1519 }
1520
1521 if (total_len < WB_MIN_FRAMELEN) {
1522 f = &c->wb_ptr->wb_frag[frag];
1523 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1524 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1525 f->wb_ctl |= WB_TXCTL_TLINK;
1526 f->wb_status = WB_TXSTAT_OWN;
1527 frag++;
1528 }
1529
1530 c->wb_mbuf = m_head;
1531 c->wb_lastdesc = frag - 1;
1532 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1533 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1534
1535 return(0);
1536}
1537
1538/*
1539 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1540 * to the mbuf data regions directly in the transmit lists. We also save a
1541 * copy of the pointers since the transmit list fragment pointers are
1542 * physical addresses.
1543 */
1544
1545static void wb_start(ifp)
1546 struct ifnet *ifp;
1547{
1548 struct wb_softc *sc;
1549 struct mbuf *m_head = NULL;
1550 struct wb_chain *cur_tx = NULL, *start_tx;
1551
1552 sc = ifp->if_softc;
1553
|
1832 if (sc->wb_autoneg) {
1833 sc->wb_tx_pend = 1;
1834 return;
1835 }
1836
| |
1837 /*
1838 * Check for an available queue slot. If there are none,
1839 * punt.
1840 */
1841 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1842 ifp->if_flags |= IFF_OACTIVE;
1843 return;
1844 }
1845
1846 start_tx = sc->wb_cdata.wb_tx_free;
1847
1848 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1849 IF_DEQUEUE(&ifp->if_snd, m_head);
1850 if (m_head == NULL)
1851 break;
1852
1853 /* Pick a descriptor off the free list. */
1854 cur_tx = sc->wb_cdata.wb_tx_free;
1855 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1856
1857 /* Pack the data into the descriptor. */
1858 wb_encap(sc, cur_tx, m_head);
1859
1860 if (cur_tx != start_tx)
1861 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1862
1863#if NBPF > 0
1864 /*
1865 * If there's a BPF listener, bounce a copy of this frame
1866 * to him.
1867 */
1868 if (ifp->if_bpf)
1869 bpf_mtap(ifp, cur_tx->wb_mbuf);
1870#endif
1871 }
1872
1873 /*
1874 * If there are no packets queued, bail.
1875 */
1876 if (cur_tx == NULL)
1877 return;
1878
1879 /*
1880 * Place the request for the upload interrupt
1881 * in the last descriptor in the chain. This way, if
1882 * we're chaining several packets at once, we'll only
1883 * get an interupt once for the whole chain rather than
1884 * once for each packet.
1885 */
1886 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1887 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1888 sc->wb_cdata.wb_tx_tail = cur_tx;
1889
1890 if (sc->wb_cdata.wb_tx_head == NULL) {
1891 sc->wb_cdata.wb_tx_head = start_tx;
1892 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1893 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1894 } else {
1895 /*
1896 * We need to distinguish between the case where
1897 * the own bit is clear because the chip cleared it
1898 * and where the own bit is clear because we haven't
1899 * set it yet. The magic value WB_UNSET is just some
1900 * ramdomly chosen number which doesn't have the own
1901 * bit set. When we actually transmit the frame, the
1902 * status word will have _only_ the own bit set, so
1903 * the txeoc handler will be able to tell if it needs
1904 * to initiate another transmission to flush out pending
1905 * frames.
1906 */
1907 WB_TXOWN(start_tx) = WB_UNSENT;
1908 }
1909
1910 /*
1911 * Set a timeout in case the chip goes out to lunch.
1912 */
1913 ifp->if_timer = 5;
1914
1915 return;
1916}
1917
1918static void wb_init(xsc)
1919 void *xsc;
1920{
1921 struct wb_softc *sc = xsc;
1922 struct ifnet *ifp = &sc->arpcom.ac_if;
1923 int s, i;
| 1554 /*
1555 * Check for an available queue slot. If there are none,
1556 * punt.
1557 */
1558 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1559 ifp->if_flags |= IFF_OACTIVE;
1560 return;
1561 }
1562
1563 start_tx = sc->wb_cdata.wb_tx_free;
1564
1565 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1566 IF_DEQUEUE(&ifp->if_snd, m_head);
1567 if (m_head == NULL)
1568 break;
1569
1570 /* Pick a descriptor off the free list. */
1571 cur_tx = sc->wb_cdata.wb_tx_free;
1572 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1573
1574 /* Pack the data into the descriptor. */
1575 wb_encap(sc, cur_tx, m_head);
1576
1577 if (cur_tx != start_tx)
1578 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1579
1580#if NBPF > 0
1581 /*
1582 * If there's a BPF listener, bounce a copy of this frame
1583 * to him.
1584 */
1585 if (ifp->if_bpf)
1586 bpf_mtap(ifp, cur_tx->wb_mbuf);
1587#endif
1588 }
1589
1590 /*
1591 * If there are no packets queued, bail.
1592 */
1593 if (cur_tx == NULL)
1594 return;
1595
1596 /*
1597 * Place the request for the upload interrupt
1598 * in the last descriptor in the chain. This way, if
1599 * we're chaining several packets at once, we'll only
1600 * get an interupt once for the whole chain rather than
1601 * once for each packet.
1602 */
1603 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1604 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1605 sc->wb_cdata.wb_tx_tail = cur_tx;
1606
1607 if (sc->wb_cdata.wb_tx_head == NULL) {
1608 sc->wb_cdata.wb_tx_head = start_tx;
1609 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1610 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1611 } else {
1612 /*
1613 * We need to distinguish between the case where
1614 * the own bit is clear because the chip cleared it
1615 * and where the own bit is clear because we haven't
1616 * set it yet. The magic value WB_UNSET is just some
1617 * ramdomly chosen number which doesn't have the own
1618 * bit set. When we actually transmit the frame, the
1619 * status word will have _only_ the own bit set, so
1620 * the txeoc handler will be able to tell if it needs
1621 * to initiate another transmission to flush out pending
1622 * frames.
1623 */
1624 WB_TXOWN(start_tx) = WB_UNSENT;
1625 }
1626
1627 /*
1628 * Set a timeout in case the chip goes out to lunch.
1629 */
1630 ifp->if_timer = 5;
1631
1632 return;
1633}
1634
1635static void wb_init(xsc)
1636 void *xsc;
1637{
1638 struct wb_softc *sc = xsc;
1639 struct ifnet *ifp = &sc->arpcom.ac_if;
1640 int s, i;
|
1924 u_int16_t phy_bmcr = 0;
| 1641 struct mii_data *mii;
|
1925
| 1642
|
1926 if (sc->wb_autoneg)
1927 return;
1928
| |
1929 s = splimp();
1930
| 1643 s = splimp();
1644
|
1931 if (sc->wb_pinfo != NULL)
1932 phy_bmcr = wb_phy_readreg(sc, PHY_BMCR);
| 1645 mii = device_get_softc(sc->wb_miibus);
|
1933
1934 /*
1935 * Cancel pending I/O and free all RX/TX buffers.
1936 */
1937 wb_stop(sc);
1938 wb_reset(sc);
1939
1940 sc->wb_txthresh = WB_TXTHRESH_INIT;
1941
1942 /*
1943 * Set cache alignment and burst length.
1944 */
| 1646
1647 /*
1648 * Cancel pending I/O and free all RX/TX buffers.
1649 */
1650 wb_stop(sc);
1651 wb_reset(sc);
1652
1653 sc->wb_txthresh = WB_TXTHRESH_INIT;
1654
1655 /*
1656 * Set cache alignment and burst length.
1657 */
|
| 1658#ifdef foo
|
1945 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1946 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1947 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
| 1659 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1660 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1661 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
|
| 1662#endif
|
1948
| 1663
|
| 1664 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
1665 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1666 switch(sc->wb_cachesize) {
1667 case 32:
1668 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1669 break;
1670 case 16:
1671 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1672 break;
1673 case 8:
1674 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1675 break;
1676 case 0:
1677 default:
1678 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1679 break;
1680 }
1681
|
1949 /* This doesn't tend to work too well at 100Mbps. */
1950 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1951
| 1682 /* This doesn't tend to work too well at 100Mbps. */
1683 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1684
|
1952 wb_setcfg(sc, phy_bmcr);
1953
| |
1954 /* Init our MAC address */
1955 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1956 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);
1957 }
1958
1959 /* Init circular RX list. */
1960 if (wb_list_rx_init(sc) == ENOBUFS) {
1961 printf("wb%d: initialization failed: no "
1962 "memory for rx buffers\n", sc->wb_unit);
1963 wb_stop(sc);
1964 (void)splx(s);
1965 return;
1966 }
1967
1968 /* Init TX descriptors. */
1969 wb_list_tx_init(sc);
1970
1971 /* If we want promiscuous mode, set the allframes bit. */
1972 if (ifp->if_flags & IFF_PROMISC) {
1973 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1974 } else {
1975 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1976 }
1977
1978 /*
1979 * Set capture broadcast bit to capture broadcast frames.
1980 */
1981 if (ifp->if_flags & IFF_BROADCAST) {
1982 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1983 } else {
1984 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1985 }
1986
1987 /*
1988 * Program the multicast filter, if necessary.
1989 */
1990 wb_setmulti(sc);
1991
1992 /*
1993 * Load the address of the RX list.
1994 */
1995 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1996 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1997
1998 /*
1999 * Enable interrupts.
2000 */
2001 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
2002 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
2003
2004 /* Enable receiver and transmitter. */
2005 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
2006 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
2007
2008 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
2009 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
2010 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
2011
| 1685 /* Init our MAC address */
1686 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1687 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);
1688 }
1689
1690 /* Init circular RX list. */
1691 if (wb_list_rx_init(sc) == ENOBUFS) {
1692 printf("wb%d: initialization failed: no "
1693 "memory for rx buffers\n", sc->wb_unit);
1694 wb_stop(sc);
1695 (void)splx(s);
1696 return;
1697 }
1698
1699 /* Init TX descriptors. */
1700 wb_list_tx_init(sc);
1701
1702 /* If we want promiscuous mode, set the allframes bit. */
1703 if (ifp->if_flags & IFF_PROMISC) {
1704 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1705 } else {
1706 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1707 }
1708
1709 /*
1710 * Set capture broadcast bit to capture broadcast frames.
1711 */
1712 if (ifp->if_flags & IFF_BROADCAST) {
1713 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1714 } else {
1715 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1716 }
1717
1718 /*
1719 * Program the multicast filter, if necessary.
1720 */
1721 wb_setmulti(sc);
1722
1723 /*
1724 * Load the address of the RX list.
1725 */
1726 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1727 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1728
1729 /*
1730 * Enable interrupts.
1731 */
1732 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1733 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1734
1735 /* Enable receiver and transmitter. */
1736 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1737 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1738
1739 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1740 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1741 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1742
|
2012 /* Restore state of BMCR */
2013 if (sc->wb_pinfo != NULL)
2014 wb_phy_writereg(sc, PHY_BMCR, phy_bmcr);
| 1743 mii_mediachg(mii);
|
2015
2016 ifp->if_flags |= IFF_RUNNING;
2017 ifp->if_flags &= ~IFF_OACTIVE;
2018
2019 (void)splx(s);
2020
| 1744
1745 ifp->if_flags |= IFF_RUNNING;
1746 ifp->if_flags &= ~IFF_OACTIVE;
1747
1748 (void)splx(s);
1749
|
| 1750 sc->wb_stat_ch = timeout(wb_tick, sc, hz);
1751
|
2021 return;
2022}
2023
2024/*
2025 * Set media options.
2026 */
2027static int wb_ifmedia_upd(ifp)
2028 struct ifnet *ifp;
2029{
2030 struct wb_softc *sc;
| 1752 return;
1753}
1754
1755/*
1756 * Set media options.
1757 */
1758static int wb_ifmedia_upd(ifp)
1759 struct ifnet *ifp;
1760{
1761 struct wb_softc *sc;
|
2031 struct ifmedia *ifm;
| |
2032
2033 sc = ifp->if_softc;
| 1762
1763 sc = ifp->if_softc;
|
2034 ifm = &sc->ifmedia;
| |
2035
| 1764
|
2036 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2037 return(EINVAL);
| 1765 if (ifp->if_flags & IFF_UP)
1766 wb_init(sc);
|
2038
| 1767
|
2039 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
2040 wb_autoneg_mii(sc, WB_FLAG_SCHEDDELAY, 1);
2041 else
2042 wb_setmode_mii(sc, ifm->ifm_media);
2043
| |
2044 return(0);
2045}
2046
2047/*
2048 * Report current media status.
2049 */
2050static void wb_ifmedia_sts(ifp, ifmr)
2051 struct ifnet *ifp;
2052 struct ifmediareq *ifmr;
2053{
2054 struct wb_softc *sc;
| 1768 return(0);
1769}
1770
1771/*
1772 * Report current media status.
1773 */
1774static void wb_ifmedia_sts(ifp, ifmr)
1775 struct ifnet *ifp;
1776 struct ifmediareq *ifmr;
1777{
1778 struct wb_softc *sc;
|
2055 u_int16_t advert = 0, ability = 0;
| 1779 struct mii_data *mii;
|
2056
2057 sc = ifp->if_softc;
2058
| 1780
1781 sc = ifp->if_softc;
1782
|
2059 ifmr->ifm_active = IFM_ETHER;
| 1783 mii = device_get_softc(sc->wb_miibus);
|
2060
| 1784
|
2061 if (!(wb_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
2062 if (wb_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
2063 ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
2064 else
2065 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2066 if (wb_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
2067 ifmr->ifm_active |= IFM_FDX;
2068 else
2069 ifmr->ifm_active |= IFM_HDX;
2070 return;
2071 }
| 1785 mii_pollstat(mii);
1786 ifmr->ifm_active = mii->mii_media_active;
1787 ifmr->ifm_status = mii->mii_media_status;
|
2072
| 1788
|
2073 ability = wb_phy_readreg(sc, PHY_LPAR);
2074 advert = wb_phy_readreg(sc, PHY_ANAR);
2075 if (advert & PHY_ANAR_100BT4 &&
2076 ability & PHY_ANAR_100BT4) {
2077 ifmr->ifm_active = IFM_ETHER|IFM_100_T4;
2078 } else if (advert & PHY_ANAR_100BTXFULL &&
2079 ability & PHY_ANAR_100BTXFULL) {
2080 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX;
2081 } else if (advert & PHY_ANAR_100BTXHALF &&
2082 ability & PHY_ANAR_100BTXHALF) {
2083 ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX;
2084 } else if (advert & PHY_ANAR_10BTFULL &&
2085 ability & PHY_ANAR_10BTFULL) {
2086 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX;
2087 } else if (advert & PHY_ANAR_10BTHALF &&
2088 ability & PHY_ANAR_10BTHALF) {
2089 ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX;
2090 }
2091
| |
2092 return;
2093}
2094
2095static int wb_ioctl(ifp, command, data)
2096 struct ifnet *ifp;
2097 u_long command;
2098 caddr_t data;
2099{
2100 struct wb_softc *sc = ifp->if_softc;
| 1789 return;
1790}
1791
1792static int wb_ioctl(ifp, command, data)
1793 struct ifnet *ifp;
1794 u_long command;
1795 caddr_t data;
1796{
1797 struct wb_softc *sc = ifp->if_softc;
|
| 1798 struct mii_data *mii;
|
2101 struct ifreq *ifr = (struct ifreq *) data;
2102 int s, error = 0;
2103
2104 s = splimp();
2105
2106 switch(command) {
2107 case SIOCSIFADDR:
2108 case SIOCGIFADDR:
2109 case SIOCSIFMTU:
2110 error = ether_ioctl(ifp, command, data);
2111 break;
2112 case SIOCSIFFLAGS:
2113 if (ifp->if_flags & IFF_UP) {
2114 wb_init(sc);
2115 } else {
2116 if (ifp->if_flags & IFF_RUNNING)
2117 wb_stop(sc);
2118 }
2119 error = 0;
2120 break;
2121 case SIOCADDMULTI:
2122 case SIOCDELMULTI:
2123 wb_setmulti(sc);
2124 error = 0;
2125 break;
2126 case SIOCGIFMEDIA:
2127 case SIOCSIFMEDIA:
| 1799 struct ifreq *ifr = (struct ifreq *) data;
1800 int s, error = 0;
1801
1802 s = splimp();
1803
1804 switch(command) {
1805 case SIOCSIFADDR:
1806 case SIOCGIFADDR:
1807 case SIOCSIFMTU:
1808 error = ether_ioctl(ifp, command, data);
1809 break;
1810 case SIOCSIFFLAGS:
1811 if (ifp->if_flags & IFF_UP) {
1812 wb_init(sc);
1813 } else {
1814 if (ifp->if_flags & IFF_RUNNING)
1815 wb_stop(sc);
1816 }
1817 error = 0;
1818 break;
1819 case SIOCADDMULTI:
1820 case SIOCDELMULTI:
1821 wb_setmulti(sc);
1822 error = 0;
1823 break;
1824 case SIOCGIFMEDIA:
1825 case SIOCSIFMEDIA:
|
2128 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
| 1826 mii = device_get_softc(sc->wb_miibus);
1827 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
|
2129 break;
2130 default:
2131 error = EINVAL;
2132 break;
2133 }
2134
2135 (void)splx(s);
2136
2137 return(error);
2138}
2139
2140static void wb_watchdog(ifp)
2141 struct ifnet *ifp;
2142{
2143 struct wb_softc *sc;
2144
2145 sc = ifp->if_softc;
2146
| 1828 break;
1829 default:
1830 error = EINVAL;
1831 break;
1832 }
1833
1834 (void)splx(s);
1835
1836 return(error);
1837}
1838
1839static void wb_watchdog(ifp)
1840 struct ifnet *ifp;
1841{
1842 struct wb_softc *sc;
1843
1844 sc = ifp->if_softc;
1845
|
2147 if (sc->wb_autoneg) {
2148 wb_autoneg_mii(sc, WB_FLAG_DELAYTIMEO, 1);
2149 if (!(ifp->if_flags & IFF_UP))
2150 wb_stop(sc);
2151 return;
2152 }
2153
| |
2154 ifp->if_oerrors++;
2155 printf("wb%d: watchdog timeout\n", sc->wb_unit);
| 1846 ifp->if_oerrors++;
1847 printf("wb%d: watchdog timeout\n", sc->wb_unit);
|
2156
| 1848#ifdef foo
|
2157 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
2158 printf("wb%d: no carrier - transceiver cable problem?\n",
2159 sc->wb_unit);
| 1849 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1850 printf("wb%d: no carrier - transceiver cable problem?\n",
1851 sc->wb_unit);
|
2160
| 1852#endif
|
2161 wb_stop(sc);
2162 wb_reset(sc);
2163 wb_init(sc);
2164
2165 if (ifp->if_snd.ifq_head != NULL)
2166 wb_start(ifp);
2167
2168 return;
2169}
2170
2171/*
2172 * Stop the adapter and free any mbufs allocated to the
2173 * RX and TX lists.
2174 */
2175static void wb_stop(sc)
2176 struct wb_softc *sc;
2177{
2178 register int i;
2179 struct ifnet *ifp;
2180
2181 ifp = &sc->arpcom.ac_if;
2182 ifp->if_timer = 0;
2183
| 1853 wb_stop(sc);
1854 wb_reset(sc);
1855 wb_init(sc);
1856
1857 if (ifp->if_snd.ifq_head != NULL)
1858 wb_start(ifp);
1859
1860 return;
1861}
1862
1863/*
1864 * Stop the adapter and free any mbufs allocated to the
1865 * RX and TX lists.
1866 */
1867static void wb_stop(sc)
1868 struct wb_softc *sc;
1869{
1870 register int i;
1871 struct ifnet *ifp;
1872
1873 ifp = &sc->arpcom.ac_if;
1874 ifp->if_timer = 0;
1875
|
| 1876 untimeout(wb_tick, sc, sc->wb_stat_ch);
1877
|
2184 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
2185 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
2186 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
2187 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
2188
2189 /*
2190 * Free data in the RX lists.
2191 */
2192 for (i = 0; i < WB_RX_LIST_CNT; i++) {
2193 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
2194 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
2195 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
2196 }
2197 }
2198 bzero((char *)&sc->wb_ldata->wb_rx_list,
2199 sizeof(sc->wb_ldata->wb_rx_list));
2200
2201 /*
2202 * Free the TX list buffers.
2203 */
2204 for (i = 0; i < WB_TX_LIST_CNT; i++) {
2205 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
2206 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
2207 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
2208 }
2209 }
2210
2211 bzero((char *)&sc->wb_ldata->wb_tx_list,
2212 sizeof(sc->wb_ldata->wb_tx_list));
2213
2214 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2215
2216 return;
2217}
2218
2219/*
2220 * Stop all chip I/O so that the kernel's probe routines don't
2221 * get confused by errant DMAs when rebooting.
2222 */
2223static void wb_shutdown(dev)
2224 device_t dev;
2225{
2226 struct wb_softc *sc;
2227
2228 sc = device_get_softc(dev);
2229 wb_stop(sc);
2230
2231 return;
2232}
| 1878 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
1879 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1880 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1881 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1882
1883 /*
1884 * Free data in the RX lists.
1885 */
1886 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1887 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1888 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1889 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1890 }
1891 }
1892 bzero((char *)&sc->wb_ldata->wb_rx_list,
1893 sizeof(sc->wb_ldata->wb_rx_list));
1894
1895 /*
1896 * Free the TX list buffers.
1897 */
1898 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1899 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1900 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1901 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1902 }
1903 }
1904
1905 bzero((char *)&sc->wb_ldata->wb_tx_list,
1906 sizeof(sc->wb_ldata->wb_tx_list));
1907
1908 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1909
1910 return;
1911}
1912
1913/*
1914 * Stop all chip I/O so that the kernel's probe routines don't
1915 * get confused by errant DMAs when rebooting.
1916 */
1917static void wb_shutdown(dev)
1918 device_t dev;
1919{
1920 struct wb_softc *sc;
1921
1922 sc = device_get_softc(dev);
1923 wb_stop(sc);
1924
1925 return;
1926}
|