1/* $FreeBSD: head/sys/dev/usb/controller/xhci.c 251249 2013-06-02 10:54:47Z hselasky $ */
2/*-
3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.

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1540 USB_BUS_UNLOCK(&sc->sc_bus);
1541}
1542
1543static void
1544xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1545{
1546 struct usb_page_search buf_res;
1547 struct xhci_td *td;
1548 struct xhci_td *td_next;
1549 struct xhci_td *td_alt_next;
1550 uint32_t buf_offset;
1551 uint32_t average;
1552 uint32_t len_old;
1553 uint32_t dword;
1554 uint8_t shortpkt_old;
1555 uint8_t precompute;
1556 uint8_t x;
1557
1558 td_alt_next = NULL;
1559 buf_offset = 0;
1560 shortpkt_old = temp->shortpkt;
1561 len_old = temp->len;
1562 precompute = 1;
1563
1564restart:
1565
1566 td = temp->td;
1567 td_next = temp->td_next;
1568
1569 while (1) {
1570
1571 if (temp->len == 0) {
1572
1573 if (temp->shortpkt)
1574 break;
1575

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1693
1694 dword =
1695 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1696 XHCI_TRB_2_TDSZ_SET(npkt) |
1697 XHCI_TRB_2_IRQ_SET(0);
1698
1699 td->td_trb[x].dwTrb2 = htole32(dword);
1700
1701 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1702 XHCI_TRB_3_TYPE_SET(temp->trb_type) |
1703 XHCI_TRB_3_TBC_SET(temp->tbc) |
1704 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1705
1706 if (temp->trb_type == XHCI_TRB_TYPE_ISOCH) {
1707 if (temp->do_isoc_sync != 0) {
1708 temp->do_isoc_sync = 0;
1709 dword |= XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);

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1756 /* this field will get updated later */
1757 DPRINTF("NOLINK\n");
1758 }
1759
1760 dword = XHCI_TRB_2_IRQ_SET(0);
1761
1762 td->td_trb[x].dwTrb2 = htole32(dword);
1763
1764 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1765 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT;
1766
1767 td->td_trb[x].dwTrb3 = htole32(dword);
1768
1769 td->alt_next = td_alt_next;
1770#ifdef USB_DEBUG
1771 xhci_dump_trb(&td->td_trb[x]);
1772#endif
1773 usb_pc_cpu_flush(td->page_cache);

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1785 }
1786
1787 /* restore */
1788 temp->shortpkt = shortpkt_old;
1789 temp->len = len_old;
1790 goto restart;
1791 }
1792
1793 /* remove cycle bit from first if we are stepping the TRBs */
1794 if (temp->step_td)
1795 td->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1796
1797 /* remove chain bit because this is the last TRB in the chain */
1798 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1799 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1800
1801 usb_pc_cpu_flush(td->page_cache);
1802
1803 temp->td = td;

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2650 }
2651}
2652
2653static usb_error_t
2654xhci_transfer_insert(struct usb_xfer *xfer)
2655{
2656 struct xhci_td *td_first;
2657 struct xhci_td *td_last;
2658 struct xhci_endpoint_ext *pepext;
2659 uint64_t addr;
2660 usb_stream_t id;
2661 uint8_t i;
2662 uint8_t inext;
2663 uint8_t trb_limit;
2664
2665 DPRINTFN(8, "\n");

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2725
2726 /* offset for stream */
2727 i += id * XHCI_MAX_TRANSFERS;
2728 inext += id * XHCI_MAX_TRANSFERS;
2729
2730 /* compute terminating return address */
2731 addr += (inext * sizeof(struct xhci_trb));
2732
2733 /* update next pointer of last link TRB */
2734 td_last->td_trb[td_last->ntrb].qwTrb0 = htole64(addr);
2735 td_last->td_trb[td_last->ntrb].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2736 td_last->td_trb[td_last->ntrb].dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2737 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2738
2739#ifdef USB_DEBUG
2740 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2741#endif
2742 usb_pc_cpu_flush(td_last->page_cache);
2743
2744 /* write ahead chain end marker */
2745

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