1/* $FreeBSD: head/sys/dev/usb/controller/xhci.c 251251 2013-06-02 11:58:31Z hselasky $ */
2/*-
3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.

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1540 USB_BUS_UNLOCK(&sc->sc_bus);
1541}
1542
1543static void
1544xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1545{
1546 struct usb_page_search buf_res;
1547 struct xhci_td *td;
1548 struct xhci_td *td_first;
1549 struct xhci_td *td_next;
1550 struct xhci_td *td_alt_next;
1551 uint32_t buf_offset;
1552 uint32_t average;
1553 uint32_t len_old;
1554 uint32_t dword;
1555 uint8_t shortpkt_old;
1556 uint8_t precompute;
1557 uint8_t x;
1558
1559 td_alt_next = NULL;
1560 buf_offset = 0;
1561 shortpkt_old = temp->shortpkt;
1562 len_old = temp->len;
1563 precompute = 1;
1564
1565restart:
1566
1567 td = temp->td;
1568 td_next = td_first = temp->td_next;
1569
1570 while (1) {
1571
1572 if (temp->len == 0) {
1573
1574 if (temp->shortpkt)
1575 break;
1576

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1694
1695 dword =
1696 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1697 XHCI_TRB_2_TDSZ_SET(npkt) |
1698 XHCI_TRB_2_IRQ_SET(0);
1699
1700 td->td_trb[x].dwTrb2 = htole32(dword);
1701
1702 /* BEI: Interrupts are inhibited until EOT */
1703 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1704 XHCI_TRB_3_BEI_BIT |
1705 XHCI_TRB_3_TYPE_SET(temp->trb_type) |
1706 XHCI_TRB_3_TBC_SET(temp->tbc) |
1707 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1708
1709 if (temp->trb_type == XHCI_TRB_TYPE_ISOCH) {
1710 if (temp->do_isoc_sync != 0) {
1711 temp->do_isoc_sync = 0;
1712 dword |= XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);

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1759 /* this field will get updated later */
1760 DPRINTF("NOLINK\n");
1761 }
1762
1763 dword = XHCI_TRB_2_IRQ_SET(0);
1764
1765 td->td_trb[x].dwTrb2 = htole32(dword);
1766
1767 /* BEI: interrupts are inhibited until EOT */
1768 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1769 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1770 XHCI_TRB_3_BEI_BIT;
1771
1772 td->td_trb[x].dwTrb3 = htole32(dword);
1773
1774 td->alt_next = td_alt_next;
1775#ifdef USB_DEBUG
1776 xhci_dump_trb(&td->td_trb[x]);
1777#endif
1778 usb_pc_cpu_flush(td->page_cache);

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1790 }
1791
1792 /* restore */
1793 temp->shortpkt = shortpkt_old;
1794 temp->len = len_old;
1795 goto restart;
1796 }
1797
1798 /* need to force an interrupt if we are stepping the TRBs */
1799 if ((temp->direction & UE_DIR_IN) != 0 && temp->multishort == 0) {
1800 /* remove cycle bit from first TRB if we are stepping them */
1801 if (temp->step_td)
1802 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1803 /* make sure the last LINK event generates an interrupt */
1804 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_BEI_BIT);
1805 }
1806
1807 /* remove chain bit because this is the last TRB in the chain */
1808 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1809 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1810
1811 usb_pc_cpu_flush(td->page_cache);
1812
1813 temp->td = td;

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2660 }
2661}
2662
2663static usb_error_t
2664xhci_transfer_insert(struct usb_xfer *xfer)
2665{
2666 struct xhci_td *td_first;
2667 struct xhci_td *td_last;
2668 struct xhci_trb *trb_link;
2669 struct xhci_endpoint_ext *pepext;
2670 uint64_t addr;
2671 usb_stream_t id;
2672 uint8_t i;
2673 uint8_t inext;
2674 uint8_t trb_limit;
2675
2676 DPRINTFN(8, "\n");

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2736
2737 /* offset for stream */
2738 i += id * XHCI_MAX_TRANSFERS;
2739 inext += id * XHCI_MAX_TRANSFERS;
2740
2741 /* compute terminating return address */
2742 addr += (inext * sizeof(struct xhci_trb));
2743
2744 /* compute link TRB pointer */
2745 trb_link = td_last->td_trb + td_last->ntrb;
2746
2747 /* update next pointer of last link TRB */
2748 trb_link->qwTrb0 = htole64(addr);
2749 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2750 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2751 XHCI_TRB_3_CYCLE_BIT |
2752 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2753
2754#ifdef USB_DEBUG
2755 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2756#endif
2757 usb_pc_cpu_flush(td_last->page_cache);
2758
2759 /* write ahead chain end marker */
2760

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