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uart_dev_sab82532.c (119866) uart_dev_sab82532.c (120143)
1/*
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

--- 11 unchanged lines hidden (view full) ---

20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
1/*
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

--- 11 unchanged lines hidden (view full) ---

20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_sab82532.c 119866 2003-09-07 21:51:03Z marcel $");
28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_sab82532.c 120143 2003-09-17 01:41:21Z marcel $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/conf.h>
34#include <machine/bus.h>
35
36#include <dev/uart/uart.h>

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420 uart_barrier(bas);
421 return (0);
422}
423
424static int
425sab82532_bus_flush(struct uart_softc *sc, int what)
426{
427
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/conf.h>
34#include <machine/bus.h>
35
36#include <dev/uart/uart.h>

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420 uart_barrier(bas);
421 return (0);
422}
423
424static int
425sab82532_bus_flush(struct uart_softc *sc, int what)
426{
427
428 mtx_lock_spin(&sc->sc_hwmtx);
428 sab82532_flush(&sc->sc_bas, what);
429 sab82532_flush(&sc->sc_bas, what);
430 mtx_unlock_spin(&sc->sc_hwmtx);
429 return (0);
430}
431
432static int
433sab82532_bus_getsig(struct uart_softc *sc)
434{
435 struct uart_bas *bas;
436 uint32_t new, old, sig;
437 uint8_t pvr, star, vstr;
438
439 bas = &sc->sc_bas;
440 do {
441 old = sc->sc_hwsig;
442 sig = old;
431 return (0);
432}
433
434static int
435sab82532_bus_getsig(struct uart_softc *sc)
436{
437 struct uart_bas *bas;
438 uint32_t new, old, sig;
439 uint8_t pvr, star, vstr;
440
441 bas = &sc->sc_bas;
442 do {
443 old = sc->sc_hwsig;
444 sig = old;
445 mtx_lock_spin(&sc->sc_hwmtx);
443 star = uart_getreg(bas, SAB_STAR);
444 SIGCHG(star & SAB_STAR_CTS, sig, UART_SIG_CTS, UART_SIG_DCTS);
445 vstr = uart_getreg(bas, SAB_VSTR);
446 SIGCHG(vstr & SAB_VSTR_CD, sig, UART_SIG_DCD, UART_SIG_DDCD);
447 pvr = uart_getreg(bas, SAB_PVR);
448 pvr &= (IS_CHANNEL_A(bas)) ? SAB_PVR_DSR_A : SAB_PVR_DSR_B;
449 SIGCHG(~pvr, sig, UART_SIG_DSR, UART_SIG_DDSR);
446 star = uart_getreg(bas, SAB_STAR);
447 SIGCHG(star & SAB_STAR_CTS, sig, UART_SIG_CTS, UART_SIG_DCTS);
448 vstr = uart_getreg(bas, SAB_VSTR);
449 SIGCHG(vstr & SAB_VSTR_CD, sig, UART_SIG_DCD, UART_SIG_DDCD);
450 pvr = uart_getreg(bas, SAB_PVR);
451 pvr &= (IS_CHANNEL_A(bas)) ? SAB_PVR_DSR_A : SAB_PVR_DSR_B;
452 SIGCHG(~pvr, sig, UART_SIG_DSR, UART_SIG_DDSR);
453 mtx_unlock_spin(&sc->sc_hwmtx);
450 new = sig & ~UART_SIGMASK_DELTA;
451 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
452 return (sig);
453}
454
455static int
456sab82532_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
457{
458 struct uart_bas *bas;
459 uint8_t dafo, mode;
454 new = sig & ~UART_SIGMASK_DELTA;
455 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
456 return (sig);
457}
458
459static int
460sab82532_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
461{
462 struct uart_bas *bas;
463 uint8_t dafo, mode;
464 int error;
460
461 bas = &sc->sc_bas;
465
466 bas = &sc->sc_bas;
467 error = 0;
468 mtx_lock_spin(&sc->sc_hwmtx);
462 switch (request) {
463 case UART_IOCTL_BREAK:
464 dafo = uart_getreg(bas, SAB_DAFO);
465 if (data)
466 dafo |= SAB_DAFO_XBRK;
467 else
468 dafo &= ~SAB_DAFO_XBRK;
469 uart_setreg(bas, SAB_DAFO, dafo);

--- 16 unchanged lines hidden (view full) ---

486 if (data)
487 mode &= ~SAB_MODE_FCTS;
488 else
489 mode |= SAB_MODE_FCTS;
490 uart_setreg(bas, SAB_MODE, mode);
491 uart_barrier(bas);
492 break;
493 default:
469 switch (request) {
470 case UART_IOCTL_BREAK:
471 dafo = uart_getreg(bas, SAB_DAFO);
472 if (data)
473 dafo |= SAB_DAFO_XBRK;
474 else
475 dafo &= ~SAB_DAFO_XBRK;
476 uart_setreg(bas, SAB_DAFO, dafo);

--- 16 unchanged lines hidden (view full) ---

493 if (data)
494 mode &= ~SAB_MODE_FCTS;
495 else
496 mode |= SAB_MODE_FCTS;
497 uart_setreg(bas, SAB_MODE, mode);
498 uart_barrier(bas);
499 break;
500 default:
494 return (EINVAL);
501 error = EINVAL;
502 break;
495 }
503 }
496 return (0);
504 mtx_unlock_spin(&sc->sc_hwmtx);
505 return (error);
497}
498
499static int
500sab82532_bus_ipend(struct uart_softc *sc)
501{
502 struct uart_bas *bas;
503 int ipend;
504 uint8_t isr0, isr1;
505
506 bas = &sc->sc_bas;
506}
507
508static int
509sab82532_bus_ipend(struct uart_softc *sc)
510{
511 struct uart_bas *bas;
512 int ipend;
513 uint8_t isr0, isr1;
514
515 bas = &sc->sc_bas;
516 mtx_lock_spin(&sc->sc_hwmtx);
507 isr0 = uart_getreg(bas, SAB_ISR0);
508 isr1 = uart_getreg(bas, SAB_ISR1);
509 uart_barrier(bas);
517 isr0 = uart_getreg(bas, SAB_ISR0);
518 isr1 = uart_getreg(bas, SAB_ISR1);
519 uart_barrier(bas);
510
511 if (isr0 & SAB_ISR0_TIME) {
512 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
513 ;
514 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD);
515 uart_barrier(bas);
516 }
520 if (isr0 & SAB_ISR0_TIME) {
521 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
522 ;
523 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RFRD);
524 uart_barrier(bas);
525 }
526 mtx_unlock_spin(&sc->sc_hwmtx);
517
518 ipend = 0;
519 if (isr1 & SAB_ISR1_BRKT)
520 ipend |= UART_IPEND_BREAK;
521 if (isr0 & SAB_ISR0_RFO)
522 ipend |= UART_IPEND_OVERRUN;
523 if (isr0 & (SAB_ISR0_TCD|SAB_ISR0_RPF))
524 ipend |= UART_IPEND_RXREADY;

--- 5 unchanged lines hidden (view full) ---

530 return (ipend);
531}
532
533static int
534sab82532_bus_param(struct uart_softc *sc, int baudrate, int databits,
535 int stopbits, int parity)
536{
537 struct uart_bas *bas;
527
528 ipend = 0;
529 if (isr1 & SAB_ISR1_BRKT)
530 ipend |= UART_IPEND_BREAK;
531 if (isr0 & SAB_ISR0_RFO)
532 ipend |= UART_IPEND_OVERRUN;
533 if (isr0 & (SAB_ISR0_TCD|SAB_ISR0_RPF))
534 ipend |= UART_IPEND_RXREADY;

--- 5 unchanged lines hidden (view full) ---

540 return (ipend);
541}
542
543static int
544sab82532_bus_param(struct uart_softc *sc, int baudrate, int databits,
545 int stopbits, int parity)
546{
547 struct uart_bas *bas;
548 int error;
538
539 bas = &sc->sc_bas;
549
550 bas = &sc->sc_bas;
540 return (sab82532_param(bas, baudrate, databits, stopbits, parity));
551 mtx_lock_spin(&sc->sc_hwmtx);
552 error = sab82532_param(bas, baudrate, databits, stopbits, parity);
553 mtx_unlock_spin(&sc->sc_hwmtx);
554 return (error);
541}
542
543static int
544sab82532_bus_probe(struct uart_softc *sc)
545{
546 char buf[80];
547 const char *ch, *vstr;
548 int error;

--- 30 unchanged lines hidden (view full) ---

579static int
580sab82532_bus_receive(struct uart_softc *sc)
581{
582 struct uart_bas *bas;
583 int i, rbcl, xc;
584 uint8_t s;
585
586 bas = &sc->sc_bas;
555}
556
557static int
558sab82532_bus_probe(struct uart_softc *sc)
559{
560 char buf[80];
561 const char *ch, *vstr;
562 int error;

--- 30 unchanged lines hidden (view full) ---

593static int
594sab82532_bus_receive(struct uart_softc *sc)
595{
596 struct uart_bas *bas;
597 int i, rbcl, xc;
598 uint8_t s;
599
600 bas = &sc->sc_bas;
601 mtx_lock_spin(&sc->sc_hwmtx);
587 if (uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) {
588 rbcl = uart_getreg(bas, SAB_RBCL) & 31;
589 if (rbcl == 0)
590 rbcl = 32;
591 for (i = 0; i < rbcl; i += 2) {
592 if (uart_rx_full(sc)) {
593 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
594 break;

--- 7 unchanged lines hidden (view full) ---

602 uart_rx_put(sc, xc);
603 }
604 }
605
606 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
607 ;
608 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC);
609 uart_barrier(bas);
602 if (uart_getreg(bas, SAB_STAR) & SAB_STAR_RFNE) {
603 rbcl = uart_getreg(bas, SAB_RBCL) & 31;
604 if (rbcl == 0)
605 rbcl = 32;
606 for (i = 0; i < rbcl; i += 2) {
607 if (uart_rx_full(sc)) {
608 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
609 break;

--- 7 unchanged lines hidden (view full) ---

617 uart_rx_put(sc, xc);
618 }
619 }
620
621 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
622 ;
623 uart_setreg(bas, SAB_CMDR, SAB_CMDR_RMC);
624 uart_barrier(bas);
625 mtx_unlock_spin(&sc->sc_hwmtx);
610 return (0);
611}
612
613static int
614sab82532_bus_setsig(struct uart_softc *sc, int sig)
615{
616 struct uart_bas *bas;
617 uint32_t new, old;

--- 8 unchanged lines hidden (view full) ---

626 UART_SIG_DDTR);
627 }
628 if (sig & UART_SIG_DRTS) {
629 SIGCHG(sig & UART_SIG_RTS, new, UART_SIG_RTS,
630 UART_SIG_DRTS);
631 }
632 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
633
626 return (0);
627}
628
629static int
630sab82532_bus_setsig(struct uart_softc *sc, int sig)
631{
632 struct uart_bas *bas;
633 uint32_t new, old;

--- 8 unchanged lines hidden (view full) ---

642 UART_SIG_DDTR);
643 }
644 if (sig & UART_SIG_DRTS) {
645 SIGCHG(sig & UART_SIG_RTS, new, UART_SIG_RTS,
646 UART_SIG_DRTS);
647 }
648 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
649
650 mtx_lock_spin(&sc->sc_hwmtx);
634 /* Set DTR pin. */
635 pvr = uart_getreg(bas, SAB_PVR);
636 if (new & UART_SIG_DTR)
637 pvr &= (IS_CHANNEL_A(bas)) ? ~SAB_PVR_DTR_A : ~SAB_PVR_DTR_B;
638 else
639 pvr |= (IS_CHANNEL_A(bas)) ? SAB_PVR_DTR_A : SAB_PVR_DTR_B;
640 uart_setreg(bas, SAB_PVR, pvr);
641
642 /* Set RTS pin. */
643 mode = uart_getreg(bas, SAB_MODE);
644 if (new & UART_SIG_RTS)
645 mode &= ~SAB_MODE_FRTS;
646 else
647 mode |= SAB_MODE_FRTS;
648 uart_setreg(bas, SAB_MODE, mode);
649 uart_barrier(bas);
651 /* Set DTR pin. */
652 pvr = uart_getreg(bas, SAB_PVR);
653 if (new & UART_SIG_DTR)
654 pvr &= (IS_CHANNEL_A(bas)) ? ~SAB_PVR_DTR_A : ~SAB_PVR_DTR_B;
655 else
656 pvr |= (IS_CHANNEL_A(bas)) ? SAB_PVR_DTR_A : SAB_PVR_DTR_B;
657 uart_setreg(bas, SAB_PVR, pvr);
658
659 /* Set RTS pin. */
660 mode = uart_getreg(bas, SAB_MODE);
661 if (new & UART_SIG_RTS)
662 mode &= ~SAB_MODE_FRTS;
663 else
664 mode |= SAB_MODE_FRTS;
665 uart_setreg(bas, SAB_MODE, mode);
666 uart_barrier(bas);
667 mtx_unlock_spin(&sc->sc_hwmtx);
650 return (0);
651}
652
653static int
654sab82532_bus_transmit(struct uart_softc *sc)
655{
656 struct uart_bas *bas;
657 int i;
658
659 bas = &sc->sc_bas;
668 return (0);
669}
670
671static int
672sab82532_bus_transmit(struct uart_softc *sc)
673{
674 struct uart_bas *bas;
675 int i;
676
677 bas = &sc->sc_bas;
678 mtx_lock_spin(&sc->sc_hwmtx);
660 while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_XFW))
661 ;
662 for (i = 0; i < sc->sc_txdatasz; i++)
663 uart_setreg(bas, SAB_XFIFO + i, sc->sc_txbuf[i]);
664 uart_barrier(bas);
665 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
666 ;
667 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XF);
668 sc->sc_txbusy = 1;
679 while (!(uart_getreg(bas, SAB_STAR) & SAB_STAR_XFW))
680 ;
681 for (i = 0; i < sc->sc_txdatasz; i++)
682 uart_setreg(bas, SAB_XFIFO + i, sc->sc_txbuf[i]);
683 uart_barrier(bas);
684 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC)
685 ;
686 uart_setreg(bas, SAB_CMDR, SAB_CMDR_XF);
687 sc->sc_txbusy = 1;
688 mtx_unlock_spin(&sc->sc_hwmtx);
669 return (0);
670}
689 return (0);
690}