1/*-
2 * Copyright (c) 2014 Ganbold Tsagaankhuu <ganbold@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
| 1/*-
2 * Copyright (c) 2014 Ganbold Tsagaankhuu <ganbold@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
|
27 */
28
29#ifndef _UART_DM_H_
30#define _UART_DM_H_
31
32#define UART_DM_EXTR_BITS(value, start_pos, end_pos) \
33 ((value << (32 - end_pos)) >> (32 - (end_pos - start_pos)))
34
35/* UART Parity Mode */
36enum UART_DM_PARITY_MODE {
37 UART_DM_NO_PARITY,
38 UART_DM_ODD_PARITY,
39 UART_DM_EVEN_PARITY,
40 UART_DM_SPACE_PARITY
41};
42
43/* UART Stop Bit Length */
44enum UART_DM_STOP_BIT_LEN {
45 UART_DM_SBL_9_16,
46 UART_DM_SBL_1,
47 UART_DM_SBL_1_9_16,
48 UART_DM_SBL_2
49};
50
51/* UART Bits per Char */
52enum UART_DM_BITS_PER_CHAR {
53 UART_DM_5_BPS,
54 UART_DM_6_BPS,
55 UART_DM_7_BPS,
56 UART_DM_8_BPS
57};
58
59/* 8-N-1 Configuration */
60#define UART_DM_8_N_1_MODE (UART_DM_NO_PARITY | \
61 (UART_DM_SBL_1 << 2) | \
62 (UART_DM_8_BPS << 4))
63
64/* UART_DM Registers */
65
66/* UART Operational Mode Registers (HSUART) */
67#define UART_DM_MR1 0x00
68#define UART_DM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00
69#define UART_DM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f
70#define UART_DM_MR1_CTS_CTL_BMSK 0x40
71#define UART_DM_MR1_RX_RDY_CTL_BMSK 0x80
72
73#define UART_DM_MR2 0x04
74#define UART_DM_MR2_ERROR_MODE_BMSK 0x40
75#define UART_DM_MR2_BITS_PER_CHAR_BMSK 0x30
76#define UART_DM_MR2_STOP_BIT_LEN_BMSK 0x0c
77#define UART_DM_MR2_PARITY_MODE_BMSK 0x03
78#define UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8)
79#define UART_DM_LOOPBACK (1 << 7)
80
81/* UART Clock Selection Register, write only */
82#define UART_DM_CSR 0x08
83#define UART_DM_CSR_115200 0xff
84#define UART_DM_CSR_57600 0xee
85#define UART_DM_CSR_38400 0xdd
86#define UART_DM_CSR_28800 0xcc
87#define UART_DM_CSR_19200 0xbb
88#define UART_DM_CSR_14400 0xaa
89#define UART_DM_CSR_9600 0x99
90#define UART_DM_CSR_7200 0x88
91#define UART_DM_CSR_4800 0x77
92#define UART_DM_CSR_3600 0x66
93#define UART_DM_CSR_2400 0x55
94#define UART_DM_CSR_1200 0x44
95#define UART_DM_CSR_600 0x33
96#define UART_DM_CSR_300 0x22
97#define UART_DM_CSR_150 0x11
98#define UART_DM_CSR_75 0x00
99
100/* UART DM TX FIFO Registers - 4, write only */
101#define UART_DM_TF(x) (0x70 + (4 * (x)))
102
103/* UART Command Register, write only */
104#define UART_DM_CR 0x10
105#define UART_DM_CR_RX_ENABLE (1 << 0)
106#define UART_DM_CR_RX_DISABLE (1 << 1)
107#define UART_DM_CR_TX_ENABLE (1 << 2)
108#define UART_DM_CR_TX_DISABLE (1 << 3)
109
110/* UART_DM_CR channel command bit value (register field is bits 8:4) */
111#define UART_DM_RESET_RX 0x10
112#define UART_DM_RESET_TX 0x20
113#define UART_DM_RESET_ERROR_STATUS 0x30
114#define UART_DM_RESET_BREAK_INT 0x40
115#define UART_DM_START_BREAK 0x50
116#define UART_DM_STOP_BREAK 0x60
117#define UART_DM_RESET_CTS 0x70
118#define UART_DM_RESET_STALE_INT 0x80
119#define UART_DM_RFR_LOW 0xD0
120#define UART_DM_RFR_HIGH 0xE0
121#define UART_DM_CR_PROTECTION_EN 0x100
122#define UART_DM_STALE_EVENT_ENABLE 0x500
123#define UART_DM_STALE_EVENT_DISABLE 0x600
124#define UART_DM_FORCE_STALE_EVENT 0x400
125#define UART_DM_CLEAR_TX_READY 0x300
126#define UART_DM_RESET_TX_ERROR 0x800
127#define UART_DM_RESET_TX_DONE 0x810
128
129/* UART Interrupt Mask Register */
130#define UART_DM_IMR 0x14
131/* these can be used for both ISR and IMR registers */
132#define UART_DM_TXLEV (1 << 0)
133#define UART_DM_RXHUNT (1 << 1)
134#define UART_DM_RXBRK_CHNG (1 << 2)
135#define UART_DM_RXSTALE (1 << 3)
136#define UART_DM_RXLEV (1 << 4)
137#define UART_DM_DELTA_CTS (1 << 5)
138#define UART_DM_CURRENT_CTS (1 << 6)
139#define UART_DM_TX_READY (1 << 7)
140#define UART_DM_TX_ERROR (1 << 8)
141#define UART_DM_TX_DONE (1 << 9)
142#define UART_DM_RXBREAK_START (1 << 10)
143#define UART_DM_RXBREAK_END (1 << 11)
144#define UART_DM_PAR_FRAME_ERR_IRQ (1 << 12)
145
146#define UART_DM_IMR_ENABLED (UART_DM_TX_READY | \
147 UART_DM_TXLEV | \
148 UART_DM_RXLEV | \
149 UART_DM_RXSTALE)
150
151/* UART Interrupt Programming Register */
152#define UART_DM_IPR 0x18
153#define UART_DM_STALE_TIMEOUT_LSB 0x0f
154#define UART_DM_STALE_TIMEOUT_MSB 0x00
155#define UART_DM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80
156#define UART_DM_IPR_STALE_LSB_BMSK 0x1f
157
158/* UART Transmit/Receive FIFO Watermark Register */
159#define UART_DM_TFWR 0x1c
160/* Interrupt is generated when FIFO level is less than or equal to this value */
161#define UART_DM_TFW_VALUE 0
162
163#define UART_DM_RFWR 0x20
164/* Interrupt generated when no of words in RX FIFO is greater than this value */
165#define UART_DM_RFW_VALUE 0
166
167/* UART Hunt Character Register */
168#define UART_DM_HCR 0x24
169
170/* Used for RX transfer initialization */
171#define UART_DM_DMRX 0x34
172/* Default DMRX value - any value bigger than FIFO size would be fine */
173#define UART_DM_DMRX_DEF_VALUE 0x220
174
175/* Register to enable IRDA function */
176#define UART_DM_IRDA 0x38
177
178/* UART Data Mover Enable Register */
179#define UART_DM_DMEN 0x3c
180
181/* Number of characters for Transmission */
182#define UART_DM_NO_CHARS_FOR_TX 0x40
183
184/* UART RX FIFO Base Address */
185#define UART_DM_BADR 0x44
186
187#define UART_DM_SIM_CFG_ADDR 0x80
188
189/* Read only registers */
190/* UART Status Register */
191#define UART_DM_SR 0x08
192/* register field mask mapping */
193#define UART_DM_SR_RXRDY (1 << 0)
194#define UART_DM_SR_RXFULL (1 << 1)
195#define UART_DM_SR_TXRDY (1 << 2)
196#define UART_DM_SR_TXEMT (1 << 3)
197#define UART_DM_SR_UART_OVERRUN (1 << 4)
198#define UART_DM_SR_PAR_FRAME_ERR (1 << 5)
199#define UART_DM_RX_BREAK (1 << 6)
200#define UART_DM_HUNT_CHAR (1 << 7)
201#define UART_DM_RX_BRK_START_LAST (1 << 8)
202
203/* UART Receive FIFO Registers - 4 in numbers */
204#define UART_DM_RF(x) (0x70 + (4 * (x)))
205
206/* UART Masked Interrupt Status Register */
207#define UART_DM_MISR 0x10
208
209/* UART Interrupt Status Register */
210#define UART_DM_ISR 0x14
211
212/* Number of characters received since the end of last RX transfer */
213#define UART_DM_RX_TOTAL_SNAP 0x38
214
215/* UART TX FIFO Status Register */
216#define UART_DM_TXFS 0x4c
217#define UART_DM_TXFS_STATE_LSB(x) UART_DM_EXTR_BITS(x,0,6)
218#define UART_DM_TXFS_STATE_MSB(x) UART_DM_EXTR_BITS(x,14,31)
219#define UART_DM_TXFS_BUF_STATE(x) UART_DM_EXTR_BITS(x,7,9)
220#define UART_DM_TXFS_ASYNC_STATE(x) UART_DM_EXTR_BITS(x,10,13)
221
222/* UART RX FIFO Status Register */
223#define UART_DM_RXFS 0x50
224#define UART_DM_RXFS_STATE_LSB(x) UART_DM_EXTR_BITS(x,0,6)
225#define UART_DM_RXFS_STATE_MSB(x) UART_DM_EXTR_BITS(x,14,31)
226#define UART_DM_RXFS_BUF_STATE(x) UART_DM_EXTR_BITS(x,7,9)
227#define UART_DM_RXFS_ASYNC_STATE(x) UART_DM_EXTR_BITS(x,10,13)
228
229#endif /* _UART_DM_H_ */
| 27 */
28
29#ifndef _UART_DM_H_
30#define _UART_DM_H_
31
32#define UART_DM_EXTR_BITS(value, start_pos, end_pos) \
33 ((value << (32 - end_pos)) >> (32 - (end_pos - start_pos)))
34
35/* UART Parity Mode */
36enum UART_DM_PARITY_MODE {
37 UART_DM_NO_PARITY,
38 UART_DM_ODD_PARITY,
39 UART_DM_EVEN_PARITY,
40 UART_DM_SPACE_PARITY
41};
42
43/* UART Stop Bit Length */
44enum UART_DM_STOP_BIT_LEN {
45 UART_DM_SBL_9_16,
46 UART_DM_SBL_1,
47 UART_DM_SBL_1_9_16,
48 UART_DM_SBL_2
49};
50
51/* UART Bits per Char */
52enum UART_DM_BITS_PER_CHAR {
53 UART_DM_5_BPS,
54 UART_DM_6_BPS,
55 UART_DM_7_BPS,
56 UART_DM_8_BPS
57};
58
59/* 8-N-1 Configuration */
60#define UART_DM_8_N_1_MODE (UART_DM_NO_PARITY | \
61 (UART_DM_SBL_1 << 2) | \
62 (UART_DM_8_BPS << 4))
63
64/* UART_DM Registers */
65
66/* UART Operational Mode Registers (HSUART) */
67#define UART_DM_MR1 0x00
68#define UART_DM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00
69#define UART_DM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f
70#define UART_DM_MR1_CTS_CTL_BMSK 0x40
71#define UART_DM_MR1_RX_RDY_CTL_BMSK 0x80
72
73#define UART_DM_MR2 0x04
74#define UART_DM_MR2_ERROR_MODE_BMSK 0x40
75#define UART_DM_MR2_BITS_PER_CHAR_BMSK 0x30
76#define UART_DM_MR2_STOP_BIT_LEN_BMSK 0x0c
77#define UART_DM_MR2_PARITY_MODE_BMSK 0x03
78#define UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8)
79#define UART_DM_LOOPBACK (1 << 7)
80
81/* UART Clock Selection Register, write only */
82#define UART_DM_CSR 0x08
83#define UART_DM_CSR_115200 0xff
84#define UART_DM_CSR_57600 0xee
85#define UART_DM_CSR_38400 0xdd
86#define UART_DM_CSR_28800 0xcc
87#define UART_DM_CSR_19200 0xbb
88#define UART_DM_CSR_14400 0xaa
89#define UART_DM_CSR_9600 0x99
90#define UART_DM_CSR_7200 0x88
91#define UART_DM_CSR_4800 0x77
92#define UART_DM_CSR_3600 0x66
93#define UART_DM_CSR_2400 0x55
94#define UART_DM_CSR_1200 0x44
95#define UART_DM_CSR_600 0x33
96#define UART_DM_CSR_300 0x22
97#define UART_DM_CSR_150 0x11
98#define UART_DM_CSR_75 0x00
99
100/* UART DM TX FIFO Registers - 4, write only */
101#define UART_DM_TF(x) (0x70 + (4 * (x)))
102
103/* UART Command Register, write only */
104#define UART_DM_CR 0x10
105#define UART_DM_CR_RX_ENABLE (1 << 0)
106#define UART_DM_CR_RX_DISABLE (1 << 1)
107#define UART_DM_CR_TX_ENABLE (1 << 2)
108#define UART_DM_CR_TX_DISABLE (1 << 3)
109
110/* UART_DM_CR channel command bit value (register field is bits 8:4) */
111#define UART_DM_RESET_RX 0x10
112#define UART_DM_RESET_TX 0x20
113#define UART_DM_RESET_ERROR_STATUS 0x30
114#define UART_DM_RESET_BREAK_INT 0x40
115#define UART_DM_START_BREAK 0x50
116#define UART_DM_STOP_BREAK 0x60
117#define UART_DM_RESET_CTS 0x70
118#define UART_DM_RESET_STALE_INT 0x80
119#define UART_DM_RFR_LOW 0xD0
120#define UART_DM_RFR_HIGH 0xE0
121#define UART_DM_CR_PROTECTION_EN 0x100
122#define UART_DM_STALE_EVENT_ENABLE 0x500
123#define UART_DM_STALE_EVENT_DISABLE 0x600
124#define UART_DM_FORCE_STALE_EVENT 0x400
125#define UART_DM_CLEAR_TX_READY 0x300
126#define UART_DM_RESET_TX_ERROR 0x800
127#define UART_DM_RESET_TX_DONE 0x810
128
129/* UART Interrupt Mask Register */
130#define UART_DM_IMR 0x14
131/* these can be used for both ISR and IMR registers */
132#define UART_DM_TXLEV (1 << 0)
133#define UART_DM_RXHUNT (1 << 1)
134#define UART_DM_RXBRK_CHNG (1 << 2)
135#define UART_DM_RXSTALE (1 << 3)
136#define UART_DM_RXLEV (1 << 4)
137#define UART_DM_DELTA_CTS (1 << 5)
138#define UART_DM_CURRENT_CTS (1 << 6)
139#define UART_DM_TX_READY (1 << 7)
140#define UART_DM_TX_ERROR (1 << 8)
141#define UART_DM_TX_DONE (1 << 9)
142#define UART_DM_RXBREAK_START (1 << 10)
143#define UART_DM_RXBREAK_END (1 << 11)
144#define UART_DM_PAR_FRAME_ERR_IRQ (1 << 12)
145
146#define UART_DM_IMR_ENABLED (UART_DM_TX_READY | \
147 UART_DM_TXLEV | \
148 UART_DM_RXLEV | \
149 UART_DM_RXSTALE)
150
151/* UART Interrupt Programming Register */
152#define UART_DM_IPR 0x18
153#define UART_DM_STALE_TIMEOUT_LSB 0x0f
154#define UART_DM_STALE_TIMEOUT_MSB 0x00
155#define UART_DM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80
156#define UART_DM_IPR_STALE_LSB_BMSK 0x1f
157
158/* UART Transmit/Receive FIFO Watermark Register */
159#define UART_DM_TFWR 0x1c
160/* Interrupt is generated when FIFO level is less than or equal to this value */
161#define UART_DM_TFW_VALUE 0
162
163#define UART_DM_RFWR 0x20
164/* Interrupt generated when no of words in RX FIFO is greater than this value */
165#define UART_DM_RFW_VALUE 0
166
167/* UART Hunt Character Register */
168#define UART_DM_HCR 0x24
169
170/* Used for RX transfer initialization */
171#define UART_DM_DMRX 0x34
172/* Default DMRX value - any value bigger than FIFO size would be fine */
173#define UART_DM_DMRX_DEF_VALUE 0x220
174
175/* Register to enable IRDA function */
176#define UART_DM_IRDA 0x38
177
178/* UART Data Mover Enable Register */
179#define UART_DM_DMEN 0x3c
180
181/* Number of characters for Transmission */
182#define UART_DM_NO_CHARS_FOR_TX 0x40
183
184/* UART RX FIFO Base Address */
185#define UART_DM_BADR 0x44
186
187#define UART_DM_SIM_CFG_ADDR 0x80
188
189/* Read only registers */
190/* UART Status Register */
191#define UART_DM_SR 0x08
192/* register field mask mapping */
193#define UART_DM_SR_RXRDY (1 << 0)
194#define UART_DM_SR_RXFULL (1 << 1)
195#define UART_DM_SR_TXRDY (1 << 2)
196#define UART_DM_SR_TXEMT (1 << 3)
197#define UART_DM_SR_UART_OVERRUN (1 << 4)
198#define UART_DM_SR_PAR_FRAME_ERR (1 << 5)
199#define UART_DM_RX_BREAK (1 << 6)
200#define UART_DM_HUNT_CHAR (1 << 7)
201#define UART_DM_RX_BRK_START_LAST (1 << 8)
202
203/* UART Receive FIFO Registers - 4 in numbers */
204#define UART_DM_RF(x) (0x70 + (4 * (x)))
205
206/* UART Masked Interrupt Status Register */
207#define UART_DM_MISR 0x10
208
209/* UART Interrupt Status Register */
210#define UART_DM_ISR 0x14
211
212/* Number of characters received since the end of last RX transfer */
213#define UART_DM_RX_TOTAL_SNAP 0x38
214
215/* UART TX FIFO Status Register */
216#define UART_DM_TXFS 0x4c
217#define UART_DM_TXFS_STATE_LSB(x) UART_DM_EXTR_BITS(x,0,6)
218#define UART_DM_TXFS_STATE_MSB(x) UART_DM_EXTR_BITS(x,14,31)
219#define UART_DM_TXFS_BUF_STATE(x) UART_DM_EXTR_BITS(x,7,9)
220#define UART_DM_TXFS_ASYNC_STATE(x) UART_DM_EXTR_BITS(x,10,13)
221
222/* UART RX FIFO Status Register */
223#define UART_DM_RXFS 0x50
224#define UART_DM_RXFS_STATE_LSB(x) UART_DM_EXTR_BITS(x,0,6)
225#define UART_DM_RXFS_STATE_MSB(x) UART_DM_EXTR_BITS(x,14,31)
226#define UART_DM_RXFS_BUF_STATE(x) UART_DM_EXTR_BITS(x,7,9)
227#define UART_DM_RXFS_ASYNC_STATE(x) UART_DM_EXTR_BITS(x,10,13)
228
229#endif /* _UART_DM_H_ */
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