56
57/*
58 * Clear pending interrupts. THRE is cleared by reading IIR. Data
59 * that may have been received gets lost here.
60 */
61static void
62lpc_ns8250_clrint(struct uart_bas *bas)
63{
64 uint8_t iir, lsr;
65
66 iir = uart_getreg(bas, REG_IIR);
67 while ((iir & IIR_NOPEND) == 0) {
68 iir &= IIR_IMASK;
69 if (iir == IIR_RLS) {
70 lsr = uart_getreg(bas, REG_LSR);
71 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
72 (void)uart_getreg(bas, REG_DATA);
73 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
74 (void)uart_getreg(bas, REG_DATA);
75 else if (iir == IIR_MLSC)
76 (void)uart_getreg(bas, REG_MSR);
77 uart_barrier(bas);
78 iir = uart_getreg(bas, REG_IIR);
79 }
80}
81
82static int
83lpc_ns8250_delay(struct uart_bas *bas)
84{
85 uint32_t uclk;
86 int x, y;
87
88 uclk = lpc_ns8250_get_clkreg(bas, LPC_CLKPWR_UART_U5CLK);
89
90 x = (uclk >> 8) & 0xff;
91 y = uclk & 0xff;
92
93 return (16000000 / (bas->rclk * x / y));
94}
95
96static void
97lpc_ns8250_divisor(int rclk, int baudrate, int *x, int *y)
98{
99
100 switch (baudrate) {
101 case 2400:
102 *x = 1;
103 *y = 255;
104 return;
105 case 4800:
106 *x = 1;
107 *y = 169;
108 return;
109 case 9600:
110 *x = 3;
111 *y = 254;
112 return;
113 case 19200:
114 *x = 3;
115 *y = 127;
116 return;
117 case 38400:
118 *x = 6;
119 *y = 127;
120 return;
121 case 57600:
122 *x = 9;
123 *y = 127;
124 return;
125 default:
126 case 115200:
127 *x = 19;
128 *y = 134;
129 return;
130 case 230400:
131 *x = 19;
132 *y = 67;
133 return;
134 case 460800:
135 *x = 38;
136 *y = 67;
137 return;
138 }
139}
140
141static int
142lpc_ns8250_drain(struct uart_bas *bas, int what)
143{
144 int delay, limit;
145
146 delay = lpc_ns8250_delay(bas);
147
148 if (what & UART_DRAIN_TRANSMITTER) {
149 /*
150 * Pick an arbitrary high limit to avoid getting stuck in
151 * an infinite loop when the hardware is broken. Make the
152 * limit high enough to handle large FIFOs.
153 */
154 limit = 10*1024;
155 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
156 DELAY(delay);
157 if (limit == 0) {
158 /* printf("lpc_ns8250: transmitter appears stuck... "); */
159 return (EIO);
160 }
161 }
162
163 if (what & UART_DRAIN_RECEIVER) {
164 /*
165 * Pick an arbitrary high limit to avoid getting stuck in
166 * an infinite loop when the hardware is broken. Make the
167 * limit high enough to handle large FIFOs and integrated
168 * UARTs. The HP rx2600 for example has 3 UARTs on the
169 * management board that tend to get a lot of data send
170 * to it when the UART is first activated.
171 */
172 limit=10*4096;
173 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
174 (void)uart_getreg(bas, REG_DATA);
175 uart_barrier(bas);
176 DELAY(delay << 2);
177 }
178 if (limit == 0) {
179 /* printf("lpc_ns8250: receiver appears broken... "); */
180 return (EIO);
181 }
182 }
183
184 return (0);
185}
186
187/*
188 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
189 * drained. WARNING: this function clobbers the FIFO setting!
190 */
191static void
192lpc_ns8250_flush(struct uart_bas *bas, int what)
193{
194 uint8_t fcr;
195
196 fcr = FCR_ENABLE;
197 if (what & UART_FLUSH_TRANSMITTER)
198 fcr |= FCR_XMT_RST;
199 if (what & UART_FLUSH_RECEIVER)
200 fcr |= FCR_RCV_RST;
201 uart_setreg(bas, REG_FCR, fcr);
202 uart_barrier(bas);
203}
204
205static int
206lpc_ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
207 int parity)
208{
209 int xdiv, ydiv;
210 uint8_t lcr;
211
212 lcr = 0;
213 if (databits >= 8)
214 lcr |= LCR_8BITS;
215 else if (databits == 7)
216 lcr |= LCR_7BITS;
217 else if (databits == 6)
218 lcr |= LCR_6BITS;
219 else
220 lcr |= LCR_5BITS;
221 if (stopbits > 1)
222 lcr |= LCR_STOPB;
223 lcr |= parity << 3;
224
225 /* Set baudrate. */
226 if (baudrate > 0) {
227 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
228 uart_barrier(bas);
229 uart_setreg(bas, REG_DLL, 0x00);
230 uart_setreg(bas, REG_DLH, 0x00);
231 uart_barrier(bas);
232
233 lpc_ns8250_divisor(bas->rclk, baudrate, &xdiv, &ydiv);
234 lpc_ns8250_set_clkreg(bas,
235 LPC_CLKPWR_UART_U5CLK,
236 LPC_CLKPWR_UART_UCLK_X(xdiv) |
237 LPC_CLKPWR_UART_UCLK_Y(ydiv));
238 }
239
240 /* Set LCR and clear DLAB. */
241 uart_setreg(bas, REG_LCR, lcr);
242 uart_barrier(bas);
243 return (0);
244}
245
246/*
247 * Low-level UART interface.
248 */
249static int lpc_ns8250_probe(struct uart_bas *bas);
250static void lpc_ns8250_init(struct uart_bas *bas, int, int, int, int);
251static void lpc_ns8250_term(struct uart_bas *bas);
252static void lpc_ns8250_putc(struct uart_bas *bas, int);
253static int lpc_ns8250_rxready(struct uart_bas *bas);
254static int lpc_ns8250_getc(struct uart_bas *bas, struct mtx *);
255
256static struct uart_ops uart_lpc_ns8250_ops = {
257 .probe = lpc_ns8250_probe,
258 .init = lpc_ns8250_init,
259 .term = lpc_ns8250_term,
260 .putc = lpc_ns8250_putc,
261 .rxready = lpc_ns8250_rxready,
262 .getc = lpc_ns8250_getc,
263};
264
265static int
266lpc_ns8250_probe(struct uart_bas *bas)
267{
268#if 0
269 u_char val;
270
271 /* Check known 0 bits that don't depend on DLAB. */
272 val = uart_getreg(bas, REG_IIR);
273 if (val & 0x30)
274 return (ENXIO);
275 /*
276 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
277 * chip, but otherwise doesn't seem to have a function. In
278 * other words, uart(4) works regardless. Ignore that bit so
279 * the probe succeeds.
280 */
281 val = uart_getreg(bas, REG_MCR);
282 if (val & 0xa0)
283 return (ENXIO);
284#endif
285 return (0);
286}
287
288static void
289lpc_ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
290 int parity)
291{
292 u_char ier;
293 u_long clkmode;
294
295 /* Enable UART clock */
| 54
55/*
56 * Clear pending interrupts. THRE is cleared by reading IIR. Data
57 * that may have been received gets lost here.
58 */
59static void
60lpc_ns8250_clrint(struct uart_bas *bas)
61{
62 uint8_t iir, lsr;
63
64 iir = uart_getreg(bas, REG_IIR);
65 while ((iir & IIR_NOPEND) == 0) {
66 iir &= IIR_IMASK;
67 if (iir == IIR_RLS) {
68 lsr = uart_getreg(bas, REG_LSR);
69 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
70 (void)uart_getreg(bas, REG_DATA);
71 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
72 (void)uart_getreg(bas, REG_DATA);
73 else if (iir == IIR_MLSC)
74 (void)uart_getreg(bas, REG_MSR);
75 uart_barrier(bas);
76 iir = uart_getreg(bas, REG_IIR);
77 }
78}
79
80static int
81lpc_ns8250_delay(struct uart_bas *bas)
82{
83 uint32_t uclk;
84 int x, y;
85
86 uclk = lpc_ns8250_get_clkreg(bas, LPC_CLKPWR_UART_U5CLK);
87
88 x = (uclk >> 8) & 0xff;
89 y = uclk & 0xff;
90
91 return (16000000 / (bas->rclk * x / y));
92}
93
94static void
95lpc_ns8250_divisor(int rclk, int baudrate, int *x, int *y)
96{
97
98 switch (baudrate) {
99 case 2400:
100 *x = 1;
101 *y = 255;
102 return;
103 case 4800:
104 *x = 1;
105 *y = 169;
106 return;
107 case 9600:
108 *x = 3;
109 *y = 254;
110 return;
111 case 19200:
112 *x = 3;
113 *y = 127;
114 return;
115 case 38400:
116 *x = 6;
117 *y = 127;
118 return;
119 case 57600:
120 *x = 9;
121 *y = 127;
122 return;
123 default:
124 case 115200:
125 *x = 19;
126 *y = 134;
127 return;
128 case 230400:
129 *x = 19;
130 *y = 67;
131 return;
132 case 460800:
133 *x = 38;
134 *y = 67;
135 return;
136 }
137}
138
139static int
140lpc_ns8250_drain(struct uart_bas *bas, int what)
141{
142 int delay, limit;
143
144 delay = lpc_ns8250_delay(bas);
145
146 if (what & UART_DRAIN_TRANSMITTER) {
147 /*
148 * Pick an arbitrary high limit to avoid getting stuck in
149 * an infinite loop when the hardware is broken. Make the
150 * limit high enough to handle large FIFOs.
151 */
152 limit = 10*1024;
153 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
154 DELAY(delay);
155 if (limit == 0) {
156 /* printf("lpc_ns8250: transmitter appears stuck... "); */
157 return (EIO);
158 }
159 }
160
161 if (what & UART_DRAIN_RECEIVER) {
162 /*
163 * Pick an arbitrary high limit to avoid getting stuck in
164 * an infinite loop when the hardware is broken. Make the
165 * limit high enough to handle large FIFOs and integrated
166 * UARTs. The HP rx2600 for example has 3 UARTs on the
167 * management board that tend to get a lot of data send
168 * to it when the UART is first activated.
169 */
170 limit=10*4096;
171 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
172 (void)uart_getreg(bas, REG_DATA);
173 uart_barrier(bas);
174 DELAY(delay << 2);
175 }
176 if (limit == 0) {
177 /* printf("lpc_ns8250: receiver appears broken... "); */
178 return (EIO);
179 }
180 }
181
182 return (0);
183}
184
185/*
186 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
187 * drained. WARNING: this function clobbers the FIFO setting!
188 */
189static void
190lpc_ns8250_flush(struct uart_bas *bas, int what)
191{
192 uint8_t fcr;
193
194 fcr = FCR_ENABLE;
195 if (what & UART_FLUSH_TRANSMITTER)
196 fcr |= FCR_XMT_RST;
197 if (what & UART_FLUSH_RECEIVER)
198 fcr |= FCR_RCV_RST;
199 uart_setreg(bas, REG_FCR, fcr);
200 uart_barrier(bas);
201}
202
203static int
204lpc_ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
205 int parity)
206{
207 int xdiv, ydiv;
208 uint8_t lcr;
209
210 lcr = 0;
211 if (databits >= 8)
212 lcr |= LCR_8BITS;
213 else if (databits == 7)
214 lcr |= LCR_7BITS;
215 else if (databits == 6)
216 lcr |= LCR_6BITS;
217 else
218 lcr |= LCR_5BITS;
219 if (stopbits > 1)
220 lcr |= LCR_STOPB;
221 lcr |= parity << 3;
222
223 /* Set baudrate. */
224 if (baudrate > 0) {
225 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
226 uart_barrier(bas);
227 uart_setreg(bas, REG_DLL, 0x00);
228 uart_setreg(bas, REG_DLH, 0x00);
229 uart_barrier(bas);
230
231 lpc_ns8250_divisor(bas->rclk, baudrate, &xdiv, &ydiv);
232 lpc_ns8250_set_clkreg(bas,
233 LPC_CLKPWR_UART_U5CLK,
234 LPC_CLKPWR_UART_UCLK_X(xdiv) |
235 LPC_CLKPWR_UART_UCLK_Y(ydiv));
236 }
237
238 /* Set LCR and clear DLAB. */
239 uart_setreg(bas, REG_LCR, lcr);
240 uart_barrier(bas);
241 return (0);
242}
243
244/*
245 * Low-level UART interface.
246 */
247static int lpc_ns8250_probe(struct uart_bas *bas);
248static void lpc_ns8250_init(struct uart_bas *bas, int, int, int, int);
249static void lpc_ns8250_term(struct uart_bas *bas);
250static void lpc_ns8250_putc(struct uart_bas *bas, int);
251static int lpc_ns8250_rxready(struct uart_bas *bas);
252static int lpc_ns8250_getc(struct uart_bas *bas, struct mtx *);
253
254static struct uart_ops uart_lpc_ns8250_ops = {
255 .probe = lpc_ns8250_probe,
256 .init = lpc_ns8250_init,
257 .term = lpc_ns8250_term,
258 .putc = lpc_ns8250_putc,
259 .rxready = lpc_ns8250_rxready,
260 .getc = lpc_ns8250_getc,
261};
262
263static int
264lpc_ns8250_probe(struct uart_bas *bas)
265{
266#if 0
267 u_char val;
268
269 /* Check known 0 bits that don't depend on DLAB. */
270 val = uart_getreg(bas, REG_IIR);
271 if (val & 0x30)
272 return (ENXIO);
273 /*
274 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
275 * chip, but otherwise doesn't seem to have a function. In
276 * other words, uart(4) works regardless. Ignore that bit so
277 * the probe succeeds.
278 */
279 val = uart_getreg(bas, REG_MCR);
280 if (val & 0xa0)
281 return (ENXIO);
282#endif
283 return (0);
284}
285
286static void
287lpc_ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
288 int parity)
289{
290 u_char ier;
291 u_long clkmode;
292
293 /* Enable UART clock */
|
299#if 0
300 /* Work around H/W bug */
301 uart_setreg(bas, REG_DATA, 0x00);
302#endif
303 if (bas->rclk == 0)
304 bas->rclk = DEFAULT_RCLK;
305 lpc_ns8250_param(bas, baudrate, databits, stopbits, parity);
306
307 /* Disable all interrupt sources. */
308 /*
309 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
310 * UARTs split the receive time-out interrupt bit out separately as
311 * 0x10. This gets handled by ier_mask and ier_rxbits below.
312 */
313 ier = uart_getreg(bas, REG_IER) & 0xe0;
314 uart_setreg(bas, REG_IER, ier);
315 uart_barrier(bas);
316
317 /* Disable the FIFO (if present). */
318 uart_setreg(bas, REG_FCR, 0);
319 uart_barrier(bas);
320
321 /* Set RTS & DTR. */
322 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
323 uart_barrier(bas);
324
325 lpc_ns8250_clrint(bas);
326}
327
328static void
329lpc_ns8250_term(struct uart_bas *bas)
330{
331
332 /* Clear RTS & DTR. */
333 uart_setreg(bas, REG_MCR, MCR_IE);
334 uart_barrier(bas);
335}
336
337static void
338lpc_ns8250_putc(struct uart_bas *bas, int c)
339{
340 int limit;
341
342 limit = 250000;
343 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
344 DELAY(4);
345 uart_setreg(bas, REG_DATA, c);
346 uart_barrier(bas);
347 limit = 250000;
348 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
349 DELAY(4);
350}
351
352static int
353lpc_ns8250_rxready(struct uart_bas *bas)
354{
355
356 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
357}
358
359static int
360lpc_ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
361{
362 int c;
363
364 uart_lock(hwmtx);
365
366 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
367 uart_unlock(hwmtx);
368 DELAY(4);
369 uart_lock(hwmtx);
370 }
371
372 c = uart_getreg(bas, REG_DATA);
373
374 uart_unlock(hwmtx);
375
376 return (c);
377}
378
379/*
380 * High-level UART interface.
381 */
382struct lpc_ns8250_softc {
383 struct uart_softc base;
384 uint8_t fcr;
385 uint8_t ier;
386 uint8_t mcr;
387
388 uint8_t ier_mask;
389 uint8_t ier_rxbits;
390};
391
392static int lpc_ns8250_bus_attach(struct uart_softc *);
393static int lpc_ns8250_bus_detach(struct uart_softc *);
394static int lpc_ns8250_bus_flush(struct uart_softc *, int);
395static int lpc_ns8250_bus_getsig(struct uart_softc *);
396static int lpc_ns8250_bus_ioctl(struct uart_softc *, int, intptr_t);
397static int lpc_ns8250_bus_ipend(struct uart_softc *);
398static int lpc_ns8250_bus_param(struct uart_softc *, int, int, int, int);
399static int lpc_ns8250_bus_probe(struct uart_softc *);
400static int lpc_ns8250_bus_receive(struct uart_softc *);
401static int lpc_ns8250_bus_setsig(struct uart_softc *, int);
402static int lpc_ns8250_bus_transmit(struct uart_softc *);
403static void lpc_ns8250_bus_grab(struct uart_softc *);
404static void lpc_ns8250_bus_ungrab(struct uart_softc *);
405
406static kobj_method_t lpc_ns8250_methods[] = {
407 KOBJMETHOD(uart_attach, lpc_ns8250_bus_attach),
408 KOBJMETHOD(uart_detach, lpc_ns8250_bus_detach),
409 KOBJMETHOD(uart_flush, lpc_ns8250_bus_flush),
410 KOBJMETHOD(uart_getsig, lpc_ns8250_bus_getsig),
411 KOBJMETHOD(uart_ioctl, lpc_ns8250_bus_ioctl),
412 KOBJMETHOD(uart_ipend, lpc_ns8250_bus_ipend),
413 KOBJMETHOD(uart_param, lpc_ns8250_bus_param),
414 KOBJMETHOD(uart_probe, lpc_ns8250_bus_probe),
415 KOBJMETHOD(uart_receive, lpc_ns8250_bus_receive),
416 KOBJMETHOD(uart_setsig, lpc_ns8250_bus_setsig),
417 KOBJMETHOD(uart_transmit, lpc_ns8250_bus_transmit),
418 KOBJMETHOD(uart_grab, lpc_ns8250_bus_grab),
419 KOBJMETHOD(uart_ungrab, lpc_ns8250_bus_ungrab),
420 { 0, 0 }
421};
422
423struct uart_class uart_lpc_class = {
424 "lpc_ns8250",
425 lpc_ns8250_methods,
426 sizeof(struct lpc_ns8250_softc),
427 .uc_ops = &uart_lpc_ns8250_ops,
428 .uc_range = 8,
429 .uc_rclk = DEFAULT_RCLK
430};
431
432#define SIGCHG(c, i, s, d) \
433 if (c) { \
434 i |= (i & s) ? s : s | d; \
435 } else { \
436 i = (i & s) ? (i & ~s) | d : i; \
437 }
438
439static int
440lpc_ns8250_bus_attach(struct uart_softc *sc)
441{
442 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
443 struct uart_bas *bas;
444 unsigned int ivar;
445
446 bas = &sc->sc_bas;
447
448 lpc_ns8250->mcr = uart_getreg(bas, REG_MCR);
449 lpc_ns8250->fcr = FCR_ENABLE | FCR_DMA;
450 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
451 &ivar)) {
452 if (UART_FLAGS_FCR_RX_LOW(ivar))
453 lpc_ns8250->fcr |= FCR_RX_LOW;
454 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
455 lpc_ns8250->fcr |= FCR_RX_MEDL;
456 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
457 lpc_ns8250->fcr |= FCR_RX_HIGH;
458 else
459 lpc_ns8250->fcr |= FCR_RX_MEDH;
460 } else
461 lpc_ns8250->fcr |= FCR_RX_HIGH;
462
463 /* Get IER mask */
464 ivar = 0xf0;
465 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
466 &ivar);
467 lpc_ns8250->ier_mask = (uint8_t)(ivar & 0xff);
468
469 /* Get IER RX interrupt bits */
470 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
471 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
472 &ivar);
473 lpc_ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
474
475 uart_setreg(bas, REG_FCR, lpc_ns8250->fcr);
476 uart_barrier(bas);
477 lpc_ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
478
479 if (lpc_ns8250->mcr & MCR_DTR)
480 sc->sc_hwsig |= SER_DTR;
481 if (lpc_ns8250->mcr & MCR_RTS)
482 sc->sc_hwsig |= SER_RTS;
483 lpc_ns8250_bus_getsig(sc);
484
485 lpc_ns8250_clrint(bas);
486 lpc_ns8250->ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask;
487 lpc_ns8250->ier |= lpc_ns8250->ier_rxbits;
488 uart_setreg(bas, REG_IER, lpc_ns8250->ier);
489 uart_barrier(bas);
490
491 return (0);
492}
493
494static int
495lpc_ns8250_bus_detach(struct uart_softc *sc)
496{
497 struct lpc_ns8250_softc *lpc_ns8250;
498 struct uart_bas *bas;
499 u_char ier;
500
501 lpc_ns8250 = (struct lpc_ns8250_softc *)sc;
502 bas = &sc->sc_bas;
503 ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask;
504 uart_setreg(bas, REG_IER, ier);
505 uart_barrier(bas);
506 lpc_ns8250_clrint(bas);
507 return (0);
508}
509
510static int
511lpc_ns8250_bus_flush(struct uart_softc *sc, int what)
512{
513 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
514 struct uart_bas *bas;
515 int error;
516
517 bas = &sc->sc_bas;
518 uart_lock(sc->sc_hwmtx);
519 if (sc->sc_rxfifosz > 1) {
520 lpc_ns8250_flush(bas, what);
521 uart_setreg(bas, REG_FCR, lpc_ns8250->fcr);
522 uart_barrier(bas);
523 error = 0;
524 } else
525 error = lpc_ns8250_drain(bas, what);
526 uart_unlock(sc->sc_hwmtx);
527 return (error);
528}
529
530static int
531lpc_ns8250_bus_getsig(struct uart_softc *sc)
532{
533 uint32_t new, old, sig;
534 uint8_t msr;
535
536 do {
537 old = sc->sc_hwsig;
538 sig = old;
539 uart_lock(sc->sc_hwmtx);
540 msr = uart_getreg(&sc->sc_bas, REG_MSR);
541 uart_unlock(sc->sc_hwmtx);
542 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
543 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
544 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
545 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
546 new = sig & ~SER_MASK_DELTA;
547 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
548 return (sig);
549}
550
551static int
552lpc_ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
553{
554 struct uart_bas *bas;
555 int baudrate, divisor, error;
556 uint8_t efr, lcr;
557
558 bas = &sc->sc_bas;
559 error = 0;
560 uart_lock(sc->sc_hwmtx);
561 switch (request) {
562 case UART_IOCTL_BREAK:
563 lcr = uart_getreg(bas, REG_LCR);
564 if (data)
565 lcr |= LCR_SBREAK;
566 else
567 lcr &= ~LCR_SBREAK;
568 uart_setreg(bas, REG_LCR, lcr);
569 uart_barrier(bas);
570 break;
571 case UART_IOCTL_IFLOW:
572 lcr = uart_getreg(bas, REG_LCR);
573 uart_barrier(bas);
574 uart_setreg(bas, REG_LCR, 0xbf);
575 uart_barrier(bas);
576 efr = uart_getreg(bas, REG_EFR);
577 if (data)
578 efr |= EFR_RTS;
579 else
580 efr &= ~EFR_RTS;
581 uart_setreg(bas, REG_EFR, efr);
582 uart_barrier(bas);
583 uart_setreg(bas, REG_LCR, lcr);
584 uart_barrier(bas);
585 break;
586 case UART_IOCTL_OFLOW:
587 lcr = uart_getreg(bas, REG_LCR);
588 uart_barrier(bas);
589 uart_setreg(bas, REG_LCR, 0xbf);
590 uart_barrier(bas);
591 efr = uart_getreg(bas, REG_EFR);
592 if (data)
593 efr |= EFR_CTS;
594 else
595 efr &= ~EFR_CTS;
596 uart_setreg(bas, REG_EFR, efr);
597 uart_barrier(bas);
598 uart_setreg(bas, REG_LCR, lcr);
599 uart_barrier(bas);
600 break;
601 case UART_IOCTL_BAUD:
602 lcr = uart_getreg(bas, REG_LCR);
603 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
604 uart_barrier(bas);
605 divisor = uart_getreg(bas, REG_DLL) |
606 (uart_getreg(bas, REG_DLH) << 8);
607 uart_barrier(bas);
608 uart_setreg(bas, REG_LCR, lcr);
609 uart_barrier(bas);
610 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
611 if (baudrate > 0)
612 *(int*)data = baudrate;
613 else
614 error = ENXIO;
615 break;
616 default:
617 error = EINVAL;
618 break;
619 }
620 uart_unlock(sc->sc_hwmtx);
621 return (error);
622}
623
624static int
625lpc_ns8250_bus_ipend(struct uart_softc *sc)
626{
627 struct uart_bas *bas;
628 struct lpc_ns8250_softc *lpc_ns8250;
629 int ipend;
630 uint8_t iir, lsr;
631
632 lpc_ns8250 = (struct lpc_ns8250_softc *)sc;
633 bas = &sc->sc_bas;
634 uart_lock(sc->sc_hwmtx);
635 iir = uart_getreg(bas, REG_IIR);
636 if (iir & IIR_NOPEND) {
637 uart_unlock(sc->sc_hwmtx);
638 return (0);
639 }
640 ipend = 0;
641 if (iir & IIR_RXRDY) {
642 lsr = uart_getreg(bas, REG_LSR);
643 if (lsr & LSR_OE)
644 ipend |= SER_INT_OVERRUN;
645 if (lsr & LSR_BI)
646 ipend |= SER_INT_BREAK;
647 if (lsr & LSR_RXRDY)
648 ipend |= SER_INT_RXREADY;
649 } else {
650 if (iir & IIR_TXRDY) {
651 ipend |= SER_INT_TXIDLE;
652 uart_setreg(bas, REG_IER, lpc_ns8250->ier);
653 } else
654 ipend |= SER_INT_SIGCHG;
655 }
656 if (ipend == 0)
657 lpc_ns8250_clrint(bas);
658 uart_unlock(sc->sc_hwmtx);
659 return (ipend);
660}
661
662static int
663lpc_ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
664 int stopbits, int parity)
665{
666 struct uart_bas *bas;
667 int error;
668
669 bas = &sc->sc_bas;
670 uart_lock(sc->sc_hwmtx);
671 error = lpc_ns8250_param(bas, baudrate, databits, stopbits, parity);
672 uart_unlock(sc->sc_hwmtx);
673 return (error);
674}
675
676static int
677lpc_ns8250_bus_probe(struct uart_softc *sc)
678{
679 struct lpc_ns8250_softc *lpc_ns8250;
680 struct uart_bas *bas;
681 int count, delay, error, limit;
682 uint8_t lsr, mcr, ier;
683
684 lpc_ns8250 = (struct lpc_ns8250_softc *)sc;
685 bas = &sc->sc_bas;
686
687 error = lpc_ns8250_probe(bas);
688 if (error)
689 return (error);
690
691 mcr = MCR_IE;
692 if (sc->sc_sysdev == NULL) {
693 /* By using lpc_ns8250_init() we also set DTR and RTS. */
694 lpc_ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
695 } else
696 mcr |= MCR_DTR | MCR_RTS;
697
698 error = lpc_ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
699 if (error)
700 return (error);
701
702 /*
703 * Set loopback mode. This avoids having garbage on the wire and
704 * also allows us send and receive data. We set DTR and RTS to
705 * avoid the possibility that automatic flow-control prevents
706 * any data from being sent.
707 */
708 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
709 uart_barrier(bas);
710
711 /*
712 * Enable FIFOs. And check that the UART has them. If not, we're
713 * done. Since this is the first time we enable the FIFOs, we reset
714 * them.
715 */
716 uart_setreg(bas, REG_FCR, FCR_ENABLE);
717 uart_barrier(bas);
718 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
719 /*
720 * NS16450 or INS8250. We don't bother to differentiate
721 * between them. They're too old to be interesting.
722 */
723 uart_setreg(bas, REG_MCR, mcr);
724 uart_barrier(bas);
725 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
726 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
727 return (0);
728 }
729
730 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
731 uart_barrier(bas);
732
733 count = 0;
734 delay = lpc_ns8250_delay(bas);
735
736 /* We have FIFOs. Drain the transmitter and receiver. */
737 error = lpc_ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
738 if (error) {
739 uart_setreg(bas, REG_MCR, mcr);
740 uart_setreg(bas, REG_FCR, 0);
741 uart_barrier(bas);
742 goto done;
743 }
744
745 /*
746 * We should have a sufficiently clean "pipe" to determine the
747 * size of the FIFOs. We send as much characters as is reasonable
748 * and wait for the overflow bit in the LSR register to be
749 * asserted, counting the characters as we send them. Based on
750 * that count we know the FIFO size.
751 */
752 do {
753 uart_setreg(bas, REG_DATA, 0);
754 uart_barrier(bas);
755 count++;
756
757 limit = 30;
758 lsr = 0;
759 /*
760 * LSR bits are cleared upon read, so we must accumulate
761 * them to be able to test LSR_OE below.
762 */
763 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
764 --limit)
765 DELAY(delay);
766 if (limit == 0) {
767 ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask;
768 uart_setreg(bas, REG_IER, ier);
769 uart_setreg(bas, REG_MCR, mcr);
770 uart_setreg(bas, REG_FCR, 0);
771 uart_barrier(bas);
772 count = 0;
773 goto done;
774 }
775 } while ((lsr & LSR_OE) == 0 && count < 130);
776 count--;
777
778 uart_setreg(bas, REG_MCR, mcr);
779
780 /* Reset FIFOs. */
781 lpc_ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
782
783done:
784 sc->sc_rxfifosz = 64;
785 device_set_desc(sc->sc_dev, "LPC32x0 UART with FIFOs");
786
787 /*
788 * Force the Tx FIFO size to 16 bytes for now. We don't program the
789 * Tx trigger. Also, we assume that all data has been sent when the
790 * interrupt happens.
791 */
792 sc->sc_txfifosz = 16;
793
794#if 0
795 /*
796 * XXX there are some issues related to hardware flow control and
797 * it's likely that uart(4) is the cause. This basicly needs more
798 * investigation, but we avoid using for hardware flow control
799 * until then.
800 */
801 /* 16650s or higher have automatic flow control. */
802 if (sc->sc_rxfifosz > 16) {
803 sc->sc_hwiflow = 1;
804 sc->sc_hwoflow = 1;
805 }
806#endif
807 return (0);
808}
809
810static int
811lpc_ns8250_bus_receive(struct uart_softc *sc)
812{
813 struct uart_bas *bas;
814 int xc;
815 uint8_t lsr;
816
817 bas = &sc->sc_bas;
818 uart_lock(sc->sc_hwmtx);
819 lsr = uart_getreg(bas, REG_LSR);
820 while (lsr & LSR_RXRDY) {
821 if (uart_rx_full(sc)) {
822 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
823 break;
824 }
825 xc = uart_getreg(bas, REG_DATA);
826 if (lsr & LSR_FE)
827 xc |= UART_STAT_FRAMERR;
828 if (lsr & LSR_PE)
829 xc |= UART_STAT_PARERR;
830 uart_rx_put(sc, xc);
831 lsr = uart_getreg(bas, REG_LSR);
832 }
833 /* Discard everything left in the Rx FIFO. */
834 while (lsr & LSR_RXRDY) {
835 (void)uart_getreg(bas, REG_DATA);
836 uart_barrier(bas);
837 lsr = uart_getreg(bas, REG_LSR);
838 }
839 uart_unlock(sc->sc_hwmtx);
840 return (0);
841}
842
843static int
844lpc_ns8250_bus_setsig(struct uart_softc *sc, int sig)
845{
846 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
847 struct uart_bas *bas;
848 uint32_t new, old;
849
850 bas = &sc->sc_bas;
851 do {
852 old = sc->sc_hwsig;
853 new = old;
854 if (sig & SER_DDTR) {
855 SIGCHG(sig & SER_DTR, new, SER_DTR,
856 SER_DDTR);
857 }
858 if (sig & SER_DRTS) {
859 SIGCHG(sig & SER_RTS, new, SER_RTS,
860 SER_DRTS);
861 }
862 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
863 uart_lock(sc->sc_hwmtx);
864 lpc_ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
865 if (new & SER_DTR)
866 lpc_ns8250->mcr |= MCR_DTR;
867 if (new & SER_RTS)
868 lpc_ns8250->mcr |= MCR_RTS;
869 uart_setreg(bas, REG_MCR, lpc_ns8250->mcr);
870 uart_barrier(bas);
871 uart_unlock(sc->sc_hwmtx);
872 return (0);
873}
874
875static int
876lpc_ns8250_bus_transmit(struct uart_softc *sc)
877{
878 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
879 struct uart_bas *bas;
880 int i;
881
882 bas = &sc->sc_bas;
883 uart_lock(sc->sc_hwmtx);
884 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
885 ;
886 uart_setreg(bas, REG_IER, lpc_ns8250->ier | IER_ETXRDY);
887 uart_barrier(bas);
888 for (i = 0; i < sc->sc_txdatasz; i++) {
889 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
890 uart_barrier(bas);
891 }
892 sc->sc_txbusy = 1;
893 uart_unlock(sc->sc_hwmtx);
894 return (0);
895}
896
897void
898lpc_ns8250_bus_grab(struct uart_softc *sc)
899{
900 struct uart_bas *bas = &sc->sc_bas;
901
902 /*
903 * turn off all interrupts to enter polling mode. Leave the
904 * saved mask alone. We'll restore whatever it was in ungrab.
905 * All pending interupt signals are reset when IER is set to 0.
906 */
907 uart_lock(sc->sc_hwmtx);
908 uart_setreg(bas, REG_IER, 0);
909 uart_barrier(bas);
910 uart_unlock(sc->sc_hwmtx);
911}
912
913void
914lpc_ns8250_bus_ungrab(struct uart_softc *sc)
915{
916 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
917 struct uart_bas *bas = &sc->sc_bas;
918
919 /*
920 * Restore previous interrupt mask
921 */
922 uart_lock(sc->sc_hwmtx);
923 uart_setreg(bas, REG_IER, lpc_ns8250->ier);
924 uart_barrier(bas);
925 uart_unlock(sc->sc_hwmtx);
926}
| 300#if 0
301 /* Work around H/W bug */
302 uart_setreg(bas, REG_DATA, 0x00);
303#endif
304 if (bas->rclk == 0)
305 bas->rclk = DEFAULT_RCLK;
306 lpc_ns8250_param(bas, baudrate, databits, stopbits, parity);
307
308 /* Disable all interrupt sources. */
309 /*
310 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
311 * UARTs split the receive time-out interrupt bit out separately as
312 * 0x10. This gets handled by ier_mask and ier_rxbits below.
313 */
314 ier = uart_getreg(bas, REG_IER) & 0xe0;
315 uart_setreg(bas, REG_IER, ier);
316 uart_barrier(bas);
317
318 /* Disable the FIFO (if present). */
319 uart_setreg(bas, REG_FCR, 0);
320 uart_barrier(bas);
321
322 /* Set RTS & DTR. */
323 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
324 uart_barrier(bas);
325
326 lpc_ns8250_clrint(bas);
327}
328
329static void
330lpc_ns8250_term(struct uart_bas *bas)
331{
332
333 /* Clear RTS & DTR. */
334 uart_setreg(bas, REG_MCR, MCR_IE);
335 uart_barrier(bas);
336}
337
338static void
339lpc_ns8250_putc(struct uart_bas *bas, int c)
340{
341 int limit;
342
343 limit = 250000;
344 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
345 DELAY(4);
346 uart_setreg(bas, REG_DATA, c);
347 uart_barrier(bas);
348 limit = 250000;
349 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
350 DELAY(4);
351}
352
353static int
354lpc_ns8250_rxready(struct uart_bas *bas)
355{
356
357 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
358}
359
360static int
361lpc_ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
362{
363 int c;
364
365 uart_lock(hwmtx);
366
367 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
368 uart_unlock(hwmtx);
369 DELAY(4);
370 uart_lock(hwmtx);
371 }
372
373 c = uart_getreg(bas, REG_DATA);
374
375 uart_unlock(hwmtx);
376
377 return (c);
378}
379
380/*
381 * High-level UART interface.
382 */
383struct lpc_ns8250_softc {
384 struct uart_softc base;
385 uint8_t fcr;
386 uint8_t ier;
387 uint8_t mcr;
388
389 uint8_t ier_mask;
390 uint8_t ier_rxbits;
391};
392
393static int lpc_ns8250_bus_attach(struct uart_softc *);
394static int lpc_ns8250_bus_detach(struct uart_softc *);
395static int lpc_ns8250_bus_flush(struct uart_softc *, int);
396static int lpc_ns8250_bus_getsig(struct uart_softc *);
397static int lpc_ns8250_bus_ioctl(struct uart_softc *, int, intptr_t);
398static int lpc_ns8250_bus_ipend(struct uart_softc *);
399static int lpc_ns8250_bus_param(struct uart_softc *, int, int, int, int);
400static int lpc_ns8250_bus_probe(struct uart_softc *);
401static int lpc_ns8250_bus_receive(struct uart_softc *);
402static int lpc_ns8250_bus_setsig(struct uart_softc *, int);
403static int lpc_ns8250_bus_transmit(struct uart_softc *);
404static void lpc_ns8250_bus_grab(struct uart_softc *);
405static void lpc_ns8250_bus_ungrab(struct uart_softc *);
406
407static kobj_method_t lpc_ns8250_methods[] = {
408 KOBJMETHOD(uart_attach, lpc_ns8250_bus_attach),
409 KOBJMETHOD(uart_detach, lpc_ns8250_bus_detach),
410 KOBJMETHOD(uart_flush, lpc_ns8250_bus_flush),
411 KOBJMETHOD(uart_getsig, lpc_ns8250_bus_getsig),
412 KOBJMETHOD(uart_ioctl, lpc_ns8250_bus_ioctl),
413 KOBJMETHOD(uart_ipend, lpc_ns8250_bus_ipend),
414 KOBJMETHOD(uart_param, lpc_ns8250_bus_param),
415 KOBJMETHOD(uart_probe, lpc_ns8250_bus_probe),
416 KOBJMETHOD(uart_receive, lpc_ns8250_bus_receive),
417 KOBJMETHOD(uart_setsig, lpc_ns8250_bus_setsig),
418 KOBJMETHOD(uart_transmit, lpc_ns8250_bus_transmit),
419 KOBJMETHOD(uart_grab, lpc_ns8250_bus_grab),
420 KOBJMETHOD(uart_ungrab, lpc_ns8250_bus_ungrab),
421 { 0, 0 }
422};
423
424struct uart_class uart_lpc_class = {
425 "lpc_ns8250",
426 lpc_ns8250_methods,
427 sizeof(struct lpc_ns8250_softc),
428 .uc_ops = &uart_lpc_ns8250_ops,
429 .uc_range = 8,
430 .uc_rclk = DEFAULT_RCLK
431};
432
433#define SIGCHG(c, i, s, d) \
434 if (c) { \
435 i |= (i & s) ? s : s | d; \
436 } else { \
437 i = (i & s) ? (i & ~s) | d : i; \
438 }
439
440static int
441lpc_ns8250_bus_attach(struct uart_softc *sc)
442{
443 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
444 struct uart_bas *bas;
445 unsigned int ivar;
446
447 bas = &sc->sc_bas;
448
449 lpc_ns8250->mcr = uart_getreg(bas, REG_MCR);
450 lpc_ns8250->fcr = FCR_ENABLE | FCR_DMA;
451 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
452 &ivar)) {
453 if (UART_FLAGS_FCR_RX_LOW(ivar))
454 lpc_ns8250->fcr |= FCR_RX_LOW;
455 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
456 lpc_ns8250->fcr |= FCR_RX_MEDL;
457 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
458 lpc_ns8250->fcr |= FCR_RX_HIGH;
459 else
460 lpc_ns8250->fcr |= FCR_RX_MEDH;
461 } else
462 lpc_ns8250->fcr |= FCR_RX_HIGH;
463
464 /* Get IER mask */
465 ivar = 0xf0;
466 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
467 &ivar);
468 lpc_ns8250->ier_mask = (uint8_t)(ivar & 0xff);
469
470 /* Get IER RX interrupt bits */
471 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
472 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
473 &ivar);
474 lpc_ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
475
476 uart_setreg(bas, REG_FCR, lpc_ns8250->fcr);
477 uart_barrier(bas);
478 lpc_ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
479
480 if (lpc_ns8250->mcr & MCR_DTR)
481 sc->sc_hwsig |= SER_DTR;
482 if (lpc_ns8250->mcr & MCR_RTS)
483 sc->sc_hwsig |= SER_RTS;
484 lpc_ns8250_bus_getsig(sc);
485
486 lpc_ns8250_clrint(bas);
487 lpc_ns8250->ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask;
488 lpc_ns8250->ier |= lpc_ns8250->ier_rxbits;
489 uart_setreg(bas, REG_IER, lpc_ns8250->ier);
490 uart_barrier(bas);
491
492 return (0);
493}
494
495static int
496lpc_ns8250_bus_detach(struct uart_softc *sc)
497{
498 struct lpc_ns8250_softc *lpc_ns8250;
499 struct uart_bas *bas;
500 u_char ier;
501
502 lpc_ns8250 = (struct lpc_ns8250_softc *)sc;
503 bas = &sc->sc_bas;
504 ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask;
505 uart_setreg(bas, REG_IER, ier);
506 uart_barrier(bas);
507 lpc_ns8250_clrint(bas);
508 return (0);
509}
510
511static int
512lpc_ns8250_bus_flush(struct uart_softc *sc, int what)
513{
514 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
515 struct uart_bas *bas;
516 int error;
517
518 bas = &sc->sc_bas;
519 uart_lock(sc->sc_hwmtx);
520 if (sc->sc_rxfifosz > 1) {
521 lpc_ns8250_flush(bas, what);
522 uart_setreg(bas, REG_FCR, lpc_ns8250->fcr);
523 uart_barrier(bas);
524 error = 0;
525 } else
526 error = lpc_ns8250_drain(bas, what);
527 uart_unlock(sc->sc_hwmtx);
528 return (error);
529}
530
531static int
532lpc_ns8250_bus_getsig(struct uart_softc *sc)
533{
534 uint32_t new, old, sig;
535 uint8_t msr;
536
537 do {
538 old = sc->sc_hwsig;
539 sig = old;
540 uart_lock(sc->sc_hwmtx);
541 msr = uart_getreg(&sc->sc_bas, REG_MSR);
542 uart_unlock(sc->sc_hwmtx);
543 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
544 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
545 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
546 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
547 new = sig & ~SER_MASK_DELTA;
548 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
549 return (sig);
550}
551
552static int
553lpc_ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
554{
555 struct uart_bas *bas;
556 int baudrate, divisor, error;
557 uint8_t efr, lcr;
558
559 bas = &sc->sc_bas;
560 error = 0;
561 uart_lock(sc->sc_hwmtx);
562 switch (request) {
563 case UART_IOCTL_BREAK:
564 lcr = uart_getreg(bas, REG_LCR);
565 if (data)
566 lcr |= LCR_SBREAK;
567 else
568 lcr &= ~LCR_SBREAK;
569 uart_setreg(bas, REG_LCR, lcr);
570 uart_barrier(bas);
571 break;
572 case UART_IOCTL_IFLOW:
573 lcr = uart_getreg(bas, REG_LCR);
574 uart_barrier(bas);
575 uart_setreg(bas, REG_LCR, 0xbf);
576 uart_barrier(bas);
577 efr = uart_getreg(bas, REG_EFR);
578 if (data)
579 efr |= EFR_RTS;
580 else
581 efr &= ~EFR_RTS;
582 uart_setreg(bas, REG_EFR, efr);
583 uart_barrier(bas);
584 uart_setreg(bas, REG_LCR, lcr);
585 uart_barrier(bas);
586 break;
587 case UART_IOCTL_OFLOW:
588 lcr = uart_getreg(bas, REG_LCR);
589 uart_barrier(bas);
590 uart_setreg(bas, REG_LCR, 0xbf);
591 uart_barrier(bas);
592 efr = uart_getreg(bas, REG_EFR);
593 if (data)
594 efr |= EFR_CTS;
595 else
596 efr &= ~EFR_CTS;
597 uart_setreg(bas, REG_EFR, efr);
598 uart_barrier(bas);
599 uart_setreg(bas, REG_LCR, lcr);
600 uart_barrier(bas);
601 break;
602 case UART_IOCTL_BAUD:
603 lcr = uart_getreg(bas, REG_LCR);
604 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
605 uart_barrier(bas);
606 divisor = uart_getreg(bas, REG_DLL) |
607 (uart_getreg(bas, REG_DLH) << 8);
608 uart_barrier(bas);
609 uart_setreg(bas, REG_LCR, lcr);
610 uart_barrier(bas);
611 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
612 if (baudrate > 0)
613 *(int*)data = baudrate;
614 else
615 error = ENXIO;
616 break;
617 default:
618 error = EINVAL;
619 break;
620 }
621 uart_unlock(sc->sc_hwmtx);
622 return (error);
623}
624
625static int
626lpc_ns8250_bus_ipend(struct uart_softc *sc)
627{
628 struct uart_bas *bas;
629 struct lpc_ns8250_softc *lpc_ns8250;
630 int ipend;
631 uint8_t iir, lsr;
632
633 lpc_ns8250 = (struct lpc_ns8250_softc *)sc;
634 bas = &sc->sc_bas;
635 uart_lock(sc->sc_hwmtx);
636 iir = uart_getreg(bas, REG_IIR);
637 if (iir & IIR_NOPEND) {
638 uart_unlock(sc->sc_hwmtx);
639 return (0);
640 }
641 ipend = 0;
642 if (iir & IIR_RXRDY) {
643 lsr = uart_getreg(bas, REG_LSR);
644 if (lsr & LSR_OE)
645 ipend |= SER_INT_OVERRUN;
646 if (lsr & LSR_BI)
647 ipend |= SER_INT_BREAK;
648 if (lsr & LSR_RXRDY)
649 ipend |= SER_INT_RXREADY;
650 } else {
651 if (iir & IIR_TXRDY) {
652 ipend |= SER_INT_TXIDLE;
653 uart_setreg(bas, REG_IER, lpc_ns8250->ier);
654 } else
655 ipend |= SER_INT_SIGCHG;
656 }
657 if (ipend == 0)
658 lpc_ns8250_clrint(bas);
659 uart_unlock(sc->sc_hwmtx);
660 return (ipend);
661}
662
663static int
664lpc_ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
665 int stopbits, int parity)
666{
667 struct uart_bas *bas;
668 int error;
669
670 bas = &sc->sc_bas;
671 uart_lock(sc->sc_hwmtx);
672 error = lpc_ns8250_param(bas, baudrate, databits, stopbits, parity);
673 uart_unlock(sc->sc_hwmtx);
674 return (error);
675}
676
677static int
678lpc_ns8250_bus_probe(struct uart_softc *sc)
679{
680 struct lpc_ns8250_softc *lpc_ns8250;
681 struct uart_bas *bas;
682 int count, delay, error, limit;
683 uint8_t lsr, mcr, ier;
684
685 lpc_ns8250 = (struct lpc_ns8250_softc *)sc;
686 bas = &sc->sc_bas;
687
688 error = lpc_ns8250_probe(bas);
689 if (error)
690 return (error);
691
692 mcr = MCR_IE;
693 if (sc->sc_sysdev == NULL) {
694 /* By using lpc_ns8250_init() we also set DTR and RTS. */
695 lpc_ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
696 } else
697 mcr |= MCR_DTR | MCR_RTS;
698
699 error = lpc_ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
700 if (error)
701 return (error);
702
703 /*
704 * Set loopback mode. This avoids having garbage on the wire and
705 * also allows us send and receive data. We set DTR and RTS to
706 * avoid the possibility that automatic flow-control prevents
707 * any data from being sent.
708 */
709 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
710 uart_barrier(bas);
711
712 /*
713 * Enable FIFOs. And check that the UART has them. If not, we're
714 * done. Since this is the first time we enable the FIFOs, we reset
715 * them.
716 */
717 uart_setreg(bas, REG_FCR, FCR_ENABLE);
718 uart_barrier(bas);
719 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
720 /*
721 * NS16450 or INS8250. We don't bother to differentiate
722 * between them. They're too old to be interesting.
723 */
724 uart_setreg(bas, REG_MCR, mcr);
725 uart_barrier(bas);
726 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
727 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
728 return (0);
729 }
730
731 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
732 uart_barrier(bas);
733
734 count = 0;
735 delay = lpc_ns8250_delay(bas);
736
737 /* We have FIFOs. Drain the transmitter and receiver. */
738 error = lpc_ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
739 if (error) {
740 uart_setreg(bas, REG_MCR, mcr);
741 uart_setreg(bas, REG_FCR, 0);
742 uart_barrier(bas);
743 goto done;
744 }
745
746 /*
747 * We should have a sufficiently clean "pipe" to determine the
748 * size of the FIFOs. We send as much characters as is reasonable
749 * and wait for the overflow bit in the LSR register to be
750 * asserted, counting the characters as we send them. Based on
751 * that count we know the FIFO size.
752 */
753 do {
754 uart_setreg(bas, REG_DATA, 0);
755 uart_barrier(bas);
756 count++;
757
758 limit = 30;
759 lsr = 0;
760 /*
761 * LSR bits are cleared upon read, so we must accumulate
762 * them to be able to test LSR_OE below.
763 */
764 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
765 --limit)
766 DELAY(delay);
767 if (limit == 0) {
768 ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask;
769 uart_setreg(bas, REG_IER, ier);
770 uart_setreg(bas, REG_MCR, mcr);
771 uart_setreg(bas, REG_FCR, 0);
772 uart_barrier(bas);
773 count = 0;
774 goto done;
775 }
776 } while ((lsr & LSR_OE) == 0 && count < 130);
777 count--;
778
779 uart_setreg(bas, REG_MCR, mcr);
780
781 /* Reset FIFOs. */
782 lpc_ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
783
784done:
785 sc->sc_rxfifosz = 64;
786 device_set_desc(sc->sc_dev, "LPC32x0 UART with FIFOs");
787
788 /*
789 * Force the Tx FIFO size to 16 bytes for now. We don't program the
790 * Tx trigger. Also, we assume that all data has been sent when the
791 * interrupt happens.
792 */
793 sc->sc_txfifosz = 16;
794
795#if 0
796 /*
797 * XXX there are some issues related to hardware flow control and
798 * it's likely that uart(4) is the cause. This basicly needs more
799 * investigation, but we avoid using for hardware flow control
800 * until then.
801 */
802 /* 16650s or higher have automatic flow control. */
803 if (sc->sc_rxfifosz > 16) {
804 sc->sc_hwiflow = 1;
805 sc->sc_hwoflow = 1;
806 }
807#endif
808 return (0);
809}
810
811static int
812lpc_ns8250_bus_receive(struct uart_softc *sc)
813{
814 struct uart_bas *bas;
815 int xc;
816 uint8_t lsr;
817
818 bas = &sc->sc_bas;
819 uart_lock(sc->sc_hwmtx);
820 lsr = uart_getreg(bas, REG_LSR);
821 while (lsr & LSR_RXRDY) {
822 if (uart_rx_full(sc)) {
823 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
824 break;
825 }
826 xc = uart_getreg(bas, REG_DATA);
827 if (lsr & LSR_FE)
828 xc |= UART_STAT_FRAMERR;
829 if (lsr & LSR_PE)
830 xc |= UART_STAT_PARERR;
831 uart_rx_put(sc, xc);
832 lsr = uart_getreg(bas, REG_LSR);
833 }
834 /* Discard everything left in the Rx FIFO. */
835 while (lsr & LSR_RXRDY) {
836 (void)uart_getreg(bas, REG_DATA);
837 uart_barrier(bas);
838 lsr = uart_getreg(bas, REG_LSR);
839 }
840 uart_unlock(sc->sc_hwmtx);
841 return (0);
842}
843
844static int
845lpc_ns8250_bus_setsig(struct uart_softc *sc, int sig)
846{
847 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
848 struct uart_bas *bas;
849 uint32_t new, old;
850
851 bas = &sc->sc_bas;
852 do {
853 old = sc->sc_hwsig;
854 new = old;
855 if (sig & SER_DDTR) {
856 SIGCHG(sig & SER_DTR, new, SER_DTR,
857 SER_DDTR);
858 }
859 if (sig & SER_DRTS) {
860 SIGCHG(sig & SER_RTS, new, SER_RTS,
861 SER_DRTS);
862 }
863 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
864 uart_lock(sc->sc_hwmtx);
865 lpc_ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
866 if (new & SER_DTR)
867 lpc_ns8250->mcr |= MCR_DTR;
868 if (new & SER_RTS)
869 lpc_ns8250->mcr |= MCR_RTS;
870 uart_setreg(bas, REG_MCR, lpc_ns8250->mcr);
871 uart_barrier(bas);
872 uart_unlock(sc->sc_hwmtx);
873 return (0);
874}
875
876static int
877lpc_ns8250_bus_transmit(struct uart_softc *sc)
878{
879 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
880 struct uart_bas *bas;
881 int i;
882
883 bas = &sc->sc_bas;
884 uart_lock(sc->sc_hwmtx);
885 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
886 ;
887 uart_setreg(bas, REG_IER, lpc_ns8250->ier | IER_ETXRDY);
888 uart_barrier(bas);
889 for (i = 0; i < sc->sc_txdatasz; i++) {
890 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
891 uart_barrier(bas);
892 }
893 sc->sc_txbusy = 1;
894 uart_unlock(sc->sc_hwmtx);
895 return (0);
896}
897
898void
899lpc_ns8250_bus_grab(struct uart_softc *sc)
900{
901 struct uart_bas *bas = &sc->sc_bas;
902
903 /*
904 * turn off all interrupts to enter polling mode. Leave the
905 * saved mask alone. We'll restore whatever it was in ungrab.
906 * All pending interupt signals are reset when IER is set to 0.
907 */
908 uart_lock(sc->sc_hwmtx);
909 uart_setreg(bas, REG_IER, 0);
910 uart_barrier(bas);
911 uart_unlock(sc->sc_hwmtx);
912}
913
914void
915lpc_ns8250_bus_ungrab(struct uart_softc *sc)
916{
917 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
918 struct uart_bas *bas = &sc->sc_bas;
919
920 /*
921 * Restore previous interrupt mask
922 */
923 uart_lock(sc->sc_hwmtx);
924 uart_setreg(bas, REG_IER, lpc_ns8250->ier);
925 uart_barrier(bas);
926 uart_unlock(sc->sc_hwmtx);
927}
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