| tw_cl_intr.c (144966) | tw_cl_intr.c (152213) |
|---|---|
| 1/* 2 * Copyright (c) 2004-05 Applied Micro Circuits Corporation. 3 * Copyright (c) 2004-05 Vinod Kashyap 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 10 unchanged lines hidden (view full) --- 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * | 1/* 2 * Copyright (c) 2004-05 Applied Micro Circuits Corporation. 3 * Copyright (c) 2004-05 Vinod Kashyap 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 10 unchanged lines hidden (view full) --- 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * |
| 27 * $FreeBSD: head/sys/dev/twa/tw_cl_intr.c 144966 2005-04-12 22:07:11Z vkashyap $ | 27 * $FreeBSD: head/sys/dev/twa/tw_cl_intr.c 152213 2005-11-08 22:51:43Z vkashyap $ |
| 28 */ 29 30/* 31 * AMCC'S 3ware driver for 9000 series storage controllers. 32 * 33 * Author: Vinod Kashyap 34 */ 35 --- 29 unchanged lines hidden (view full) --- 65 struct tw_cli_ctlr_context *ctlr = 66 (struct tw_cli_ctlr_context *)(ctlr_handle->cl_ctlr_ctxt); 67 TW_UINT32 status_reg; 68 TW_INT32 rc = TW_CL_FALSE; 69 70 tw_cli_dbg_printf(10, ctlr_handle, tw_osl_cur_func(), "entered"); 71 72 /* | 28 */ 29 30/* 31 * AMCC'S 3ware driver for 9000 series storage controllers. 32 * 33 * Author: Vinod Kashyap 34 */ 35 --- 29 unchanged lines hidden (view full) --- 65 struct tw_cli_ctlr_context *ctlr = 66 (struct tw_cli_ctlr_context *)(ctlr_handle->cl_ctlr_ctxt); 67 TW_UINT32 status_reg; 68 TW_INT32 rc = TW_CL_FALSE; 69 70 tw_cli_dbg_printf(10, ctlr_handle, tw_osl_cur_func(), "entered"); 71 72 /* |
| 73 * Serialize access to this function so multiple threads don't try to 74 * do the same thing (such as clearing interrupt bits). | 73 * Synchronize access between writes to command and control registers 74 * in 64-bit environments, on G66. |
| 75 */ | 75 */ |
| 76 tw_osl_get_lock(ctlr_handle, ctlr->intr_lock); | 76 if (ctlr->state & TW_CLI_CTLR_STATE_G66_WORKAROUND_NEEDED) 77 tw_osl_get_lock(ctlr_handle, ctlr->io_lock); |
| 77 78 /* Read the status register to determine the type of interrupt. */ 79 status_reg = TW_CLI_READ_STATUS_REGISTER(ctlr_handle); 80 if (tw_cli_check_ctlr_state(ctlr, status_reg)) 81 goto out; 82 83 /* Clear the interrupt. */ 84 if (status_reg & TWA_STATUS_HOST_INTERRUPT) { --- 24 unchanged lines hidden (view full) --- 109 tw_cli_dbg_printf(10, ctlr_handle, tw_osl_cur_func(), 110 "Response interrupt"); 111 TW_CLI_WRITE_CONTROL_REGISTER(ctlr_handle, 112 TWA_CONTROL_MASK_RESPONSE_INTERRUPT); 113 ctlr->resp_intr_pending = 1; 114 rc |= TW_CL_TRUE; /* request for a deferred isr call */ 115 } 116out: | 78 79 /* Read the status register to determine the type of interrupt. */ 80 status_reg = TW_CLI_READ_STATUS_REGISTER(ctlr_handle); 81 if (tw_cli_check_ctlr_state(ctlr, status_reg)) 82 goto out; 83 84 /* Clear the interrupt. */ 85 if (status_reg & TWA_STATUS_HOST_INTERRUPT) { --- 24 unchanged lines hidden (view full) --- 110 tw_cli_dbg_printf(10, ctlr_handle, tw_osl_cur_func(), 111 "Response interrupt"); 112 TW_CLI_WRITE_CONTROL_REGISTER(ctlr_handle, 113 TWA_CONTROL_MASK_RESPONSE_INTERRUPT); 114 ctlr->resp_intr_pending = 1; 115 rc |= TW_CL_TRUE; /* request for a deferred isr call */ 116 } 117out: |
| 117 tw_osl_free_lock(ctlr_handle, ctlr->intr_lock); | 118 if (ctlr->state & TW_CLI_CTLR_STATE_G66_WORKAROUND_NEEDED) 119 tw_osl_free_lock(ctlr_handle, ctlr->io_lock); |
| 118 119 return(rc); 120} 121 122 123 124/* 125 * Function name: tw_cl_deferred_interrupt --- 188 unchanged lines hidden (view full) --- 314 315 /* 316 * Remove the request from the busy queue, mark it as complete, 317 * and enqueue it in the complete queue. 318 */ 319 tw_cli_req_q_remove_item(req, TW_CLI_BUSY_Q); 320 req->state = TW_CLI_REQ_STATE_COMPLETE; 321 tw_cli_req_q_insert_tail(req, TW_CLI_COMPLETE_Q); | 120 121 return(rc); 122} 123 124 125 126/* 127 * Function name: tw_cl_deferred_interrupt --- 188 unchanged lines hidden (view full) --- 316 317 /* 318 * Remove the request from the busy queue, mark it as complete, 319 * and enqueue it in the complete queue. 320 */ 321 tw_cli_req_q_remove_item(req, TW_CLI_BUSY_Q); 322 req->state = TW_CLI_REQ_STATE_COMPLETE; 323 tw_cli_req_q_insert_tail(req, TW_CLI_COMPLETE_Q); |
| 324 |
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| 322#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST | 325#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST |
| 326 tw_osl_free_lock(ctlr->ctlr_handle, ctlr->intr_lock); |
|
| 323 /* Call the CL internal callback, if there's one. */ 324 if (req->tw_cli_callback) 325 req->tw_cli_callback(req); | 327 /* Call the CL internal callback, if there's one. */ 328 if (req->tw_cli_callback) 329 req->tw_cli_callback(req); |
| 330 tw_osl_get_lock(ctlr->ctlr_handle, ctlr->intr_lock); |
|
| 326#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */ 327 } 328 329 /* Unmask the response interrupt. */ 330 TW_CLI_WRITE_CONTROL_REGISTER(ctlr->ctlr_handle, 331 TWA_CONTROL_UNMASK_RESPONSE_INTERRUPT); 332 333 tw_osl_free_lock(ctlr->ctlr_handle, ctlr->intr_lock); --- 493 unchanged lines hidden --- | 331#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */ 332 } 333 334 /* Unmask the response interrupt. */ 335 TW_CLI_WRITE_CONTROL_REGISTER(ctlr->ctlr_handle, 336 TWA_CONTROL_UNMASK_RESPONSE_INTERRUPT); 337 338 tw_osl_free_lock(ctlr->ctlr_handle, ctlr->intr_lock); --- 493 unchanged lines hidden --- |