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tw_cl_init.c (144966) tw_cl_init.c (152213)
1/*
2 * Copyright (c) 2004-05 Applied Micro Circuits Corporation.
3 * Copyright (c) 2004-05 Vinod Kashyap
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 10 unchanged lines hidden (view full) ---

19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
1/*
2 * Copyright (c) 2004-05 Applied Micro Circuits Corporation.
3 * Copyright (c) 2004-05 Vinod Kashyap
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 10 unchanged lines hidden (view full) ---

19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/dev/twa/tw_cl_init.c 144966 2005-04-12 22:07:11Z vkashyap $
27 * $FreeBSD: head/sys/dev/twa/tw_cl_init.c 152213 2005-11-08 22:51:43Z vkashyap $
28 */
29
30/*
31 * AMCC'S 3ware driver for 9000 series storage controllers.
32 *
33 * Author: Vinod Kashyap
34 */
35

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56 * device_id -- device id of the controller
57 * Output: None
58 * Return value: TW_CL_TRUE-- controller supported
59 * TW_CL_FALSE-- controller not supported
60 */
61TW_INT32
62tw_cl_ctlr_supported(TW_INT32 vendor_id, TW_INT32 device_id)
63{
28 */
29
30/*
31 * AMCC'S 3ware driver for 9000 series storage controllers.
32 *
33 * Author: Vinod Kashyap
34 */
35

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56 * device_id -- device id of the controller
57 * Output: None
58 * Return value: TW_CL_TRUE-- controller supported
59 * TW_CL_FALSE-- controller not supported
60 */
61TW_INT32
62tw_cl_ctlr_supported(TW_INT32 vendor_id, TW_INT32 device_id)
63{
64 if ((vendor_id == TW_CL_VENDOR_ID) && (device_id == TW_CL_DEVICE_ID_9K))
64 if ((vendor_id == TW_CL_VENDOR_ID) &&
65 ((device_id == TW_CL_DEVICE_ID_9K) ||
66 (device_id == TW_CL_DEVICE_ID_9K_X)))
65 return(TW_CL_TRUE);
66 return(TW_CL_FALSE);
67}
68
69
70
71/*
67 return(TW_CL_TRUE);
68 return(TW_CL_FALSE);
69}
70
71
72
73/*
74 * Function name: tw_cl_get_pci_bar_info
75 * Description: Returns PCI BAR info.
76 *
77 * Input: device_id -- device id of the controller
78 * bar_type -- type of PCI BAR in question
79 * Output: bar_num -- PCI BAR number corresponding to bar_type
80 * bar0_offset -- byte offset from BAR 0 (0x10 in
81 * PCI config space)
82 * bar_size -- size, in bytes, of the BAR in question
83 * Return value: 0 -- success
84 * non-zero -- failure
85 */
86TW_INT32
87tw_cl_get_pci_bar_info(TW_INT32 device_id, TW_INT32 bar_type,
88 TW_INT32 *bar_num, TW_INT32 *bar0_offset, TW_INT32 *bar_size)
89{
90 TW_INT32 error = TW_OSL_ESUCCESS;
91
92 switch(device_id) {
93 case TW_CL_DEVICE_ID_9K:
94 switch(bar_type) {
95 case TW_CL_BAR_TYPE_IO:
96 *bar_num = 0;
97 *bar0_offset = 0;
98 *bar_size = 4;
99 break;
100
101 case TW_CL_BAR_TYPE_MEM:
102 *bar_num = 1;
103 *bar0_offset = 0x4;
104 *bar_size = 8;
105 break;
106
107 case TW_CL_BAR_TYPE_SBUF:
108 *bar_num = 2;
109 *bar0_offset = 0xC;
110 *bar_size = 8;
111 break;
112 }
113 break;
114
115 case TW_CL_DEVICE_ID_9K_X:
116 switch(bar_type) {
117 case TW_CL_BAR_TYPE_IO:
118 *bar_num = 2;
119 *bar0_offset = 0x10;
120 *bar_size = 4;
121 break;
122
123 case TW_CL_BAR_TYPE_MEM:
124 *bar_num = 1;
125 *bar0_offset = 0x8;
126 *bar_size = 8;
127 break;
128
129 case TW_CL_BAR_TYPE_SBUF:
130 *bar_num = 0;
131 *bar0_offset = 0;
132 *bar_size = 8;
133 break;
134 }
135 break;
136
137 default:
138 error = TW_OSL_ENOTTY;
139 break;
140 }
141
142 return(error);
143}
144
145
146
147/*
72 * Function name: tw_cl_get_mem_requirements
73 * Description: Provides info about Common Layer requirements for a
74 * controller, given the controller type (in 'flags').
75 * Input: ctlr_handle -- controller handle
76 * flags -- more info passed by the OS Layer
148 * Function name: tw_cl_get_mem_requirements
149 * Description: Provides info about Common Layer requirements for a
150 * controller, given the controller type (in 'flags').
151 * Input: ctlr_handle -- controller handle
152 * flags -- more info passed by the OS Layer
153 * device_id -- device id of the controller
77 * max_simult_reqs -- maximum # of simultaneous
78 * requests that the OS Layer expects
79 * the Common Layer to support
80 * max_aens -- maximun # of AEN's needed to be supported
81 * Output: alignment -- alignment needed for all DMA'able
82 * buffers
83 * sg_size_factor -- every SG element should have a size
84 * that's a multiple of this number

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93 * per request for non-DMA purposes,
94 * if applicable
95 * Output: None
96 * Return value: 0 -- success
97 * non-zero-- failure
98 */
99TW_INT32
100tw_cl_get_mem_requirements(struct tw_cl_ctlr_handle *ctlr_handle,
154 * max_simult_reqs -- maximum # of simultaneous
155 * requests that the OS Layer expects
156 * the Common Layer to support
157 * max_aens -- maximun # of AEN's needed to be supported
158 * Output: alignment -- alignment needed for all DMA'able
159 * buffers
160 * sg_size_factor -- every SG element should have a size
161 * that's a multiple of this number

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170 * per request for non-DMA purposes,
171 * if applicable
172 * Output: None
173 * Return value: 0 -- success
174 * non-zero-- failure
175 */
176TW_INT32
177tw_cl_get_mem_requirements(struct tw_cl_ctlr_handle *ctlr_handle,
101 TW_UINT32 flags, TW_INT32 max_simult_reqs, TW_INT32 max_aens,
102 TW_UINT32 *alignment, TW_UINT32 *sg_size_factor,
178 TW_UINT32 flags, TW_INT32 device_id, TW_INT32 max_simult_reqs,
179 TW_INT32 max_aens, TW_UINT32 *alignment, TW_UINT32 *sg_size_factor,
103 TW_UINT32 *non_dma_mem_size, TW_UINT32 *dma_mem_size
104#ifdef TW_OSL_FLASH_FIRMWARE
105 , TW_UINT32 *flash_dma_mem_size
106#endif /* TW_OSL_FLASH_FIRMWARE */
107#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
108 , TW_UINT32 *per_req_dma_mem_size
109#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
110#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
111 , TW_UINT32 *per_req_non_dma_mem_size
112#endif /* TW_OSL_N0N_DMA_MEM_ALLOC_PER_REQUEST */
113 )
114{
180 TW_UINT32 *non_dma_mem_size, TW_UINT32 *dma_mem_size
181#ifdef TW_OSL_FLASH_FIRMWARE
182 , TW_UINT32 *flash_dma_mem_size
183#endif /* TW_OSL_FLASH_FIRMWARE */
184#ifdef TW_OSL_DMA_MEM_ALLOC_PER_REQUEST
185 , TW_UINT32 *per_req_dma_mem_size
186#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
187#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
188 , TW_UINT32 *per_req_non_dma_mem_size
189#endif /* TW_OSL_N0N_DMA_MEM_ALLOC_PER_REQUEST */
190 )
191{
192 if (device_id == 0)
193 device_id = TW_CL_DEVICE_ID_9K;
194
115 if (max_simult_reqs > TW_CL_MAX_SIMULTANEOUS_REQUESTS) {
116 tw_cl_create_event(ctlr_handle, TW_CL_FALSE,
117 TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
118 0x1000, 0x1, TW_CL_SEVERITY_ERROR_STRING,
119 "Too many simultaneous requests to support!",
120 "requested = %d, supported = %d, error = %d\n",
121 max_simult_reqs, TW_CL_MAX_SIMULTANEOUS_REQUESTS,
122 TW_OSL_EBIG);
123 return(TW_OSL_EBIG);
124 }
125
195 if (max_simult_reqs > TW_CL_MAX_SIMULTANEOUS_REQUESTS) {
196 tw_cl_create_event(ctlr_handle, TW_CL_FALSE,
197 TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
198 0x1000, 0x1, TW_CL_SEVERITY_ERROR_STRING,
199 "Too many simultaneous requests to support!",
200 "requested = %d, supported = %d, error = %d\n",
201 max_simult_reqs, TW_CL_MAX_SIMULTANEOUS_REQUESTS,
202 TW_OSL_EBIG);
203 return(TW_OSL_EBIG);
204 }
205
126 *alignment = TWA_ALIGNMENT;
127 *sg_size_factor = TWA_SG_ELEMENT_SIZE_FACTOR;
206 *alignment = TWA_ALIGNMENT(device_id);
207 *sg_size_factor = TWA_SG_ELEMENT_SIZE_FACTOR(device_id);
128
129 /*
130 * Total non-DMA memory needed is the sum total of memory needed for
131 * the controller context, request packets (including the 1 needed for
132 * CL internal requests), and event packets.
133 */
134#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
135

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166#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
167
168
169#ifdef TW_OSL_FLASH_FIRMWARE
170
171 /* Memory needed to hold the firmware image while flashing. */
172 *flash_dma_mem_size =
173 ((tw_cli_fw_img_size / TW_CLI_NUM_FW_IMAGE_CHUNKS) +
208
209 /*
210 * Total non-DMA memory needed is the sum total of memory needed for
211 * the controller context, request packets (including the 1 needed for
212 * CL internal requests), and event packets.
213 */
214#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST
215

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246#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
247
248
249#ifdef TW_OSL_FLASH_FIRMWARE
250
251 /* Memory needed to hold the firmware image while flashing. */
252 *flash_dma_mem_size =
253 ((tw_cli_fw_img_size / TW_CLI_NUM_FW_IMAGE_CHUNKS) +
174 (TWA_SG_ELEMENT_SIZE_FACTOR - 1)) &
175 ~(TWA_SG_ELEMENT_SIZE_FACTOR - 1);
254 511) & ~511;
255/* (TWA_SG_ELEMENT_SIZE_FACTOR(device_id) - 1)) &
256 ~(TWA_SG_ELEMENT_SIZE_FACTOR(device_id) - 1); */
176
177#endif /* TW_OSL_FLASH_FIRMWARE */
178
179 return(0);
180}
181
182
183
184/*
185 * Function name: tw_cl_init_ctlr
186 * Description: Initializes driver data structures for the controller.
187 *
188 * Input: ctlr_handle -- controller handle
189 * flags -- more info passed by the OS Layer
257
258#endif /* TW_OSL_FLASH_FIRMWARE */
259
260 return(0);
261}
262
263
264
265/*
266 * Function name: tw_cl_init_ctlr
267 * Description: Initializes driver data structures for the controller.
268 *
269 * Input: ctlr_handle -- controller handle
270 * flags -- more info passed by the OS Layer
271 * device_id -- device id of the controller
190 * max_simult_reqs -- maximum # of simultaneous requests
191 * that the OS Layer expects the Common
192 * Layer to support
193 * max_aens -- maximun # of AEN's needed to be supported
194 * non_dma_mem -- ptr to allocated non-DMA memory
195 * dma_mem -- ptr to allocated DMA'able memory
196 * dma_mem_phys -- physical address of dma_mem
197 * flash_dma_mem -- ptr to allocated DMA'able memory
198 * needed for firmware flash, if applicable
199 * flash_dma_mem_phys -- physical address of flash_dma_mem
200 * Output: None
201 * Return value: 0 -- success
202 * non-zero-- failure
203 */
204TW_INT32
205tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags,
272 * max_simult_reqs -- maximum # of simultaneous requests
273 * that the OS Layer expects the Common
274 * Layer to support
275 * max_aens -- maximun # of AEN's needed to be supported
276 * non_dma_mem -- ptr to allocated non-DMA memory
277 * dma_mem -- ptr to allocated DMA'able memory
278 * dma_mem_phys -- physical address of dma_mem
279 * flash_dma_mem -- ptr to allocated DMA'able memory
280 * needed for firmware flash, if applicable
281 * flash_dma_mem_phys -- physical address of flash_dma_mem
282 * Output: None
283 * Return value: 0 -- success
284 * non-zero-- failure
285 */
286TW_INT32
287tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags,
206 TW_INT32 max_simult_reqs, TW_INT32 max_aens, TW_VOID *non_dma_mem,
207 TW_VOID *dma_mem, TW_UINT64 dma_mem_phys
288 TW_INT32 device_id, TW_INT32 max_simult_reqs, TW_INT32 max_aens,
289 TW_VOID *non_dma_mem, TW_VOID *dma_mem, TW_UINT64 dma_mem_phys
208#ifdef TW_OSL_FLASH_FIRMWARE
209 , TW_VOID *flash_dma_mem,
210 TW_UINT64 flash_dma_mem_phys
211#endif /* TW_OSL_FLASH_FIRMWARE */
212 )
213{
214 struct tw_cli_ctlr_context *ctlr;
215 struct tw_cli_req_context *req;

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275 free_non_dma_mem = (TW_UINT8 *)non_dma_mem;
276
277 ctlr = (struct tw_cli_ctlr_context *)free_non_dma_mem;
278 free_non_dma_mem += sizeof(struct tw_cli_ctlr_context);
279
280 ctlr_handle->cl_ctlr_ctxt = ctlr;
281 ctlr->ctlr_handle = ctlr_handle;
282
290#ifdef TW_OSL_FLASH_FIRMWARE
291 , TW_VOID *flash_dma_mem,
292 TW_UINT64 flash_dma_mem_phys
293#endif /* TW_OSL_FLASH_FIRMWARE */
294 )
295{
296 struct tw_cli_ctlr_context *ctlr;
297 struct tw_cli_req_context *req;

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357 free_non_dma_mem = (TW_UINT8 *)non_dma_mem;
358
359 ctlr = (struct tw_cli_ctlr_context *)free_non_dma_mem;
360 free_non_dma_mem += sizeof(struct tw_cli_ctlr_context);
361
362 ctlr_handle->cl_ctlr_ctxt = ctlr;
363 ctlr->ctlr_handle = ctlr_handle;
364
365 ctlr->device_id = (TW_UINT32)device_id;
366 ctlr->arch_id = TWA_ARCH_ID(device_id);
367 ctlr->flags = flags;
368 ctlr->sg_size_factor = TWA_SG_ELEMENT_SIZE_FACTOR(device_id);
283 ctlr->max_simult_reqs = max_simult_reqs + 1;
284 ctlr->max_aens_supported = max_aens;
369 ctlr->max_simult_reqs = max_simult_reqs + 1;
370 ctlr->max_aens_supported = max_aens;
285 ctlr->flags = flags;
286
287#ifdef TW_OSL_FLASH_FIRMWARE
288 ctlr->flash_dma_mem = flash_dma_mem;
289 ctlr->flash_dma_mem_phys = flash_dma_mem_phys;
290#endif /* TW_OSL_FLASH_FIRMWARE */
291
292 /* Initialize queues of CL internal request context packets. */
293 tw_cli_req_q_init(ctlr, TW_CLI_FREE_Q);
294 tw_cli_req_q_init(ctlr, TW_CLI_BUSY_Q);
295 tw_cli_req_q_init(ctlr, TW_CLI_PENDING_Q);
296 tw_cli_req_q_init(ctlr, TW_CLI_COMPLETE_Q);
297
298 /* Initialize all locks used by CL. */
299 ctlr->gen_lock = &(ctlr->gen_lock_handle);
300 tw_osl_init_lock(ctlr_handle, "tw_cl_gen_lock", ctlr->gen_lock);
301 ctlr->io_lock = &(ctlr->io_lock_handle);
302 tw_osl_init_lock(ctlr_handle, "tw_cl_io_lock", ctlr->io_lock);
303 /*
304 * If 64 bit cmd pkt addresses are used, we will need to serialize
371
372#ifdef TW_OSL_FLASH_FIRMWARE
373 ctlr->flash_dma_mem = flash_dma_mem;
374 ctlr->flash_dma_mem_phys = flash_dma_mem_phys;
375#endif /* TW_OSL_FLASH_FIRMWARE */
376
377 /* Initialize queues of CL internal request context packets. */
378 tw_cli_req_q_init(ctlr, TW_CLI_FREE_Q);
379 tw_cli_req_q_init(ctlr, TW_CLI_BUSY_Q);
380 tw_cli_req_q_init(ctlr, TW_CLI_PENDING_Q);
381 tw_cli_req_q_init(ctlr, TW_CLI_COMPLETE_Q);
382
383 /* Initialize all locks used by CL. */
384 ctlr->gen_lock = &(ctlr->gen_lock_handle);
385 tw_osl_init_lock(ctlr_handle, "tw_cl_gen_lock", ctlr->gen_lock);
386 ctlr->io_lock = &(ctlr->io_lock_handle);
387 tw_osl_init_lock(ctlr_handle, "tw_cl_io_lock", ctlr->io_lock);
388 /*
389 * If 64 bit cmd pkt addresses are used, we will need to serialize
305 * writes to the hardware (across registers), since existing hardware
306 * will get confused if, for example, we wrote the low 32 bits of the
307 * cmd pkt address, followed by a response interrupt mask to the
390 * writes to the hardware (across registers), since existing (G66)
391 * hardware will get confused if, for example, we wrote the low 32 bits
392 * of the cmd pkt address, followed by a response interrupt mask to the
308 * control register, followed by the high 32 bits of the cmd pkt
309 * address. It will then interpret the value written to the control
310 * register as the low cmd pkt address. So, for this case, we will
393 * control register, followed by the high 32 bits of the cmd pkt
394 * address. It will then interpret the value written to the control
395 * register as the low cmd pkt address. So, for this case, we will
311 * only use one lock (io_lock) by making io_lock & intr_lock one and
312 * the same.
396 * make a note that we will need to synchronize control register writes
397 * with command register writes.
313 */
398 */
314 if (ctlr->flags & TW_CL_64BIT_ADDRESSES)
399 if ((ctlr->flags & TW_CL_64BIT_ADDRESSES) &&
400 (ctlr->device_id == TW_CL_DEVICE_ID_9K)) {
401 ctlr->state |= TW_CLI_CTLR_STATE_G66_WORKAROUND_NEEDED;
315 ctlr->intr_lock = ctlr->io_lock;
402 ctlr->intr_lock = ctlr->io_lock;
316 else {
403 } else {
317 ctlr->intr_lock = &(ctlr->intr_lock_handle);
318 tw_osl_init_lock(ctlr_handle, "tw_cl_intr_lock",
319 ctlr->intr_lock);
320 }
321
322 /* Initialize CL internal request context packets. */
323 ctlr->req_ctxt_buf = (struct tw_cli_req_context *)free_non_dma_mem;
324 free_non_dma_mem += (sizeof(struct tw_cli_req_context) *

--- 151 unchanged lines hidden (view full) ---

476 28 /* max bytes before sglist */);
477
478#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
479
480 req->flags |= TW_CLI_REQ_FLAGS_INTERNAL;
481
482 /*
483 * Determine amount of memory needed to hold a chunk of the
404 ctlr->intr_lock = &(ctlr->intr_lock_handle);
405 tw_osl_init_lock(ctlr_handle, "tw_cl_intr_lock",
406 ctlr->intr_lock);
407 }
408
409 /* Initialize CL internal request context packets. */
410 ctlr->req_ctxt_buf = (struct tw_cli_req_context *)free_non_dma_mem;
411 free_non_dma_mem += (sizeof(struct tw_cli_req_context) *

--- 151 unchanged lines hidden (view full) ---

563 28 /* max bytes before sglist */);
564
565#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */
566
567 req->flags |= TW_CLI_REQ_FLAGS_INTERNAL;
568
569 /*
570 * Determine amount of memory needed to hold a chunk of the
484 * firmware image.
571 * firmware image. As yet, the Download_Firmware command does not
572 * support SG elements that are ctlr->sg_size_factor multiples. It
573 * requires them to be 512-byte multiples.
485 */
486 fw_img_chunk_size = ((tw_cli_fw_img_size / TW_CLI_NUM_FW_IMAGE_CHUNKS) +
574 */
575 fw_img_chunk_size = ((tw_cli_fw_img_size / TW_CLI_NUM_FW_IMAGE_CHUNKS) +
487 (TWA_SG_ELEMENT_SIZE_FACTOR - 1)) &
488 ~(TWA_SG_ELEMENT_SIZE_FACTOR - 1);
576 511) & ~511;
577/* (ctlr->sg_size_factor - 1)) &
578 ~(ctlr->sg_size_factor - 1); */
489
490 /* Calculate the actual number of chunks needed. */
491 num_chunks = (tw_cli_fw_img_size / fw_img_chunk_size) +
492 ((tw_cli_fw_img_size % fw_img_chunk_size) ? 1 : 0);
493
494 req->data = ctlr->flash_dma_mem;
495 req->data_phys = ctlr->flash_dma_mem_phys;
496

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523 remaining_img_size -= this_chunk_size;
524
525 tw_osl_memcpy(req->data, tw_cli_fw_img + (i * fw_img_chunk_size),
526 this_chunk_size);
527
528 /*
529 * The next line will effect only the last chunk.
530 */
579
580 /* Calculate the actual number of chunks needed. */
581 num_chunks = (tw_cli_fw_img_size / fw_img_chunk_size) +
582 ((tw_cli_fw_img_size % fw_img_chunk_size) ? 1 : 0);
583
584 req->data = ctlr->flash_dma_mem;
585 req->data_phys = ctlr->flash_dma_mem_phys;
586

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613 remaining_img_size -= this_chunk_size;
614
615 tw_osl_memcpy(req->data, tw_cli_fw_img + (i * fw_img_chunk_size),
616 this_chunk_size);
617
618 /*
619 * The next line will effect only the last chunk.
620 */
531 req->length = (this_chunk_size +
532 (TWA_SG_ELEMENT_SIZE_FACTOR - 1)) &
533 ~(TWA_SG_ELEMENT_SIZE_FACTOR - 1);
621 req->length = (this_chunk_size + 511) & ~511;
622/* (ctlr->sg_size_factor - 1)) &
623 ~(ctlr->sg_size_factor - 1); */
534
535 if (ctlr->flags & TW_CL_64BIT_ADDRESSES) {
536 ((struct tw_cl_sg_desc64 *)(cmd->sgl))[0].address =
537 TW_CL_SWAP64(req->data_phys);
538 ((struct tw_cl_sg_desc64 *)(cmd->sgl))[0].length =
539 TW_CL_SWAP32(req->length);
540 cmd->size = 2 + 3;
541 } else {

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654 cmd->unit = 0;
655 cmd->status = 0;
656 cmd->flags = 0;
657 cmd->param = 0; /* don't reload FPGA logic */
658
659 req->data = TW_CL_NULL;
660 req->length = 0;
661
624
625 if (ctlr->flags & TW_CL_64BIT_ADDRESSES) {
626 ((struct tw_cl_sg_desc64 *)(cmd->sgl))[0].address =
627 TW_CL_SWAP64(req->data_phys);
628 ((struct tw_cl_sg_desc64 *)(cmd->sgl))[0].length =
629 TW_CL_SWAP32(req->length);
630 cmd->size = 2 + 3;
631 } else {

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744 cmd->unit = 0;
745 cmd->status = 0;
746 cmd->flags = 0;
747 cmd->param = 0; /* don't reload FPGA logic */
748
749 req->data = TW_CL_NULL;
750 req->length = 0;
751
752 tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
753 TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
754 0x1017, 0x3, TW_CL_SEVERITY_INFO_STRING,
755 "Issuing hard (commanded) reset to the controller...",
756 " ");
757
662 error = tw_cli_submit_and_poll_request(req,
663 TW_CLI_REQUEST_TIMEOUT_PERIOD);
664 if (error) {
665 tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
666 TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
667 0x1007, 0x1, TW_CL_SEVERITY_ERROR_STRING,
668 "Hard reset request could not be posted",
669 "error = %d", error);

--- 8 unchanged lines hidden (view full) ---

678 &(req->cmd_pkt->cmd_hdr));
679 tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
680 TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
681 0x1008, 0x1, TW_CL_SEVERITY_ERROR_STRING,
682 "Hard reset request failed",
683 "error = %d", error);
684 }
685
758 error = tw_cli_submit_and_poll_request(req,
759 TW_CLI_REQUEST_TIMEOUT_PERIOD);
760 if (error) {
761 tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
762 TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
763 0x1007, 0x1, TW_CL_SEVERITY_ERROR_STRING,
764 "Hard reset request could not be posted",
765 "error = %d", error);

--- 8 unchanged lines hidden (view full) ---

774 &(req->cmd_pkt->cmd_hdr));
775 tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
776 TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
777 0x1008, 0x1, TW_CL_SEVERITY_ERROR_STRING,
778 "Hard reset request failed",
779 "error = %d", error);
780 }
781
782 if (ctlr->device_id == TW_CL_DEVICE_ID_9K_X) {
783 /*
784 * There's a hardware bug in the G133 ASIC, which can lead to
785 * PCI parity errors and hangs, if the host accesses any
786 * registers when the firmware is resetting the hardware, as
787 * part of a hard/soft reset. The window of time when the
788 * problem can occur is about 10 ms. Here, we will handshake
789 * with the firmware to find out when the firmware is pulling
790 * down the hardware reset pin, and wait for about 500 ms to
791 * make sure we don't access any hardware registers (for
792 * polling) during that window.
793 */
794 ctlr->state |= TW_CLI_CTLR_STATE_RESET_PHASE1_IN_PROGRESS;
795 while (tw_cli_find_response(ctlr,
796 TWA_RESET_PHASE1_NOTIFICATION_RESPONSE) != TW_OSL_ESUCCESS)
797 tw_osl_delay(10);
798 tw_osl_delay(TWA_RESET_PHASE1_WAIT_TIME_MS * 1000);
799 ctlr->state &= ~TW_CLI_CTLR_STATE_RESET_PHASE1_IN_PROGRESS;
800 }
801
802 /* Wait for the MC_RDY bit to get set. */
803 if ((error = tw_cli_poll_status(ctlr, TWA_STATUS_MICROCONTROLLER_READY,
804 TW_CLI_RESET_TIMEOUT_PERIOD))) {
805 tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
806 TW_CL_MESSAGE_SOURCE_COMMON_LAYER_EVENT,
807 0x1018, 0x1, TW_CL_SEVERITY_ERROR_STRING,
808 "Micro-ctlr not ready following hard reset",
809 "error = %d", error);
810 }
811
686out:
687 if (req)
688 tw_cli_req_q_insert_tail(req, TW_CLI_FREE_Q);
689 return(error);
690}
691
692#endif /* TW_OSL_FLASH_FIRMWARE */
693

--- 49 unchanged lines hidden (view full) ---

743 "Can't drain response queue",
744 "error = %d", error);
745 return(error);
746 }
747 /* Establish a logical connection with the controller. */
748 if ((error = tw_cli_init_connection(ctlr,
749 (TW_UINT16)(ctlr->max_simult_reqs),
750 TWA_EXTENDED_INIT_CONNECT, TWA_CURRENT_FW_SRL,
812out:
813 if (req)
814 tw_cli_req_q_insert_tail(req, TW_CLI_FREE_Q);
815 return(error);
816}
817
818#endif /* TW_OSL_FLASH_FIRMWARE */
819

--- 49 unchanged lines hidden (view full) ---

869 "Can't drain response queue",
870 "error = %d", error);
871 return(error);
872 }
873 /* Establish a logical connection with the controller. */
874 if ((error = tw_cli_init_connection(ctlr,
875 (TW_UINT16)(ctlr->max_simult_reqs),
876 TWA_EXTENDED_INIT_CONNECT, TWA_CURRENT_FW_SRL,
751 TWA_9000_ARCH_ID, TWA_CURRENT_FW_BRANCH,
752 TWA_CURRENT_FW_BUILD, &fw_on_ctlr_srl,
753 &fw_on_ctlr_arch_id, &fw_on_ctlr_branch,
754 &fw_on_ctlr_build, &init_connect_result))) {
877 (TW_UINT16)(ctlr->arch_id),
878 TWA_CURRENT_FW_BRANCH(ctlr->arch_id),
879 TWA_CURRENT_FW_BUILD(ctlr->arch_id),
880 &fw_on_ctlr_srl, &fw_on_ctlr_arch_id,
881 &fw_on_ctlr_branch, &fw_on_ctlr_build,
882 &init_connect_result))) {
755 tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
756 TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
757 0x100B, 0x2, TW_CL_SEVERITY_WARNING_STRING,
758 "Can't initialize connection in current mode",
759 "error = %d", error);
760 return(error);
761 }
762

--- 57 unchanged lines hidden (view full) ---

820 * or flash failed for some reason. See if we can at
821 * least work with the firmware on the controller in the
822 * current mode.
823 */
824 if (init_connect_result & TWA_CTLR_FW_COMPATIBLE) {
825 /* Yes, we can. Make note of the operating mode. */
826 if (init_connect_result & TWA_CTLR_FW_SAME_OR_NEWER) {
827 ctlr->working_srl = TWA_CURRENT_FW_SRL;
883 tw_cl_create_event(ctlr->ctlr_handle, TW_CL_FALSE,
884 TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
885 0x100B, 0x2, TW_CL_SEVERITY_WARNING_STRING,
886 "Can't initialize connection in current mode",
887 "error = %d", error);
888 return(error);
889 }
890

--- 57 unchanged lines hidden (view full) ---

948 * or flash failed for some reason. See if we can at
949 * least work with the firmware on the controller in the
950 * current mode.
951 */
952 if (init_connect_result & TWA_CTLR_FW_COMPATIBLE) {
953 /* Yes, we can. Make note of the operating mode. */
954 if (init_connect_result & TWA_CTLR_FW_SAME_OR_NEWER) {
955 ctlr->working_srl = TWA_CURRENT_FW_SRL;
828 ctlr->working_branch = TWA_CURRENT_FW_BRANCH;
829 ctlr->working_build = TWA_CURRENT_FW_BUILD;
956 ctlr->working_branch =
957 TWA_CURRENT_FW_BRANCH(ctlr->arch_id);
958 ctlr->working_build =
959 TWA_CURRENT_FW_BUILD(ctlr->arch_id);
830 } else {
831 ctlr->working_srl = fw_on_ctlr_srl;
832 ctlr->working_branch = fw_on_ctlr_branch;
833 ctlr->working_build = fw_on_ctlr_build;
834 }
835 } else {
836 /*
837 * No, we can't. See if we can at least work with

--- 4 unchanged lines hidden (view full) ---

842 TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
843 0x1010, 0x2, TW_CL_SEVERITY_WARNING_STRING,
844 "Driver/Firmware mismatch. "
845 "Negotiating for base level...",
846 " ");
847 if ((error = tw_cli_init_connection(ctlr,
848 (TW_UINT16)(ctlr->max_simult_reqs),
849 TWA_EXTENDED_INIT_CONNECT,
960 } else {
961 ctlr->working_srl = fw_on_ctlr_srl;
962 ctlr->working_branch = fw_on_ctlr_branch;
963 ctlr->working_build = fw_on_ctlr_build;
964 }
965 } else {
966 /*
967 * No, we can't. See if we can at least work with

--- 4 unchanged lines hidden (view full) ---

972 TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
973 0x1010, 0x2, TW_CL_SEVERITY_WARNING_STRING,
974 "Driver/Firmware mismatch. "
975 "Negotiating for base level...",
976 " ");
977 if ((error = tw_cli_init_connection(ctlr,
978 (TW_UINT16)(ctlr->max_simult_reqs),
979 TWA_EXTENDED_INIT_CONNECT,
850 TWA_BASE_FW_SRL, TWA_9000_ARCH_ID,
980 TWA_BASE_FW_SRL,
981 (TW_UINT16)(ctlr->arch_id),
851 TWA_BASE_FW_BRANCH, TWA_BASE_FW_BUILD,
852 &fw_on_ctlr_srl, &fw_on_ctlr_arch_id,
853 &fw_on_ctlr_branch, &fw_on_ctlr_build,
854 &init_connect_result))) {
855 tw_cl_create_event(ctlr->ctlr_handle,
856 TW_CL_FALSE,
857 TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
858 0x1011, 0x1,

--- 37 unchanged lines hidden (view full) ---

896 * We can work with this firmware, but only in
897 * base mode.
898 */
899 ctlr->working_srl = TWA_BASE_FW_SRL;
900 ctlr->working_branch = TWA_BASE_FW_BRANCH;
901 ctlr->working_build = TWA_BASE_FW_BUILD;
902 ctlr->operating_mode = TWA_BASE_MODE;
903 }
982 TWA_BASE_FW_BRANCH, TWA_BASE_FW_BUILD,
983 &fw_on_ctlr_srl, &fw_on_ctlr_arch_id,
984 &fw_on_ctlr_branch, &fw_on_ctlr_build,
985 &init_connect_result))) {
986 tw_cl_create_event(ctlr->ctlr_handle,
987 TW_CL_FALSE,
988 TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR,
989 0x1011, 0x1,

--- 37 unchanged lines hidden (view full) ---

1027 * We can work with this firmware, but only in
1028 * base mode.
1029 */
1030 ctlr->working_srl = TWA_BASE_FW_SRL;
1031 ctlr->working_branch = TWA_BASE_FW_BRANCH;
1032 ctlr->working_build = TWA_BASE_FW_BUILD;
1033 ctlr->operating_mode = TWA_BASE_MODE;
1034 }
1035 ctlr->fw_on_ctlr_srl = fw_on_ctlr_srl;
1036 ctlr->fw_on_ctlr_branch = fw_on_ctlr_branch;
1037 ctlr->fw_on_ctlr_build = fw_on_ctlr_build;
904 }
905
906 /* Drain the AEN queue */
907 if ((error = tw_cli_drain_aen_queue(ctlr)))
908 /*
909 * We will just print that we couldn't drain the AEN queue.
910 * There's no need to bail out.
911 */

--- 193 unchanged lines hidden --- 		1038 }
1039
1040 /* Drain the AEN queue */
1041 if ((error = tw_cli_drain_aen_queue(ctlr)))
1042 /*
1043 * We will just print that we couldn't drain the AEN queue.
1044 * There's no need to bail out.
1045 */

--- 193 unchanged lines hidden ---