| tw_cl.h (144966) | tw_cl.h (152213) |
|---|---|
| 1/* 2 * Copyright (c) 2004-05 Applied Micro Circuits Corporation. 3 * Copyright (c) 2004-05 Vinod Kashyap 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 10 unchanged lines hidden (view full) --- 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * | 1/* 2 * Copyright (c) 2004-05 Applied Micro Circuits Corporation. 3 * Copyright (c) 2004-05 Vinod Kashyap 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 10 unchanged lines hidden (view full) --- 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * |
| 27 * $FreeBSD: head/sys/dev/twa/tw_cl.h 144966 2005-04-12 22:07:11Z vkashyap $ | 27 * $FreeBSD: head/sys/dev/twa/tw_cl.h 152213 2005-11-08 22:51:43Z vkashyap $ |
| 28 */ 29 30/* 31 * AMCC'S 3ware driver for 9000 series storage controllers. 32 * 33 * Author: Vinod Kashyap 34 */ 35 --- 25 unchanged lines hidden (view full) --- 61/* Interrupts on controller enabled. */ 62#define TW_CLI_CTLR_STATE_INTR_ENABLED (1<<1) 63/* Data buffer for internal requests in use. */ 64#define TW_CLI_CTLR_STATE_INTERNAL_REQ_BUSY (1<<2) 65/* More AEN's need to be retrieved. */ 66#define TW_CLI_CTLR_STATE_GET_MORE_AENS (1<<3) 67/* Controller is being reset. */ 68#define TW_CLI_CTLR_STATE_RESET_IN_PROGRESS (1<<4) | 28 */ 29 30/* 31 * AMCC'S 3ware driver for 9000 series storage controllers. 32 * 33 * Author: Vinod Kashyap 34 */ 35 --- 25 unchanged lines hidden (view full) --- 61/* Interrupts on controller enabled. */ 62#define TW_CLI_CTLR_STATE_INTR_ENABLED (1<<1) 63/* Data buffer for internal requests in use. */ 64#define TW_CLI_CTLR_STATE_INTERNAL_REQ_BUSY (1<<2) 65/* More AEN's need to be retrieved. */ 66#define TW_CLI_CTLR_STATE_GET_MORE_AENS (1<<3) 67/* Controller is being reset. */ 68#define TW_CLI_CTLR_STATE_RESET_IN_PROGRESS (1<<4) |
| 69/* G133 controller is in 'phase 1' of being reset. */ 70#define TW_CLI_CTLR_STATE_RESET_PHASE1_IN_PROGRESS (1<<5) 71/* G66 register write access bug needs to be worked around. */ 72#define TW_CLI_CTLR_STATE_G66_WORKAROUND_NEEDED (1<<6) |
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| 69 70/* Possible values of ctlr->ioctl_lock.lock. */ 71#define TW_CLI_LOCK_FREE 0x0 /* lock is free */ 72#define TW_CLI_LOCK_HELD 0x1 /* lock is held */ 73 74/* Possible values of req->state. */ 75#define TW_CLI_REQ_STATE_INIT 0x0 /* being initialized */ 76#define TW_CLI_REQ_STATE_BUSY 0x1 /* submitted to controller */ --- 75 unchanged lines hidden (view full) --- 152 TW_UINT32 num_free_req_ids; 153 154#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */ 155 156 struct tw_cl_command_packet *cmd_pkt_buf;/* ptr to array of cmd pkts */ 157 158 TW_UINT64 cmd_pkt_phys; /* phys addr of cmd_pkt_buf */ 159 | 73 74/* Possible values of ctlr->ioctl_lock.lock. */ 75#define TW_CLI_LOCK_FREE 0x0 /* lock is free */ 76#define TW_CLI_LOCK_HELD 0x1 /* lock is held */ 77 78/* Possible values of req->state. */ 79#define TW_CLI_REQ_STATE_INIT 0x0 /* being initialized */ 80#define TW_CLI_REQ_STATE_BUSY 0x1 /* submitted to controller */ --- 75 unchanged lines hidden (view full) --- 156 TW_UINT32 num_free_req_ids; 157 158#endif /* TW_OSL_DMA_MEM_ALLOC_PER_REQUEST */ 159 160 struct tw_cl_command_packet *cmd_pkt_buf;/* ptr to array of cmd pkts */ 161 162 TW_UINT64 cmd_pkt_phys; /* phys addr of cmd_pkt_buf */ 163 |
| 164 TW_UINT32 device_id; /* controller device id */ 165 TW_UINT32 arch_id; /* controller architecture id */ |
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| 160 TW_UINT32 state; /* controller state */ 161 TW_UINT32 flags; /* controller settings */ | 166 TW_UINT32 state; /* controller state */ 167 TW_UINT32 flags; /* controller settings */ |
| 168 TW_UINT32 sg_size_factor; /* SG element size should be a 169 multiple of this */ |
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| 162 163 /* Request queues and arrays. */ 164 struct tw_cl_link req_q_head[TW_CLI_Q_COUNT]; 165 166#ifdef TW_OSL_FLASH_FIRMWARE 167 TW_VOID *flash_dma_mem; /* mem for flashing fw image */ 168 TW_UINT64 flash_dma_mem_phys;/* flash_dma_mem phys addr */ 169#endif /* TW_OSL_FLASH_FIRMWARE */ --- 16 unchanged lines hidden (view full) --- 186 wrapped */ 187 188 TW_UINT16 working_srl; /* driver & firmware negotiated 189 srl */ 190 TW_UINT16 working_branch; /* branch # of the firmware 191 that the driver is compatible with */ 192 TW_UINT16 working_build; /* build # of the firmware 193 that the driver is compatible with */ | 170 171 /* Request queues and arrays. */ 172 struct tw_cl_link req_q_head[TW_CLI_Q_COUNT]; 173 174#ifdef TW_OSL_FLASH_FIRMWARE 175 TW_VOID *flash_dma_mem; /* mem for flashing fw image */ 176 TW_UINT64 flash_dma_mem_phys;/* flash_dma_mem phys addr */ 177#endif /* TW_OSL_FLASH_FIRMWARE */ --- 16 unchanged lines hidden (view full) --- 194 wrapped */ 195 196 TW_UINT16 working_srl; /* driver & firmware negotiated 197 srl */ 198 TW_UINT16 working_branch; /* branch # of the firmware 199 that the driver is compatible with */ 200 TW_UINT16 working_build; /* build # of the firmware 201 that the driver is compatible with */ |
| 202 TW_UINT16 fw_on_ctlr_srl; /* srl of running firmware */ 203 TW_UINT16 fw_on_ctlr_branch;/* branch # of running 204 firmware */ 205 TW_UINT16 fw_on_ctlr_build;/* build # of running 206 firmware */ |
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| 194 TW_UINT32 operating_mode; /* base mode/current mode */ 195 196 TW_INT32 host_intr_pending;/* host intr processing 197 needed */ 198 TW_INT32 attn_intr_pending;/* attn intr processing 199 needed */ 200 TW_INT32 cmd_intr_pending;/* cmd intr processing 201 needed */ --- 102 unchanged lines hidden (view full) --- 304 305#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST 306 if ((q_type == TW_CLI_BUSY_Q) || (q_type == TW_CLI_COMPLETE_Q) || 307 ((q_type == TW_CLI_PENDING_Q) && 308 (!(req->flags & TW_CLI_REQ_FLAGS_INTERNAL)))) 309 return; 310 if ((q_type == TW_CLI_FREE_Q) && 311 (!(req->flags & TW_CLI_REQ_FLAGS_INTERNAL))) { | 207 TW_UINT32 operating_mode; /* base mode/current mode */ 208 209 TW_INT32 host_intr_pending;/* host intr processing 210 needed */ 211 TW_INT32 attn_intr_pending;/* attn intr processing 212 needed */ 213 TW_INT32 cmd_intr_pending;/* cmd intr processing 214 needed */ --- 102 unchanged lines hidden (view full) --- 317 318#ifdef TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST 319 if ((q_type == TW_CLI_BUSY_Q) || (q_type == TW_CLI_COMPLETE_Q) || 320 ((q_type == TW_CLI_PENDING_Q) && 321 (!(req->flags & TW_CLI_REQ_FLAGS_INTERNAL)))) 322 return; 323 if ((q_type == TW_CLI_FREE_Q) && 324 (!(req->flags & TW_CLI_REQ_FLAGS_INTERNAL))) { |
| 325 TW_SYNC_HANDLE sync_handle; 326 327 tw_osl_get_lock(ctlr->ctlr_handle, ctlr->gen_lock); 328 if (req->state == TW_CLI_REQ_STATE_COMPLETE) { 329 if (ctlr->flags & TW_CL_DEFERRED_INTR_USED) 330 tw_osl_sync_io_block(ctlr->ctlr_handle, 331 &sync_handle); 332 } else { 333 if (!(ctlr->flags & TW_CL_DEFERRED_INTR_USED)) 334 tw_osl_sync_isr_block(ctlr->ctlr_handle, 335 &sync_handle); 336 } |
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| 312 ctlr->free_req_ids[ctlr->free_req_tail] = req->request_id; 313 ctlr->busy_reqs[req->request_id] = TW_CL_NULL; 314 ctlr->free_req_tail = (ctlr->free_req_tail + 1) % 315 (ctlr->max_simult_reqs - 1); 316 ctlr->num_free_req_ids++; | 337 ctlr->free_req_ids[ctlr->free_req_tail] = req->request_id; 338 ctlr->busy_reqs[req->request_id] = TW_CL_NULL; 339 ctlr->free_req_tail = (ctlr->free_req_tail + 1) % 340 (ctlr->max_simult_reqs - 1); 341 ctlr->num_free_req_ids++; |
| 342 343 if (req->state == TW_CLI_REQ_STATE_COMPLETE) { 344 if (ctlr->flags & TW_CL_DEFERRED_INTR_USED) 345 tw_osl_sync_io_unblock(ctlr->ctlr_handle, 346 &sync_handle); 347 } else { 348 if (!(ctlr->flags & TW_CL_DEFERRED_INTR_USED)) 349 tw_osl_sync_isr_unblock(ctlr->ctlr_handle, 350 &sync_handle); 351 } 352 tw_osl_free_lock(ctlr->ctlr_handle, ctlr->gen_lock); |
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| 317 return; 318 } 319#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */ 320 321 tw_osl_get_lock(ctlr->ctlr_handle, ctlr->gen_lock); 322 TW_CL_Q_INSERT_TAIL(&(ctlr->req_q_head[q_type]), &(req->link)); 323 TW_CLI_Q_INSERT(ctlr, q_type); 324 tw_osl_free_lock(ctlr->ctlr_handle, ctlr->gen_lock); --- 82 unchanged lines hidden --- | 353 return; 354 } 355#endif /* TW_OSL_NON_DMA_MEM_ALLOC_PER_REQUEST */ 356 357 tw_osl_get_lock(ctlr->ctlr_handle, ctlr->gen_lock); 358 TW_CL_Q_INSERT_TAIL(&(ctlr->req_q_head[q_type]), &(req->link)); 359 TW_CLI_Q_INSERT(ctlr, q_type); 360 tw_osl_free_lock(ctlr->ctlr_handle, ctlr->gen_lock); --- 82 unchanged lines hidden --- |