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if_tsec.c (209908) if_tsec.c (213893)
1/*-
2 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski
3 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27/*
28 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver.
29 */
30#include <sys/cdefs.h>
1/*-
2 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski
3 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27/*
28 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver.
29 */
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/tsec/if_tsec.c 209908 2010-07-11 21:08:29Z raj $");
31__FBSDID("$FreeBSD: head/sys/dev/tsec/if_tsec.c 213893 2010-10-15 14:52:11Z marius $");
32
33#ifdef HAVE_KERNEL_OPTION_HEADERS
34#include "opt_device_polling.h"
35#endif
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/bus.h>

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263
264 ifp->if_capenable = ifp->if_capabilities;
265
266#ifdef DEVICE_POLLING
267 /* Advertise that polling is supported */
268 ifp->if_capabilities |= IFCAP_POLLING;
269#endif
270
32
33#ifdef HAVE_KERNEL_OPTION_HEADERS
34#include "opt_device_polling.h"
35#endif
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/bus.h>

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263
264 ifp->if_capenable = ifp->if_capabilities;
265
266#ifdef DEVICE_POLLING
267 /* Advertise that polling is supported */
268 ifp->if_capabilities |= IFCAP_POLLING;
269#endif
270
271 /* Probe PHY(s) */
272 error = mii_phy_probe(sc->dev, &sc->tsec_miibus, tsec_ifmedia_upd,
273 tsec_ifmedia_sts);
271 /* Attach PHY(s) */
272 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd,
273 tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY,
274 0);
274 if (error) {
275 if (error) {
275 device_printf(sc->dev, "MII failed to find PHY!\n");
276 device_printf(sc->dev, "attaching PHYs failed\n");
276 if_free(ifp);
277 sc->tsec_ifp = NULL;
278 tsec_detach(sc);
279 return (error);
280 }
281 sc->tsec_mii = device_get_softc(sc->tsec_miibus);
282
283 /* Set MAC address */

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1556}
1557
1558int
1559tsec_miibus_readreg(device_t dev, int phy, int reg)
1560{
1561 struct tsec_softc *sc;
1562 uint32_t timeout;
1563
277 if_free(ifp);
278 sc->tsec_ifp = NULL;
279 tsec_detach(sc);
280 return (error);
281 }
282 sc->tsec_mii = device_get_softc(sc->tsec_miibus);
283
284 /* Set MAC address */

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1557}
1558
1559int
1560tsec_miibus_readreg(device_t dev, int phy, int reg)
1561{
1562 struct tsec_softc *sc;
1563 uint32_t timeout;
1564
1564 sc = device_get_softc(dev);
1565
1566 if (sc->phyaddr != phy)
1567 return (0);
1568
1569 sc = tsec0_sc;
1570
1571 TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1572 TSEC_WRITE(sc, TSEC_REG_MIIMCOM, 0);
1573 TSEC_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE);
1574
1575 timeout = TSEC_READ_RETRY;
1576 while (--timeout && TSEC_READ(sc, TSEC_REG_MIIMIND) &

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1584}
1585
1586int
1587tsec_miibus_writereg(device_t dev, int phy, int reg, int value)
1588{
1589 struct tsec_softc *sc;
1590 uint32_t timeout;
1591
1565 sc = tsec0_sc;
1566
1567 TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1568 TSEC_WRITE(sc, TSEC_REG_MIIMCOM, 0);
1569 TSEC_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE);
1570
1571 timeout = TSEC_READ_RETRY;
1572 while (--timeout && TSEC_READ(sc, TSEC_REG_MIIMIND) &

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1580}
1581
1582int
1583tsec_miibus_writereg(device_t dev, int phy, int reg, int value)
1584{
1585 struct tsec_softc *sc;
1586 uint32_t timeout;
1587
1592 sc = device_get_softc(dev);
1593
1594 if (sc->phyaddr != phy)
1595 return (0);
1596
1597 sc = tsec0_sc;
1598
1599 TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1600 TSEC_WRITE(sc, TSEC_REG_MIIMCON, value);
1601
1602 timeout = TSEC_READ_RETRY;
1603 while (--timeout && (TSEC_READ(sc, TSEC_REG_MIIMIND) &
1604 TSEC_MIIMIND_BUSY))

--- 328 unchanged lines hidden --- 		1588 sc = tsec0_sc;
1589
1590 TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1591 TSEC_WRITE(sc, TSEC_REG_MIIMCON, value);
1592
1593 timeout = TSEC_READ_RETRY;
1594 while (--timeout && (TSEC_READ(sc, TSEC_REG_MIIMIND) &
1595 TSEC_MIIMIND_BUSY))

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