1/*-
2 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski
3 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27/*
28 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver.
29 */
30#include <sys/cdefs.h>
| 1/*-
2 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski
3 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27/*
28 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver.
29 */
30#include <sys/cdefs.h>
|
31__FBSDID("$FreeBSD: head/sys/dev/tsec/if_tsec.c 229767 2012-01-07 09:41:57Z kevlo $");
| 31__FBSDID("$FreeBSD: head/sys/dev/tsec/if_tsec.c 232518 2012-03-04 19:22:52Z raj $");
|
32
33#ifdef HAVE_KERNEL_OPTION_HEADERS
34#include "opt_device_polling.h"
35#endif
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/bus.h>
40#include <sys/endian.h>
41#include <sys/mbuf.h>
42#include <sys/kernel.h>
43#include <sys/module.h>
44#include <sys/socket.h>
45#include <sys/sockio.h>
46#include <sys/sysctl.h>
47
48#include <net/bpf.h>
49#include <net/ethernet.h>
50#include <net/if.h>
51#include <net/if_arp.h>
52#include <net/if_dl.h>
53#include <net/if_media.h>
54#include <net/if_types.h>
55#include <net/if_vlan_var.h>
56
57#include <netinet/in_systm.h>
58#include <netinet/in.h>
59#include <netinet/ip.h>
60
61#include <machine/bus.h>
62
63#include <dev/mii/mii.h>
64#include <dev/mii/miivar.h>
65
66#include <dev/tsec/if_tsec.h>
67#include <dev/tsec/if_tsecreg.h>
68
69static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag,
70 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr,
71 const char *dname);
72static void tsec_dma_ctl(struct tsec_softc *sc, int state);
73static int tsec_encap(struct tsec_softc *sc, struct mbuf *m_head,
74 int fcb_inserted);
75static void tsec_free_dma(struct tsec_softc *sc);
76static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr);
77static int tsec_ifmedia_upd(struct ifnet *ifp);
78static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
79static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map,
80 struct mbuf **mbufp, uint32_t *paddr);
81static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs,
82 int nseg, int error);
83static void tsec_intrs_ctl(struct tsec_softc *sc, int state);
84static void tsec_init(void *xsc);
85static void tsec_init_locked(struct tsec_softc *sc);
86static int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
87static void tsec_reset_mac(struct tsec_softc *sc);
88static void tsec_setfilter(struct tsec_softc *sc);
89static void tsec_set_mac_address(struct tsec_softc *sc);
90static void tsec_start(struct ifnet *ifp);
91static void tsec_start_locked(struct ifnet *ifp);
92static void tsec_stop(struct tsec_softc *sc);
93static void tsec_tick(void *arg);
94static void tsec_watchdog(struct tsec_softc *sc);
95static void tsec_add_sysctls(struct tsec_softc *sc);
96static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS);
97static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS);
98static void tsec_set_rxic(struct tsec_softc *sc);
99static void tsec_set_txic(struct tsec_softc *sc);
100static int tsec_receive_intr_locked(struct tsec_softc *sc, int count);
101static void tsec_transmit_intr_locked(struct tsec_softc *sc);
102static void tsec_error_intr_locked(struct tsec_softc *sc, int count);
103static void tsec_offload_setup(struct tsec_softc *sc);
104static void tsec_offload_process_frame(struct tsec_softc *sc,
105 struct mbuf *m);
106static void tsec_setup_multicast(struct tsec_softc *sc);
107static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu);
108
| 32
33#ifdef HAVE_KERNEL_OPTION_HEADERS
34#include "opt_device_polling.h"
35#endif
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/bus.h>
40#include <sys/endian.h>
41#include <sys/mbuf.h>
42#include <sys/kernel.h>
43#include <sys/module.h>
44#include <sys/socket.h>
45#include <sys/sockio.h>
46#include <sys/sysctl.h>
47
48#include <net/bpf.h>
49#include <net/ethernet.h>
50#include <net/if.h>
51#include <net/if_arp.h>
52#include <net/if_dl.h>
53#include <net/if_media.h>
54#include <net/if_types.h>
55#include <net/if_vlan_var.h>
56
57#include <netinet/in_systm.h>
58#include <netinet/in.h>
59#include <netinet/ip.h>
60
61#include <machine/bus.h>
62
63#include <dev/mii/mii.h>
64#include <dev/mii/miivar.h>
65
66#include <dev/tsec/if_tsec.h>
67#include <dev/tsec/if_tsecreg.h>
68
69static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag,
70 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr,
71 const char *dname);
72static void tsec_dma_ctl(struct tsec_softc *sc, int state);
73static int tsec_encap(struct tsec_softc *sc, struct mbuf *m_head,
74 int fcb_inserted);
75static void tsec_free_dma(struct tsec_softc *sc);
76static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr);
77static int tsec_ifmedia_upd(struct ifnet *ifp);
78static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
79static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map,
80 struct mbuf **mbufp, uint32_t *paddr);
81static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs,
82 int nseg, int error);
83static void tsec_intrs_ctl(struct tsec_softc *sc, int state);
84static void tsec_init(void *xsc);
85static void tsec_init_locked(struct tsec_softc *sc);
86static int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
87static void tsec_reset_mac(struct tsec_softc *sc);
88static void tsec_setfilter(struct tsec_softc *sc);
89static void tsec_set_mac_address(struct tsec_softc *sc);
90static void tsec_start(struct ifnet *ifp);
91static void tsec_start_locked(struct ifnet *ifp);
92static void tsec_stop(struct tsec_softc *sc);
93static void tsec_tick(void *arg);
94static void tsec_watchdog(struct tsec_softc *sc);
95static void tsec_add_sysctls(struct tsec_softc *sc);
96static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS);
97static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS);
98static void tsec_set_rxic(struct tsec_softc *sc);
99static void tsec_set_txic(struct tsec_softc *sc);
100static int tsec_receive_intr_locked(struct tsec_softc *sc, int count);
101static void tsec_transmit_intr_locked(struct tsec_softc *sc);
102static void tsec_error_intr_locked(struct tsec_softc *sc, int count);
103static void tsec_offload_setup(struct tsec_softc *sc);
104static void tsec_offload_process_frame(struct tsec_softc *sc,
105 struct mbuf *m);
106static void tsec_setup_multicast(struct tsec_softc *sc);
107static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu);
108
|
109struct tsec_softc *tsec0_sc = NULL; /* XXX ugly hack! */
110
| |
111devclass_t tsec_devclass;
112DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0);
113MODULE_DEPEND(tsec, ether, 1, 1, 1);
114MODULE_DEPEND(tsec, miibus, 1, 1, 1);
115
116int
117tsec_attach(struct tsec_softc *sc)
118{
119 uint8_t hwaddr[ETHER_ADDR_LEN];
120 struct ifnet *ifp;
121 bus_dmamap_t *map_ptr;
122 bus_dmamap_t **map_pptr;
123 int error = 0;
124 int i;
125
126 /* Reset all TSEC counters */
127 TSEC_TX_RX_COUNTERS_INIT(sc);
128
129 /* Stop DMA engine if enabled by firmware */
130 tsec_dma_ctl(sc, 0);
131
132 /* Reset MAC */
133 tsec_reset_mac(sc);
134
135 /* Disable interrupts for now */
136 tsec_intrs_ctl(sc, 0);
137
138 /* Configure defaults for interrupts coalescing */
139 sc->rx_ic_time = 768;
140 sc->rx_ic_count = 16;
141 sc->tx_ic_time = 768;
142 sc->tx_ic_count = 16;
143 tsec_set_rxic(sc);
144 tsec_set_txic(sc);
145 tsec_add_sysctls(sc);
146
147 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */
148 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag,
149 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC,
150 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX");
151
152 if (error) {
153 tsec_detach(sc);
154 return (ENXIO);
155 }
156
157 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */
158 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag,
159 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC,
160 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX");
161 if (error) {
162 tsec_detach(sc);
163 return (ENXIO);
164 }
165
166 /* Allocate a busdma tag for TX mbufs. */
167 error = bus_dma_tag_create(NULL, /* parent */
168 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
169 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
170 BUS_SPACE_MAXADDR, /* highaddr */
171 NULL, NULL, /* filtfunc, filtfuncarg */
172 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */
173 TSEC_TX_NUM_DESC - 1, /* nsegments */
174 MCLBYTES, 0, /* maxsegsz, flags */
175 NULL, NULL, /* lockfunc, lockfuncarg */
176 &sc->tsec_tx_mtag); /* dmat */
177 if (error) {
178 device_printf(sc->dev, "failed to allocate busdma tag "
179 "(tx mbufs)\n");
180 tsec_detach(sc);
181 return (ENXIO);
182 }
183
184 /* Allocate a busdma tag for RX mbufs. */
185 error = bus_dma_tag_create(NULL, /* parent */
186 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
187 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
188 BUS_SPACE_MAXADDR, /* highaddr */
189 NULL, NULL, /* filtfunc, filtfuncarg */
190 MCLBYTES, /* maxsize */
191 1, /* nsegments */
192 MCLBYTES, 0, /* maxsegsz, flags */
193 NULL, NULL, /* lockfunc, lockfuncarg */
194 &sc->tsec_rx_mtag); /* dmat */
195 if (error) {
196 device_printf(sc->dev, "failed to allocate busdma tag "
197 "(rx mbufs)\n");
198 tsec_detach(sc);
199 return (ENXIO);
200 }
201
202 /* Create TX busdma maps */
203 map_ptr = sc->tx_map_data;
204 map_pptr = sc->tx_map_unused_data;
205
206 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
207 map_pptr[i] = &map_ptr[i];
208 error = bus_dmamap_create(sc->tsec_tx_mtag, 0, map_pptr[i]);
209 if (error) {
210 device_printf(sc->dev, "failed to init TX ring\n");
211 tsec_detach(sc);
212 return (ENXIO);
213 }
214 }
215
216 /* Create RX busdma maps and zero mbuf handlers */
217 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
218 error = bus_dmamap_create(sc->tsec_rx_mtag, 0,
219 &sc->rx_data[i].map);
220 if (error) {
221 device_printf(sc->dev, "failed to init RX ring\n");
222 tsec_detach(sc);
223 return (ENXIO);
224 }
225 sc->rx_data[i].mbuf = NULL;
226 }
227
228 /* Create mbufs for RX buffers */
229 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
230 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map,
231 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr);
232 if (error) {
233 device_printf(sc->dev, "can't load rx DMA map %d, "
234 "error = %d\n", i, error);
235 tsec_detach(sc);
236 return (error);
237 }
238 }
239
240 /* Create network interface for upper layers */
241 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER);
242 if (ifp == NULL) {
243 device_printf(sc->dev, "if_alloc() failed\n");
244 tsec_detach(sc);
245 return (ENOMEM);
246 }
247
248 ifp->if_softc = sc;
249 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
250 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST;
251 ifp->if_init = tsec_init;
252 ifp->if_start = tsec_start;
253 ifp->if_ioctl = tsec_ioctl;
254
255 IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1);
256 ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1;
257 IFQ_SET_READY(&ifp->if_snd);
258
259 ifp->if_capabilities = IFCAP_VLAN_MTU;
260 if (sc->is_etsec)
261 ifp->if_capabilities |= IFCAP_HWCSUM;
262
263 ifp->if_capenable = ifp->if_capabilities;
264
265#ifdef DEVICE_POLLING
266 /* Advertise that polling is supported */
267 ifp->if_capabilities |= IFCAP_POLLING;
268#endif
269
270 /* Attach PHY(s) */
271 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd,
272 tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY,
273 0);
274 if (error) {
275 device_printf(sc->dev, "attaching PHYs failed\n");
276 if_free(ifp);
277 sc->tsec_ifp = NULL;
278 tsec_detach(sc);
279 return (error);
280 }
281 sc->tsec_mii = device_get_softc(sc->tsec_miibus);
282
283 /* Set MAC address */
284 tsec_get_hwaddr(sc, hwaddr);
285 ether_ifattach(ifp, hwaddr);
286
287 return (0);
288}
289
290int
291tsec_detach(struct tsec_softc *sc)
292{
293
294#ifdef DEVICE_POLLING
295 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING)
296 ether_poll_deregister(sc->tsec_ifp);
297#endif
298
299 /* Stop TSEC controller and free TX queue */
300 if (sc->sc_rres && sc->tsec_ifp)
301 tsec_shutdown(sc->dev);
302
303 /* Detach network interface */
304 if (sc->tsec_ifp) {
305 ether_ifdetach(sc->tsec_ifp);
306 if_free(sc->tsec_ifp);
307 sc->tsec_ifp = NULL;
308 }
309
310 /* Free DMA resources */
311 tsec_free_dma(sc);
312
313 return (0);
314}
315
316int
317tsec_shutdown(device_t dev)
318{
319 struct tsec_softc *sc;
320
321 sc = device_get_softc(dev);
322
323 TSEC_GLOBAL_LOCK(sc);
324 tsec_stop(sc);
325 TSEC_GLOBAL_UNLOCK(sc);
326 return (0);
327}
328
329int
330tsec_suspend(device_t dev)
331{
332
333 /* TODO not implemented! */
334 return (0);
335}
336
337int
338tsec_resume(device_t dev)
339{
340
341 /* TODO not implemented! */
342 return (0);
343}
344
345static void
346tsec_init(void *xsc)
347{
348 struct tsec_softc *sc = xsc;
349
350 TSEC_GLOBAL_LOCK(sc);
351 tsec_init_locked(sc);
352 TSEC_GLOBAL_UNLOCK(sc);
353}
354
355static void
356tsec_init_locked(struct tsec_softc *sc)
357{
358 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr;
359 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr;
360 struct ifnet *ifp = sc->tsec_ifp;
361 uint32_t timeout, val, i;
362
363 TSEC_GLOBAL_LOCK_ASSERT(sc);
364 tsec_stop(sc);
365
366 /*
367 * These steps are according to the MPC8555E PowerQUICCIII RM:
368 * 14.7 Initialization/Application Information
369 */
370
371 /* Step 1: soft reset MAC */
372 tsec_reset_mac(sc);
373
374 /* Step 2: Initialize MACCFG2 */
375 TSEC_WRITE(sc, TSEC_REG_MACCFG2,
376 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */
377 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */
378 TSEC_MACCFG2_GMII | /* I/F Mode bit */
379 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */
380 );
381
382 /* Step 3: Initialize ECNTRL
383 * While the documentation states that R100M is ignored if RPM is
384 * not set, it does seem to be needed to get the orange boxes to
385 * work (which have a Marvell 88E1111 PHY). Go figure.
386 */
387
388 /*
389 * XXX kludge - use circumstancial evidence to program ECNTRL
390 * correctly. Ideally we need some board information to guide
391 * us here.
392 */
393 i = TSEC_READ(sc, TSEC_REG_ID2);
394 val = (i & 0xffff)
395 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */
396 : TSEC_ECNTRL_R100M; /* Orange + CDS */
397 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val);
398
399 /* Step 4: Initialize MAC station address */
400 tsec_set_mac_address(sc);
401
402 /*
403 * Step 5: Assign a Physical address to the TBI so as to not conflict
404 * with the external PHY physical address
405 */
406 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5);
407
408 /* Step 6: Reset the management interface */
| 109devclass_t tsec_devclass;
110DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0);
111MODULE_DEPEND(tsec, ether, 1, 1, 1);
112MODULE_DEPEND(tsec, miibus, 1, 1, 1);
113
114int
115tsec_attach(struct tsec_softc *sc)
116{
117 uint8_t hwaddr[ETHER_ADDR_LEN];
118 struct ifnet *ifp;
119 bus_dmamap_t *map_ptr;
120 bus_dmamap_t **map_pptr;
121 int error = 0;
122 int i;
123
124 /* Reset all TSEC counters */
125 TSEC_TX_RX_COUNTERS_INIT(sc);
126
127 /* Stop DMA engine if enabled by firmware */
128 tsec_dma_ctl(sc, 0);
129
130 /* Reset MAC */
131 tsec_reset_mac(sc);
132
133 /* Disable interrupts for now */
134 tsec_intrs_ctl(sc, 0);
135
136 /* Configure defaults for interrupts coalescing */
137 sc->rx_ic_time = 768;
138 sc->rx_ic_count = 16;
139 sc->tx_ic_time = 768;
140 sc->tx_ic_count = 16;
141 tsec_set_rxic(sc);
142 tsec_set_txic(sc);
143 tsec_add_sysctls(sc);
144
145 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */
146 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag,
147 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC,
148 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX");
149
150 if (error) {
151 tsec_detach(sc);
152 return (ENXIO);
153 }
154
155 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */
156 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag,
157 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC,
158 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX");
159 if (error) {
160 tsec_detach(sc);
161 return (ENXIO);
162 }
163
164 /* Allocate a busdma tag for TX mbufs. */
165 error = bus_dma_tag_create(NULL, /* parent */
166 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
167 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
168 BUS_SPACE_MAXADDR, /* highaddr */
169 NULL, NULL, /* filtfunc, filtfuncarg */
170 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */
171 TSEC_TX_NUM_DESC - 1, /* nsegments */
172 MCLBYTES, 0, /* maxsegsz, flags */
173 NULL, NULL, /* lockfunc, lockfuncarg */
174 &sc->tsec_tx_mtag); /* dmat */
175 if (error) {
176 device_printf(sc->dev, "failed to allocate busdma tag "
177 "(tx mbufs)\n");
178 tsec_detach(sc);
179 return (ENXIO);
180 }
181
182 /* Allocate a busdma tag for RX mbufs. */
183 error = bus_dma_tag_create(NULL, /* parent */
184 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
185 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
186 BUS_SPACE_MAXADDR, /* highaddr */
187 NULL, NULL, /* filtfunc, filtfuncarg */
188 MCLBYTES, /* maxsize */
189 1, /* nsegments */
190 MCLBYTES, 0, /* maxsegsz, flags */
191 NULL, NULL, /* lockfunc, lockfuncarg */
192 &sc->tsec_rx_mtag); /* dmat */
193 if (error) {
194 device_printf(sc->dev, "failed to allocate busdma tag "
195 "(rx mbufs)\n");
196 tsec_detach(sc);
197 return (ENXIO);
198 }
199
200 /* Create TX busdma maps */
201 map_ptr = sc->tx_map_data;
202 map_pptr = sc->tx_map_unused_data;
203
204 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
205 map_pptr[i] = &map_ptr[i];
206 error = bus_dmamap_create(sc->tsec_tx_mtag, 0, map_pptr[i]);
207 if (error) {
208 device_printf(sc->dev, "failed to init TX ring\n");
209 tsec_detach(sc);
210 return (ENXIO);
211 }
212 }
213
214 /* Create RX busdma maps and zero mbuf handlers */
215 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
216 error = bus_dmamap_create(sc->tsec_rx_mtag, 0,
217 &sc->rx_data[i].map);
218 if (error) {
219 device_printf(sc->dev, "failed to init RX ring\n");
220 tsec_detach(sc);
221 return (ENXIO);
222 }
223 sc->rx_data[i].mbuf = NULL;
224 }
225
226 /* Create mbufs for RX buffers */
227 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
228 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map,
229 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr);
230 if (error) {
231 device_printf(sc->dev, "can't load rx DMA map %d, "
232 "error = %d\n", i, error);
233 tsec_detach(sc);
234 return (error);
235 }
236 }
237
238 /* Create network interface for upper layers */
239 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER);
240 if (ifp == NULL) {
241 device_printf(sc->dev, "if_alloc() failed\n");
242 tsec_detach(sc);
243 return (ENOMEM);
244 }
245
246 ifp->if_softc = sc;
247 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
248 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST;
249 ifp->if_init = tsec_init;
250 ifp->if_start = tsec_start;
251 ifp->if_ioctl = tsec_ioctl;
252
253 IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1);
254 ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1;
255 IFQ_SET_READY(&ifp->if_snd);
256
257 ifp->if_capabilities = IFCAP_VLAN_MTU;
258 if (sc->is_etsec)
259 ifp->if_capabilities |= IFCAP_HWCSUM;
260
261 ifp->if_capenable = ifp->if_capabilities;
262
263#ifdef DEVICE_POLLING
264 /* Advertise that polling is supported */
265 ifp->if_capabilities |= IFCAP_POLLING;
266#endif
267
268 /* Attach PHY(s) */
269 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd,
270 tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY,
271 0);
272 if (error) {
273 device_printf(sc->dev, "attaching PHYs failed\n");
274 if_free(ifp);
275 sc->tsec_ifp = NULL;
276 tsec_detach(sc);
277 return (error);
278 }
279 sc->tsec_mii = device_get_softc(sc->tsec_miibus);
280
281 /* Set MAC address */
282 tsec_get_hwaddr(sc, hwaddr);
283 ether_ifattach(ifp, hwaddr);
284
285 return (0);
286}
287
288int
289tsec_detach(struct tsec_softc *sc)
290{
291
292#ifdef DEVICE_POLLING
293 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING)
294 ether_poll_deregister(sc->tsec_ifp);
295#endif
296
297 /* Stop TSEC controller and free TX queue */
298 if (sc->sc_rres && sc->tsec_ifp)
299 tsec_shutdown(sc->dev);
300
301 /* Detach network interface */
302 if (sc->tsec_ifp) {
303 ether_ifdetach(sc->tsec_ifp);
304 if_free(sc->tsec_ifp);
305 sc->tsec_ifp = NULL;
306 }
307
308 /* Free DMA resources */
309 tsec_free_dma(sc);
310
311 return (0);
312}
313
314int
315tsec_shutdown(device_t dev)
316{
317 struct tsec_softc *sc;
318
319 sc = device_get_softc(dev);
320
321 TSEC_GLOBAL_LOCK(sc);
322 tsec_stop(sc);
323 TSEC_GLOBAL_UNLOCK(sc);
324 return (0);
325}
326
327int
328tsec_suspend(device_t dev)
329{
330
331 /* TODO not implemented! */
332 return (0);
333}
334
335int
336tsec_resume(device_t dev)
337{
338
339 /* TODO not implemented! */
340 return (0);
341}
342
343static void
344tsec_init(void *xsc)
345{
346 struct tsec_softc *sc = xsc;
347
348 TSEC_GLOBAL_LOCK(sc);
349 tsec_init_locked(sc);
350 TSEC_GLOBAL_UNLOCK(sc);
351}
352
353static void
354tsec_init_locked(struct tsec_softc *sc)
355{
356 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr;
357 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr;
358 struct ifnet *ifp = sc->tsec_ifp;
359 uint32_t timeout, val, i;
360
361 TSEC_GLOBAL_LOCK_ASSERT(sc);
362 tsec_stop(sc);
363
364 /*
365 * These steps are according to the MPC8555E PowerQUICCIII RM:
366 * 14.7 Initialization/Application Information
367 */
368
369 /* Step 1: soft reset MAC */
370 tsec_reset_mac(sc);
371
372 /* Step 2: Initialize MACCFG2 */
373 TSEC_WRITE(sc, TSEC_REG_MACCFG2,
374 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */
375 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */
376 TSEC_MACCFG2_GMII | /* I/F Mode bit */
377 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */
378 );
379
380 /* Step 3: Initialize ECNTRL
381 * While the documentation states that R100M is ignored if RPM is
382 * not set, it does seem to be needed to get the orange boxes to
383 * work (which have a Marvell 88E1111 PHY). Go figure.
384 */
385
386 /*
387 * XXX kludge - use circumstancial evidence to program ECNTRL
388 * correctly. Ideally we need some board information to guide
389 * us here.
390 */
391 i = TSEC_READ(sc, TSEC_REG_ID2);
392 val = (i & 0xffff)
393 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */
394 : TSEC_ECNTRL_R100M; /* Orange + CDS */
395 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val);
396
397 /* Step 4: Initialize MAC station address */
398 tsec_set_mac_address(sc);
399
400 /*
401 * Step 5: Assign a Physical address to the TBI so as to not conflict
402 * with the external PHY physical address
403 */
404 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5);
405
406 /* Step 6: Reset the management interface */
|
409 TSEC_WRITE(tsec0_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT);
| 407 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT);
|
410
411 /* Step 7: Setup the MII Mgmt clock speed */
| 408
409 /* Step 7: Setup the MII Mgmt clock speed */
|
412 TSEC_WRITE(tsec0_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28);
| 410 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28);
|
413
414 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */
415 timeout = TSEC_READ_RETRY;
| 411
412 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */
413 timeout = TSEC_READ_RETRY;
|
416 while (--timeout && (TSEC_READ(tsec0_sc, TSEC_REG_MIIMIND) &
| 414 while (--timeout && (TSEC_READ(sc->phy_sc, TSEC_REG_MIIMIND) &
|
417 TSEC_MIIMIND_BUSY))
418 DELAY(TSEC_READ_DELAY);
419 if (timeout == 0) {
420 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n");
421 return;
422 }
423
424 /* Step 9: Setup the MII Mgmt */
425 mii_mediachg(sc->tsec_mii);
426
427 /* Step 10: Clear IEVENT register */
428 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff);
429
430 /* Step 11: Enable interrupts */
431#ifdef DEVICE_POLLING
432 /*
433 * ...only if polling is not turned on. Disable interrupts explicitly
434 * if polling is enabled.
435 */
436 if (ifp->if_capenable & IFCAP_POLLING )
437 tsec_intrs_ctl(sc, 0);
438 else
439#endif /* DEVICE_POLLING */
440 tsec_intrs_ctl(sc, 1);
441
442 /* Step 12: Initialize IADDRn */
443 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0);
444 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0);
445 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0);
446 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0);
447 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0);
448 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0);
449 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0);
450 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0);
451
452 /* Step 13: Initialize GADDRn */
453 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0);
454 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0);
455 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0);
456 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0);
457 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0);
458 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0);
459 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0);
460 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0);
461
462 /* Step 14: Initialize RCTRL */
463 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0);
464
465 /* Step 15: Initialize DMACTRL */
466 tsec_dma_ctl(sc, 1);
467
468 /* Step 16: Initialize FIFO_PAUSE_CTRL */
469 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN);
470
471 /*
472 * Step 17: Initialize transmit/receive descriptor rings.
473 * Initialize TBASE and RBASE.
474 */
475 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr);
476 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr);
477
478 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
479 tx_desc[i].bufptr = 0;
480 tx_desc[i].length = 0;
481 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ?
482 TSEC_TXBD_W : 0);
483 }
484 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
485 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
486
487 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
488 rx_desc[i].bufptr = sc->rx_data[i].paddr;
489 rx_desc[i].length = 0;
490 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I |
491 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0);
492 }
493 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
494 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
495
496 /* Step 18: Initialize the maximum receive buffer length */
497 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES);
498
499 /* Step 19: Configure ethernet frame sizes */
500 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE);
501 tsec_set_mtu(sc, ifp->if_mtu);
502
503 /* Step 20: Enable Rx and RxBD sdata snooping */
504 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN);
505 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0);
506
507 /* Step 21: Reset collision counters in hardware */
508 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
509 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
510 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
511 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
512 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
513
514 /* Step 22: Mask all CAM interrupts */
515 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff);
516 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff);
517
518 /* Step 23: Enable Rx and Tx */
519 val = TSEC_READ(sc, TSEC_REG_MACCFG1);
520 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
521 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val);
522
523 /* Step 24: Reset TSEC counters for Tx and Rx rings */
524 TSEC_TX_RX_COUNTERS_INIT(sc);
525
526 /* Step 25: Setup TCP/IP Off-Load engine */
527 if (sc->is_etsec)
528 tsec_offload_setup(sc);
529
530 /* Step 26: Setup multicast filters */
531 tsec_setup_multicast(sc);
532
533 /* Step 27: Activate network interface */
534 ifp->if_drv_flags |= IFF_DRV_RUNNING;
535 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
536 sc->tsec_if_flags = ifp->if_flags;
537 sc->tsec_watchdog = 0;
538
539 /* Schedule watchdog timeout */
540 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
541}
542
543static void
544tsec_set_mac_address(struct tsec_softc *sc)
545{
546 uint32_t macbuf[2] = { 0, 0 };
547 char *macbufp, *curmac;
548 int i;
549
550 TSEC_GLOBAL_LOCK_ASSERT(sc);
551
552 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)),
553 ("tsec_set_mac_address: (%d <= %d", ETHER_ADDR_LEN,
554 sizeof(macbuf)));
555
556 macbufp = (char *)macbuf;
557 curmac = (char *)IF_LLADDR(sc->tsec_ifp);
558
559 /* Correct order of MAC address bytes */
560 for (i = 1; i <= ETHER_ADDR_LEN; i++)
561 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1];
562
563 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */
564 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]);
565 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]);
566}
567
568/*
569 * DMA control function, if argument state is:
570 * 0 - DMA engine will be disabled
571 * 1 - DMA engine will be enabled
572 */
573static void
574tsec_dma_ctl(struct tsec_softc *sc, int state)
575{
576 device_t dev;
577 uint32_t dma_flags, timeout;
578
579 dev = sc->dev;
580
581 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL);
582
583 switch (state) {
584 case 0:
585 /* Temporarily clear stop graceful stop bits. */
586 tsec_dma_ctl(sc, 1000);
587
588 /* Set it again */
589 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
590 break;
591 case 1000:
592 case 1:
593 /* Set write with response (WWR), wait (WOP) and snoop bits */
594 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN |
595 DMACTRL_WWR | DMACTRL_WOP);
596
597 /* Clear graceful stop bits */
598 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
599 break;
600 default:
601 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n",
602 state);
603 }
604
605 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags);
606
607 switch (state) {
608 case 0:
609 /* Wait for DMA stop */
610 timeout = TSEC_READ_RETRY;
611 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) &
612 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC))))
613 DELAY(TSEC_READ_DELAY);
614
615 if (timeout == 0)
616 device_printf(dev, "tsec_dma_ctl(): timeout!\n");
617 break;
618 case 1:
619 /* Restart transmission function */
620 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
621 }
622}
623
624/*
625 * Interrupts control function, if argument state is:
626 * 0 - all TSEC interrupts will be masked
627 * 1 - all TSEC interrupts will be unmasked
628 */
629static void
630tsec_intrs_ctl(struct tsec_softc *sc, int state)
631{
632 device_t dev;
633
634 dev = sc->dev;
635
636 switch (state) {
637 case 0:
638 TSEC_WRITE(sc, TSEC_REG_IMASK, 0);
639 break;
640 case 1:
641 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN |
642 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN |
643 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN |
644 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN);
645 break;
646 default:
647 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n",
648 state);
649 }
650}
651
652static void
653tsec_reset_mac(struct tsec_softc *sc)
654{
655 uint32_t maccfg1_flags;
656
657 /* Set soft reset bit */
658 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
659 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET;
660 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
661
662 /* Clear soft reset bit */
663 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
664 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET;
665 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
666}
667
668static void
669tsec_watchdog(struct tsec_softc *sc)
670{
671 struct ifnet *ifp;
672
673 TSEC_GLOBAL_LOCK_ASSERT(sc);
674
675 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0)
676 return;
677
678 ifp = sc->tsec_ifp;
679 ifp->if_oerrors++;
680 if_printf(ifp, "watchdog timeout\n");
681
682 tsec_stop(sc);
683 tsec_init_locked(sc);
684}
685
686static void
687tsec_start(struct ifnet *ifp)
688{
689 struct tsec_softc *sc = ifp->if_softc;
690
691 TSEC_TRANSMIT_LOCK(sc);
692 tsec_start_locked(ifp);
693 TSEC_TRANSMIT_UNLOCK(sc);
694}
695
696static void
697tsec_start_locked(struct ifnet *ifp)
698{
699 struct tsec_softc *sc;
700 struct mbuf *m0, *mtmp;
701 struct tsec_tx_fcb *tx_fcb;
702 unsigned int queued = 0;
703 int csum_flags, fcb_inserted = 0;
704
705 sc = ifp->if_softc;
706
707 TSEC_TRANSMIT_LOCK_ASSERT(sc);
708
709 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
710 IFF_DRV_RUNNING)
711 return;
712
713 if (sc->tsec_link == 0)
714 return;
715
716 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
717 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
718
719 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
720 /* Get packet from the queue */
721 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
722 if (m0 == NULL)
723 break;
724
725 /* Insert TCP/IP Off-load frame control block */
726 csum_flags = m0->m_pkthdr.csum_flags;
727 if (csum_flags) {
728
729 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_DONTWAIT);
730 if (m0 == NULL)
731 break;
732
733 tx_fcb = mtod(m0, struct tsec_tx_fcb *);
734 tx_fcb->flags = 0;
735 tx_fcb->l3_offset = ETHER_HDR_LEN;
736 tx_fcb->l4_offset = sizeof(struct ip);
737
738 if (csum_flags & CSUM_IP)
739 tx_fcb->flags |= TSEC_TX_FCB_IP4 |
740 TSEC_TX_FCB_CSUM_IP;
741
742 if (csum_flags & CSUM_TCP)
743 tx_fcb->flags |= TSEC_TX_FCB_TCP |
744 TSEC_TX_FCB_CSUM_TCP_UDP;
745
746 if (csum_flags & CSUM_UDP)
747 tx_fcb->flags |= TSEC_TX_FCB_UDP |
748 TSEC_TX_FCB_CSUM_TCP_UDP;
749
750 fcb_inserted = 1;
751 }
752
753 mtmp = m_defrag(m0, M_DONTWAIT);
754 if (mtmp)
755 m0 = mtmp;
756
757 if (tsec_encap(sc, m0, fcb_inserted)) {
758 IFQ_DRV_PREPEND(&ifp->if_snd, m0);
759 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
760 break;
761 }
762 queued++;
763 BPF_MTAP(ifp, m0);
764 }
765 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
766 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
767
768 if (queued) {
769 /* Enable transmitter and watchdog timer */
770 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
771 sc->tsec_watchdog = 5;
772 }
773}
774
775static int
776tsec_encap(struct tsec_softc *sc, struct mbuf *m0, int fcb_inserted)
777{
778 struct tsec_desc *tx_desc = NULL;
779 struct ifnet *ifp;
780 bus_dma_segment_t segs[TSEC_TX_NUM_DESC];
781 bus_dmamap_t *mapp;
782 int csum_flag = 0, error, seg, nsegs;
783
784 TSEC_TRANSMIT_LOCK_ASSERT(sc);
785
786 ifp = sc->tsec_ifp;
787
788 if (TSEC_FREE_TX_DESC(sc) == 0) {
789 /* No free descriptors */
790 return (-1);
791 }
792
793 /* Fetch unused map */
794 mapp = TSEC_ALLOC_TX_MAP(sc);
795
796 /* Create mapping in DMA memory */
797 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag,
798 *mapp, m0, segs, &nsegs, BUS_DMA_NOWAIT);
799 if (error != 0 || nsegs > TSEC_FREE_TX_DESC(sc) || nsegs <= 0) {
800 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
801 TSEC_FREE_TX_MAP(sc, mapp);
802 return ((error != 0) ? error : -1);
803 }
804 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_PREWRITE);
805
806 if ((ifp->if_flags & IFF_DEBUG) && (nsegs > 1))
807 if_printf(ifp, "TX buffer has %d segments\n", nsegs);
808
809 if (fcb_inserted)
810 csum_flag = TSEC_TXBD_TOE;
811
812 /* Everything is ok, now we can send buffers */
813 for (seg = 0; seg < nsegs; seg++) {
814 tx_desc = TSEC_GET_CUR_TX_DESC(sc);
815
816 tx_desc->length = segs[seg].ds_len;
817 tx_desc->bufptr = segs[seg].ds_addr;
818
819 /*
820 * Set flags:
821 * - wrap
822 * - checksum
823 * - ready to send
824 * - transmit the CRC sequence after the last data byte
825 * - interrupt after the last buffer
826 */
827 tx_desc->flags =
828 (tx_desc->flags & TSEC_TXBD_W) |
829 ((seg == 0) ? csum_flag : 0) | TSEC_TXBD_R | TSEC_TXBD_TC |
830 ((seg == nsegs - 1) ? TSEC_TXBD_L | TSEC_TXBD_I : 0);
831 }
832
833 /* Save mbuf and DMA mapping for release at later stage */
834 TSEC_PUT_TX_MBUF(sc, m0);
835 TSEC_PUT_TX_MAP(sc, mapp);
836
837 return (0);
838}
839
840static void
841tsec_setfilter(struct tsec_softc *sc)
842{
843 struct ifnet *ifp;
844 uint32_t flags;
845
846 ifp = sc->tsec_ifp;
847 flags = TSEC_READ(sc, TSEC_REG_RCTRL);
848
849 /* Promiscuous mode */
850 if (ifp->if_flags & IFF_PROMISC)
851 flags |= TSEC_RCTRL_PROM;
852 else
853 flags &= ~TSEC_RCTRL_PROM;
854
855 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags);
856}
857
858#ifdef DEVICE_POLLING
859static poll_handler_t tsec_poll;
860
861static int
862tsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
863{
864 uint32_t ie;
865 struct tsec_softc *sc = ifp->if_softc;
866 int rx_npkts;
867
868 rx_npkts = 0;
869
870 TSEC_GLOBAL_LOCK(sc);
871 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
872 TSEC_GLOBAL_UNLOCK(sc);
873 return (rx_npkts);
874 }
875
876 if (cmd == POLL_AND_CHECK_STATUS) {
877 tsec_error_intr_locked(sc, count);
878
879 /* Clear all events reported */
880 ie = TSEC_READ(sc, TSEC_REG_IEVENT);
881 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie);
882 }
883
884 tsec_transmit_intr_locked(sc);
885
886 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc);
887
888 rx_npkts = tsec_receive_intr_locked(sc, count);
889
890 TSEC_RECEIVE_UNLOCK(sc);
891
892 return (rx_npkts);
893}
894#endif /* DEVICE_POLLING */
895
896static int
897tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
898{
899 struct tsec_softc *sc = ifp->if_softc;
900 struct ifreq *ifr = (struct ifreq *)data;
901 device_t dev;
902 int mask, error = 0;
903
904 dev = sc->dev;
905
906 switch (command) {
907 case SIOCSIFMTU:
908 TSEC_GLOBAL_LOCK(sc);
909 if (tsec_set_mtu(sc, ifr->ifr_mtu))
910 ifp->if_mtu = ifr->ifr_mtu;
911 else
912 error = EINVAL;
913 TSEC_GLOBAL_UNLOCK(sc);
914 break;
915 case SIOCSIFFLAGS:
916 TSEC_GLOBAL_LOCK(sc);
917 if (ifp->if_flags & IFF_UP) {
918 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
919 if ((sc->tsec_if_flags ^ ifp->if_flags) &
920 IFF_PROMISC)
921 tsec_setfilter(sc);
922
923 if ((sc->tsec_if_flags ^ ifp->if_flags) &
924 IFF_ALLMULTI)
925 tsec_setup_multicast(sc);
926 } else
927 tsec_init_locked(sc);
928 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
929 tsec_stop(sc);
930
931 sc->tsec_if_flags = ifp->if_flags;
932 TSEC_GLOBAL_UNLOCK(sc);
933 break;
934 case SIOCADDMULTI:
935 case SIOCDELMULTI:
936 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
937 TSEC_GLOBAL_LOCK(sc);
938 tsec_setup_multicast(sc);
939 TSEC_GLOBAL_UNLOCK(sc);
940 }
941 case SIOCGIFMEDIA:
942 case SIOCSIFMEDIA:
943 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media,
944 command);
945 break;
946 case SIOCSIFCAP:
947 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
948 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) {
949 TSEC_GLOBAL_LOCK(sc);
950 ifp->if_capenable &= ~IFCAP_HWCSUM;
951 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap;
952 tsec_offload_setup(sc);
953 TSEC_GLOBAL_UNLOCK(sc);
954 }
955#ifdef DEVICE_POLLING
956 if (mask & IFCAP_POLLING) {
957 if (ifr->ifr_reqcap & IFCAP_POLLING) {
958 error = ether_poll_register(tsec_poll, ifp);
959 if (error)
960 return (error);
961
962 TSEC_GLOBAL_LOCK(sc);
963 /* Disable interrupts */
964 tsec_intrs_ctl(sc, 0);
965 ifp->if_capenable |= IFCAP_POLLING;
966 TSEC_GLOBAL_UNLOCK(sc);
967 } else {
968 error = ether_poll_deregister(ifp);
969 TSEC_GLOBAL_LOCK(sc);
970 /* Enable interrupts */
971 tsec_intrs_ctl(sc, 1);
972 ifp->if_capenable &= ~IFCAP_POLLING;
973 TSEC_GLOBAL_UNLOCK(sc);
974 }
975 }
976#endif
977 break;
978
979 default:
980 error = ether_ioctl(ifp, command, data);
981 }
982
983 /* Flush buffers if not empty */
984 if (ifp->if_flags & IFF_UP)
985 tsec_start(ifp);
986 return (error);
987}
988
989static int
990tsec_ifmedia_upd(struct ifnet *ifp)
991{
992 struct tsec_softc *sc = ifp->if_softc;
993 struct mii_data *mii;
994
995 TSEC_TRANSMIT_LOCK(sc);
996
997 mii = sc->tsec_mii;
998 mii_mediachg(mii);
999
1000 TSEC_TRANSMIT_UNLOCK(sc);
1001 return (0);
1002}
1003
1004static void
1005tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1006{
1007 struct tsec_softc *sc = ifp->if_softc;
1008 struct mii_data *mii;
1009
1010 TSEC_TRANSMIT_LOCK(sc);
1011
1012 mii = sc->tsec_mii;
1013 mii_pollstat(mii);
1014
1015 ifmr->ifm_active = mii->mii_media_active;
1016 ifmr->ifm_status = mii->mii_media_status;
1017
1018 TSEC_TRANSMIT_UNLOCK(sc);
1019}
1020
1021static int
1022tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp,
1023 uint32_t *paddr)
1024{
1025 struct mbuf *new_mbuf;
1026 bus_dma_segment_t seg[1];
1027 int error, nsegs;
1028
1029 KASSERT(mbufp != NULL, ("NULL mbuf pointer!"));
1030
1031 new_mbuf = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MCLBYTES);
1032 if (new_mbuf == NULL)
1033 return (ENOBUFS);
1034 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size;
1035
1036 if (*mbufp) {
1037 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD);
1038 bus_dmamap_unload(tag, map);
1039 }
1040
1041 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs,
1042 BUS_DMA_NOWAIT);
1043 KASSERT(nsegs == 1, ("Too many segments returned!"));
1044 if (nsegs != 1 || error)
1045 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error);
1046
1047#if 0
1048 if (error) {
1049 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n",
1050 error);
1051 m_freem(new_mbuf);
1052 return (ENOBUFS);
1053 }
1054#endif
1055
1056#if 0
1057 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0,
1058 ("Wrong alignment of RX buffer!"));
1059#endif
1060 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD);
1061
1062 (*mbufp) = new_mbuf;
1063 (*paddr) = seg->ds_addr;
1064 return (0);
1065}
1066
1067static void
1068tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1069{
1070 u_int32_t *paddr;
1071
1072 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
1073 paddr = arg;
1074 *paddr = segs->ds_addr;
1075}
1076
1077static int
1078tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap,
1079 bus_size_t dsize, void **vaddr, void *raddr, const char *dname)
1080{
1081 int error;
1082
1083 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1084 error = bus_dma_tag_create(NULL, /* parent */
1085 PAGE_SIZE, 0, /* alignment, boundary */
1086 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1087 BUS_SPACE_MAXADDR, /* highaddr */
1088 NULL, NULL, /* filtfunc, filtfuncarg */
1089 dsize, 1, /* maxsize, nsegments */
1090 dsize, 0, /* maxsegsz, flags */
1091 NULL, NULL, /* lockfunc, lockfuncarg */
1092 dtag); /* dmat */
1093
1094 if (error) {
1095 device_printf(dev, "failed to allocate busdma %s tag\n",
1096 dname);
1097 (*vaddr) = NULL;
1098 return (ENXIO);
1099 }
1100
1101 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1102 dmap);
1103 if (error) {
1104 device_printf(dev, "failed to allocate %s DMA safe memory\n",
1105 dname);
1106 bus_dma_tag_destroy(*dtag);
1107 (*vaddr) = NULL;
1108 return (ENXIO);
1109 }
1110
1111 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize,
1112 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT);
1113 if (error) {
1114 device_printf(dev, "cannot get address of the %s "
1115 "descriptors\n", dname);
1116 bus_dmamem_free(*dtag, *vaddr, *dmap);
1117 bus_dma_tag_destroy(*dtag);
1118 (*vaddr) = NULL;
1119 return (ENXIO);
1120 }
1121
1122 return (0);
1123}
1124
1125static void
1126tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr)
1127{
1128
1129 if (vaddr == NULL)
1130 return;
1131
1132 /* Unmap descriptors from DMA memory */
1133 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD |
1134 BUS_DMASYNC_POSTWRITE);
1135 bus_dmamap_unload(dtag, dmap);
1136
1137 /* Free descriptors memory */
1138 bus_dmamem_free(dtag, vaddr, dmap);
1139
1140 /* Destroy descriptors tag */
1141 bus_dma_tag_destroy(dtag);
1142}
1143
1144static void
1145tsec_free_dma(struct tsec_softc *sc)
1146{
1147 int i;
1148
1149 /* Free TX maps */
1150 for (i = 0; i < TSEC_TX_NUM_DESC; i++)
1151 if (sc->tx_map_data[i] != NULL)
1152 bus_dmamap_destroy(sc->tsec_tx_mtag,
1153 sc->tx_map_data[i]);
1154 /* Destroy tag for TX mbufs */
1155 bus_dma_tag_destroy(sc->tsec_tx_mtag);
1156
1157 /* Free RX mbufs and maps */
1158 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
1159 if (sc->rx_data[i].mbuf) {
1160 /* Unload buffer from DMA */
1161 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map,
1162 BUS_DMASYNC_POSTREAD);
1163 bus_dmamap_unload(sc->tsec_rx_mtag,
1164 sc->rx_data[i].map);
1165
1166 /* Free buffer */
1167 m_freem(sc->rx_data[i].mbuf);
1168 }
1169 /* Destroy map for this buffer */
1170 if (sc->rx_data[i].map != NULL)
1171 bus_dmamap_destroy(sc->tsec_rx_mtag,
1172 sc->rx_data[i].map);
1173 }
1174 /* Destroy tag for RX mbufs */
1175 bus_dma_tag_destroy(sc->tsec_rx_mtag);
1176
1177 /* Unload TX/RX descriptors */
1178 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1179 sc->tsec_tx_vaddr);
1180 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1181 sc->tsec_rx_vaddr);
1182}
1183
1184static void
1185tsec_stop(struct tsec_softc *sc)
1186{
1187 struct ifnet *ifp;
1188 struct mbuf *m0;
1189 bus_dmamap_t *mapp;
1190 uint32_t tmpval;
1191
1192 TSEC_GLOBAL_LOCK_ASSERT(sc);
1193
1194 ifp = sc->tsec_ifp;
1195
1196 /* Disable interface and watchdog timer */
1197 callout_stop(&sc->tsec_callout);
1198 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1199 sc->tsec_watchdog = 0;
1200
1201 /* Disable all interrupts and stop DMA */
1202 tsec_intrs_ctl(sc, 0);
1203 tsec_dma_ctl(sc, 0);
1204
1205 /* Remove pending data from TX queue */
1206 while (!TSEC_EMPTYQ_TX_MBUF(sc)) {
1207 m0 = TSEC_GET_TX_MBUF(sc);
1208 mapp = TSEC_GET_TX_MAP(sc);
1209
1210 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp,
1211 BUS_DMASYNC_POSTWRITE);
1212 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
1213
1214 TSEC_FREE_TX_MAP(sc, mapp);
1215 m_freem(m0);
1216 }
1217
1218 /* Disable RX and TX */
1219 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1);
1220 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
1221 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval);
1222 DELAY(10);
1223}
1224
1225static void
1226tsec_tick(void *arg)
1227{
1228 struct tsec_softc *sc = arg;
1229 struct ifnet *ifp;
1230 int link;
1231
1232 TSEC_GLOBAL_LOCK(sc);
1233
1234 tsec_watchdog(sc);
1235
1236 ifp = sc->tsec_ifp;
1237 link = sc->tsec_link;
1238
1239 mii_tick(sc->tsec_mii);
1240
1241 if (link == 0 && sc->tsec_link == 1 &&
1242 (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)))
1243 tsec_start_locked(ifp);
1244
1245 /* Schedule another timeout one second from now. */
1246 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
1247
1248 TSEC_GLOBAL_UNLOCK(sc);
1249}
1250
1251/*
1252 * This is the core RX routine. It replenishes mbufs in the descriptor and
1253 * sends data which have been dma'ed into host memory to upper layer.
1254 *
1255 * Loops at most count times if count is > 0, or until done if count < 0.
1256 */
1257static int
1258tsec_receive_intr_locked(struct tsec_softc *sc, int count)
1259{
1260 struct tsec_desc *rx_desc;
1261 struct ifnet *ifp;
1262 struct rx_data_type *rx_data;
1263 struct mbuf *m;
1264 device_t dev;
1265 uint32_t i;
1266 int c, rx_npkts;
1267 uint16_t flags;
1268
1269 TSEC_RECEIVE_LOCK_ASSERT(sc);
1270
1271 ifp = sc->tsec_ifp;
1272 rx_data = sc->rx_data;
1273 dev = sc->dev;
1274 rx_npkts = 0;
1275
1276 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1277 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1278
1279 for (c = 0; ; c++) {
1280 if (count >= 0 && count-- == 0)
1281 break;
1282
1283 rx_desc = TSEC_GET_CUR_RX_DESC(sc);
1284 flags = rx_desc->flags;
1285
1286 /* Check if there is anything to receive */
1287 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) {
1288 /*
1289 * Avoid generating another interrupt
1290 */
1291 if (flags & TSEC_RXBD_E)
1292 TSEC_WRITE(sc, TSEC_REG_IEVENT,
1293 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1294 /*
1295 * We didn't consume current descriptor and have to
1296 * return it to the queue
1297 */
1298 TSEC_BACK_CUR_RX_DESC(sc);
1299 break;
1300 }
1301
1302 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO |
1303 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) {
1304
1305 rx_desc->length = 0;
1306 rx_desc->flags = (rx_desc->flags &
1307 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I;
1308
1309 if (sc->frame != NULL) {
1310 m_free(sc->frame);
1311 sc->frame = NULL;
1312 }
1313
1314 continue;
1315 }
1316
1317 /* Ok... process frame */
1318 i = TSEC_GET_CUR_RX_DESC_CNT(sc);
1319 m = rx_data[i].mbuf;
1320 m->m_len = rx_desc->length;
1321
1322 if (sc->frame != NULL) {
1323 if ((flags & TSEC_RXBD_L) != 0)
1324 m->m_len -= m_length(sc->frame, NULL);
1325
1326 m->m_flags &= ~M_PKTHDR;
1327 m_cat(sc->frame, m);
1328 } else {
1329 sc->frame = m;
1330 }
1331
1332 m = NULL;
1333
1334 if ((flags & TSEC_RXBD_L) != 0) {
1335 m = sc->frame;
1336 sc->frame = NULL;
1337 }
1338
1339 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map,
1340 &rx_data[i].mbuf, &rx_data[i].paddr)) {
1341 ifp->if_ierrors++;
1342 /*
1343 * We ran out of mbufs; didn't consume current
1344 * descriptor and have to return it to the queue.
1345 */
1346 TSEC_BACK_CUR_RX_DESC(sc);
1347 break;
1348 }
1349
1350 /* Attach new buffer to descriptor and clear flags */
1351 rx_desc->bufptr = rx_data[i].paddr;
1352 rx_desc->length = 0;
1353 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) |
1354 TSEC_RXBD_E | TSEC_RXBD_I;
1355
1356 if (m != NULL) {
1357 m->m_pkthdr.rcvif = ifp;
1358
1359 m_fixhdr(m);
1360 m_adj(m, -ETHER_CRC_LEN);
1361
1362 if (sc->is_etsec)
1363 tsec_offload_process_frame(sc, m);
1364
1365 TSEC_RECEIVE_UNLOCK(sc);
1366 (*ifp->if_input)(ifp, m);
1367 TSEC_RECEIVE_LOCK(sc);
1368 rx_npkts++;
1369 }
1370 }
1371
1372 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1373 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1374
1375 /*
1376 * Make sure TSEC receiver is not halted.
1377 *
1378 * Various conditions can stop the TSEC receiver, but not all are
1379 * signaled and handled by error interrupt, so make sure the receiver
1380 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when
1381 * halted, and is harmless if already running.
1382 */
1383 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT);
1384 return (rx_npkts);
1385}
1386
1387void
1388tsec_receive_intr(void *arg)
1389{
1390 struct tsec_softc *sc = arg;
1391
1392 TSEC_RECEIVE_LOCK(sc);
1393
1394#ifdef DEVICE_POLLING
1395 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1396 TSEC_RECEIVE_UNLOCK(sc);
1397 return;
1398 }
1399#endif
1400
1401 /* Confirm the interrupt was received by driver */
1402 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1403 tsec_receive_intr_locked(sc, -1);
1404
1405 TSEC_RECEIVE_UNLOCK(sc);
1406}
1407
1408static void
1409tsec_transmit_intr_locked(struct tsec_softc *sc)
1410{
1411 struct tsec_desc *tx_desc;
1412 struct ifnet *ifp;
1413 struct mbuf *m0;
1414 bus_dmamap_t *mapp;
1415 int send = 0;
1416
1417 TSEC_TRANSMIT_LOCK_ASSERT(sc);
1418
1419 ifp = sc->tsec_ifp;
1420
1421 /* Update collision statistics */
1422 ifp->if_collisions += TSEC_READ(sc, TSEC_REG_MON_TNCL);
1423
1424 /* Reset collision counters in hardware */
1425 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
1426 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
1427 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
1428 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
1429 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
1430
1431 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1432 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1433
1434 while (TSEC_CUR_DIFF_DIRTY_TX_DESC(sc)) {
1435 tx_desc = TSEC_GET_DIRTY_TX_DESC(sc);
1436 if (tx_desc->flags & TSEC_TXBD_R) {
1437 TSEC_BACK_DIRTY_TX_DESC(sc);
1438 break;
1439 }
1440
1441 if ((tx_desc->flags & TSEC_TXBD_L) == 0)
1442 continue;
1443
1444 /*
1445 * This is the last buf in this packet, so unmap and free it.
1446 */
1447 m0 = TSEC_GET_TX_MBUF(sc);
1448 mapp = TSEC_GET_TX_MAP(sc);
1449
1450 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp,
1451 BUS_DMASYNC_POSTWRITE);
1452 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
1453
1454 TSEC_FREE_TX_MAP(sc, mapp);
1455 m_freem(m0);
1456
1457 ifp->if_opackets++;
1458 send = 1;
1459 }
1460 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1461 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1462
1463 if (send) {
1464 /* Now send anything that was pending */
1465 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1466 tsec_start_locked(ifp);
1467
1468 /* Stop wathdog if all sent */
1469 if (TSEC_EMPTYQ_TX_MBUF(sc))
1470 sc->tsec_watchdog = 0;
1471 }
1472}
1473
1474void
1475tsec_transmit_intr(void *arg)
1476{
1477 struct tsec_softc *sc = arg;
1478
1479 TSEC_TRANSMIT_LOCK(sc);
1480
1481#ifdef DEVICE_POLLING
1482 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1483 TSEC_TRANSMIT_UNLOCK(sc);
1484 return;
1485 }
1486#endif
1487 /* Confirm the interrupt was received by driver */
1488 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF);
1489 tsec_transmit_intr_locked(sc);
1490
1491 TSEC_TRANSMIT_UNLOCK(sc);
1492}
1493
1494static void
1495tsec_error_intr_locked(struct tsec_softc *sc, int count)
1496{
1497 struct ifnet *ifp;
1498 uint32_t eflags;
1499
1500 TSEC_GLOBAL_LOCK_ASSERT(sc);
1501
1502 ifp = sc->tsec_ifp;
1503
1504 eflags = TSEC_READ(sc, TSEC_REG_IEVENT);
1505
1506 /* Clear events bits in hardware */
1507 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY |
1508 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT |
1509 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC |
1510 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN);
1511
1512 /* Check transmitter errors */
1513 if (eflags & TSEC_IEVENT_TXE) {
1514 ifp->if_oerrors++;
1515
1516 if (eflags & TSEC_IEVENT_LC)
1517 ifp->if_collisions++;
1518
1519 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
1520 }
1521
1522 /* Check receiver errors */
1523 if (eflags & TSEC_IEVENT_BSY) {
1524 ifp->if_ierrors++;
1525 ifp->if_iqdrops++;
1526
1527 /* Get data from RX buffers */
1528 tsec_receive_intr_locked(sc, count);
1529 }
1530
1531 if (ifp->if_flags & IFF_DEBUG)
1532 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n",
1533 eflags);
1534
1535 if (eflags & TSEC_IEVENT_EBERR) {
1536 if_printf(ifp, "System bus error occurred during"
1537 "DMA transaction (flags: 0x%x)\n", eflags);
1538 tsec_init_locked(sc);
1539 }
1540
1541 if (eflags & TSEC_IEVENT_BABT)
1542 ifp->if_oerrors++;
1543
1544 if (eflags & TSEC_IEVENT_BABR)
1545 ifp->if_ierrors++;
1546}
1547
1548void
1549tsec_error_intr(void *arg)
1550{
1551 struct tsec_softc *sc = arg;
1552
1553 TSEC_GLOBAL_LOCK(sc);
1554 tsec_error_intr_locked(sc, -1);
1555 TSEC_GLOBAL_UNLOCK(sc);
1556}
1557
1558int
1559tsec_miibus_readreg(device_t dev, int phy, int reg)
1560{
1561 struct tsec_softc *sc;
1562 uint32_t timeout;
1563
| 415 TSEC_MIIMIND_BUSY))
416 DELAY(TSEC_READ_DELAY);
417 if (timeout == 0) {
418 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n");
419 return;
420 }
421
422 /* Step 9: Setup the MII Mgmt */
423 mii_mediachg(sc->tsec_mii);
424
425 /* Step 10: Clear IEVENT register */
426 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff);
427
428 /* Step 11: Enable interrupts */
429#ifdef DEVICE_POLLING
430 /*
431 * ...only if polling is not turned on. Disable interrupts explicitly
432 * if polling is enabled.
433 */
434 if (ifp->if_capenable & IFCAP_POLLING )
435 tsec_intrs_ctl(sc, 0);
436 else
437#endif /* DEVICE_POLLING */
438 tsec_intrs_ctl(sc, 1);
439
440 /* Step 12: Initialize IADDRn */
441 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0);
442 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0);
443 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0);
444 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0);
445 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0);
446 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0);
447 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0);
448 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0);
449
450 /* Step 13: Initialize GADDRn */
451 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0);
452 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0);
453 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0);
454 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0);
455 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0);
456 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0);
457 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0);
458 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0);
459
460 /* Step 14: Initialize RCTRL */
461 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0);
462
463 /* Step 15: Initialize DMACTRL */
464 tsec_dma_ctl(sc, 1);
465
466 /* Step 16: Initialize FIFO_PAUSE_CTRL */
467 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN);
468
469 /*
470 * Step 17: Initialize transmit/receive descriptor rings.
471 * Initialize TBASE and RBASE.
472 */
473 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr);
474 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr);
475
476 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
477 tx_desc[i].bufptr = 0;
478 tx_desc[i].length = 0;
479 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ?
480 TSEC_TXBD_W : 0);
481 }
482 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
483 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
484
485 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
486 rx_desc[i].bufptr = sc->rx_data[i].paddr;
487 rx_desc[i].length = 0;
488 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I |
489 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0);
490 }
491 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
492 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
493
494 /* Step 18: Initialize the maximum receive buffer length */
495 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES);
496
497 /* Step 19: Configure ethernet frame sizes */
498 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE);
499 tsec_set_mtu(sc, ifp->if_mtu);
500
501 /* Step 20: Enable Rx and RxBD sdata snooping */
502 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN);
503 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0);
504
505 /* Step 21: Reset collision counters in hardware */
506 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
507 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
508 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
509 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
510 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
511
512 /* Step 22: Mask all CAM interrupts */
513 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff);
514 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff);
515
516 /* Step 23: Enable Rx and Tx */
517 val = TSEC_READ(sc, TSEC_REG_MACCFG1);
518 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
519 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val);
520
521 /* Step 24: Reset TSEC counters for Tx and Rx rings */
522 TSEC_TX_RX_COUNTERS_INIT(sc);
523
524 /* Step 25: Setup TCP/IP Off-Load engine */
525 if (sc->is_etsec)
526 tsec_offload_setup(sc);
527
528 /* Step 26: Setup multicast filters */
529 tsec_setup_multicast(sc);
530
531 /* Step 27: Activate network interface */
532 ifp->if_drv_flags |= IFF_DRV_RUNNING;
533 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
534 sc->tsec_if_flags = ifp->if_flags;
535 sc->tsec_watchdog = 0;
536
537 /* Schedule watchdog timeout */
538 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
539}
540
541static void
542tsec_set_mac_address(struct tsec_softc *sc)
543{
544 uint32_t macbuf[2] = { 0, 0 };
545 char *macbufp, *curmac;
546 int i;
547
548 TSEC_GLOBAL_LOCK_ASSERT(sc);
549
550 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)),
551 ("tsec_set_mac_address: (%d <= %d", ETHER_ADDR_LEN,
552 sizeof(macbuf)));
553
554 macbufp = (char *)macbuf;
555 curmac = (char *)IF_LLADDR(sc->tsec_ifp);
556
557 /* Correct order of MAC address bytes */
558 for (i = 1; i <= ETHER_ADDR_LEN; i++)
559 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1];
560
561 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */
562 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]);
563 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]);
564}
565
566/*
567 * DMA control function, if argument state is:
568 * 0 - DMA engine will be disabled
569 * 1 - DMA engine will be enabled
570 */
571static void
572tsec_dma_ctl(struct tsec_softc *sc, int state)
573{
574 device_t dev;
575 uint32_t dma_flags, timeout;
576
577 dev = sc->dev;
578
579 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL);
580
581 switch (state) {
582 case 0:
583 /* Temporarily clear stop graceful stop bits. */
584 tsec_dma_ctl(sc, 1000);
585
586 /* Set it again */
587 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
588 break;
589 case 1000:
590 case 1:
591 /* Set write with response (WWR), wait (WOP) and snoop bits */
592 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN |
593 DMACTRL_WWR | DMACTRL_WOP);
594
595 /* Clear graceful stop bits */
596 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
597 break;
598 default:
599 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n",
600 state);
601 }
602
603 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags);
604
605 switch (state) {
606 case 0:
607 /* Wait for DMA stop */
608 timeout = TSEC_READ_RETRY;
609 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) &
610 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC))))
611 DELAY(TSEC_READ_DELAY);
612
613 if (timeout == 0)
614 device_printf(dev, "tsec_dma_ctl(): timeout!\n");
615 break;
616 case 1:
617 /* Restart transmission function */
618 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
619 }
620}
621
622/*
623 * Interrupts control function, if argument state is:
624 * 0 - all TSEC interrupts will be masked
625 * 1 - all TSEC interrupts will be unmasked
626 */
627static void
628tsec_intrs_ctl(struct tsec_softc *sc, int state)
629{
630 device_t dev;
631
632 dev = sc->dev;
633
634 switch (state) {
635 case 0:
636 TSEC_WRITE(sc, TSEC_REG_IMASK, 0);
637 break;
638 case 1:
639 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN |
640 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN |
641 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN |
642 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN);
643 break;
644 default:
645 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n",
646 state);
647 }
648}
649
650static void
651tsec_reset_mac(struct tsec_softc *sc)
652{
653 uint32_t maccfg1_flags;
654
655 /* Set soft reset bit */
656 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
657 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET;
658 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
659
660 /* Clear soft reset bit */
661 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
662 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET;
663 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
664}
665
666static void
667tsec_watchdog(struct tsec_softc *sc)
668{
669 struct ifnet *ifp;
670
671 TSEC_GLOBAL_LOCK_ASSERT(sc);
672
673 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0)
674 return;
675
676 ifp = sc->tsec_ifp;
677 ifp->if_oerrors++;
678 if_printf(ifp, "watchdog timeout\n");
679
680 tsec_stop(sc);
681 tsec_init_locked(sc);
682}
683
684static void
685tsec_start(struct ifnet *ifp)
686{
687 struct tsec_softc *sc = ifp->if_softc;
688
689 TSEC_TRANSMIT_LOCK(sc);
690 tsec_start_locked(ifp);
691 TSEC_TRANSMIT_UNLOCK(sc);
692}
693
694static void
695tsec_start_locked(struct ifnet *ifp)
696{
697 struct tsec_softc *sc;
698 struct mbuf *m0, *mtmp;
699 struct tsec_tx_fcb *tx_fcb;
700 unsigned int queued = 0;
701 int csum_flags, fcb_inserted = 0;
702
703 sc = ifp->if_softc;
704
705 TSEC_TRANSMIT_LOCK_ASSERT(sc);
706
707 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
708 IFF_DRV_RUNNING)
709 return;
710
711 if (sc->tsec_link == 0)
712 return;
713
714 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
715 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
716
717 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
718 /* Get packet from the queue */
719 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
720 if (m0 == NULL)
721 break;
722
723 /* Insert TCP/IP Off-load frame control block */
724 csum_flags = m0->m_pkthdr.csum_flags;
725 if (csum_flags) {
726
727 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_DONTWAIT);
728 if (m0 == NULL)
729 break;
730
731 tx_fcb = mtod(m0, struct tsec_tx_fcb *);
732 tx_fcb->flags = 0;
733 tx_fcb->l3_offset = ETHER_HDR_LEN;
734 tx_fcb->l4_offset = sizeof(struct ip);
735
736 if (csum_flags & CSUM_IP)
737 tx_fcb->flags |= TSEC_TX_FCB_IP4 |
738 TSEC_TX_FCB_CSUM_IP;
739
740 if (csum_flags & CSUM_TCP)
741 tx_fcb->flags |= TSEC_TX_FCB_TCP |
742 TSEC_TX_FCB_CSUM_TCP_UDP;
743
744 if (csum_flags & CSUM_UDP)
745 tx_fcb->flags |= TSEC_TX_FCB_UDP |
746 TSEC_TX_FCB_CSUM_TCP_UDP;
747
748 fcb_inserted = 1;
749 }
750
751 mtmp = m_defrag(m0, M_DONTWAIT);
752 if (mtmp)
753 m0 = mtmp;
754
755 if (tsec_encap(sc, m0, fcb_inserted)) {
756 IFQ_DRV_PREPEND(&ifp->if_snd, m0);
757 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
758 break;
759 }
760 queued++;
761 BPF_MTAP(ifp, m0);
762 }
763 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
764 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
765
766 if (queued) {
767 /* Enable transmitter and watchdog timer */
768 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
769 sc->tsec_watchdog = 5;
770 }
771}
772
773static int
774tsec_encap(struct tsec_softc *sc, struct mbuf *m0, int fcb_inserted)
775{
776 struct tsec_desc *tx_desc = NULL;
777 struct ifnet *ifp;
778 bus_dma_segment_t segs[TSEC_TX_NUM_DESC];
779 bus_dmamap_t *mapp;
780 int csum_flag = 0, error, seg, nsegs;
781
782 TSEC_TRANSMIT_LOCK_ASSERT(sc);
783
784 ifp = sc->tsec_ifp;
785
786 if (TSEC_FREE_TX_DESC(sc) == 0) {
787 /* No free descriptors */
788 return (-1);
789 }
790
791 /* Fetch unused map */
792 mapp = TSEC_ALLOC_TX_MAP(sc);
793
794 /* Create mapping in DMA memory */
795 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag,
796 *mapp, m0, segs, &nsegs, BUS_DMA_NOWAIT);
797 if (error != 0 || nsegs > TSEC_FREE_TX_DESC(sc) || nsegs <= 0) {
798 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
799 TSEC_FREE_TX_MAP(sc, mapp);
800 return ((error != 0) ? error : -1);
801 }
802 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_PREWRITE);
803
804 if ((ifp->if_flags & IFF_DEBUG) && (nsegs > 1))
805 if_printf(ifp, "TX buffer has %d segments\n", nsegs);
806
807 if (fcb_inserted)
808 csum_flag = TSEC_TXBD_TOE;
809
810 /* Everything is ok, now we can send buffers */
811 for (seg = 0; seg < nsegs; seg++) {
812 tx_desc = TSEC_GET_CUR_TX_DESC(sc);
813
814 tx_desc->length = segs[seg].ds_len;
815 tx_desc->bufptr = segs[seg].ds_addr;
816
817 /*
818 * Set flags:
819 * - wrap
820 * - checksum
821 * - ready to send
822 * - transmit the CRC sequence after the last data byte
823 * - interrupt after the last buffer
824 */
825 tx_desc->flags =
826 (tx_desc->flags & TSEC_TXBD_W) |
827 ((seg == 0) ? csum_flag : 0) | TSEC_TXBD_R | TSEC_TXBD_TC |
828 ((seg == nsegs - 1) ? TSEC_TXBD_L | TSEC_TXBD_I : 0);
829 }
830
831 /* Save mbuf and DMA mapping for release at later stage */
832 TSEC_PUT_TX_MBUF(sc, m0);
833 TSEC_PUT_TX_MAP(sc, mapp);
834
835 return (0);
836}
837
838static void
839tsec_setfilter(struct tsec_softc *sc)
840{
841 struct ifnet *ifp;
842 uint32_t flags;
843
844 ifp = sc->tsec_ifp;
845 flags = TSEC_READ(sc, TSEC_REG_RCTRL);
846
847 /* Promiscuous mode */
848 if (ifp->if_flags & IFF_PROMISC)
849 flags |= TSEC_RCTRL_PROM;
850 else
851 flags &= ~TSEC_RCTRL_PROM;
852
853 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags);
854}
855
856#ifdef DEVICE_POLLING
857static poll_handler_t tsec_poll;
858
859static int
860tsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
861{
862 uint32_t ie;
863 struct tsec_softc *sc = ifp->if_softc;
864 int rx_npkts;
865
866 rx_npkts = 0;
867
868 TSEC_GLOBAL_LOCK(sc);
869 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
870 TSEC_GLOBAL_UNLOCK(sc);
871 return (rx_npkts);
872 }
873
874 if (cmd == POLL_AND_CHECK_STATUS) {
875 tsec_error_intr_locked(sc, count);
876
877 /* Clear all events reported */
878 ie = TSEC_READ(sc, TSEC_REG_IEVENT);
879 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie);
880 }
881
882 tsec_transmit_intr_locked(sc);
883
884 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc);
885
886 rx_npkts = tsec_receive_intr_locked(sc, count);
887
888 TSEC_RECEIVE_UNLOCK(sc);
889
890 return (rx_npkts);
891}
892#endif /* DEVICE_POLLING */
893
894static int
895tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
896{
897 struct tsec_softc *sc = ifp->if_softc;
898 struct ifreq *ifr = (struct ifreq *)data;
899 device_t dev;
900 int mask, error = 0;
901
902 dev = sc->dev;
903
904 switch (command) {
905 case SIOCSIFMTU:
906 TSEC_GLOBAL_LOCK(sc);
907 if (tsec_set_mtu(sc, ifr->ifr_mtu))
908 ifp->if_mtu = ifr->ifr_mtu;
909 else
910 error = EINVAL;
911 TSEC_GLOBAL_UNLOCK(sc);
912 break;
913 case SIOCSIFFLAGS:
914 TSEC_GLOBAL_LOCK(sc);
915 if (ifp->if_flags & IFF_UP) {
916 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
917 if ((sc->tsec_if_flags ^ ifp->if_flags) &
918 IFF_PROMISC)
919 tsec_setfilter(sc);
920
921 if ((sc->tsec_if_flags ^ ifp->if_flags) &
922 IFF_ALLMULTI)
923 tsec_setup_multicast(sc);
924 } else
925 tsec_init_locked(sc);
926 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
927 tsec_stop(sc);
928
929 sc->tsec_if_flags = ifp->if_flags;
930 TSEC_GLOBAL_UNLOCK(sc);
931 break;
932 case SIOCADDMULTI:
933 case SIOCDELMULTI:
934 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
935 TSEC_GLOBAL_LOCK(sc);
936 tsec_setup_multicast(sc);
937 TSEC_GLOBAL_UNLOCK(sc);
938 }
939 case SIOCGIFMEDIA:
940 case SIOCSIFMEDIA:
941 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media,
942 command);
943 break;
944 case SIOCSIFCAP:
945 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
946 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) {
947 TSEC_GLOBAL_LOCK(sc);
948 ifp->if_capenable &= ~IFCAP_HWCSUM;
949 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap;
950 tsec_offload_setup(sc);
951 TSEC_GLOBAL_UNLOCK(sc);
952 }
953#ifdef DEVICE_POLLING
954 if (mask & IFCAP_POLLING) {
955 if (ifr->ifr_reqcap & IFCAP_POLLING) {
956 error = ether_poll_register(tsec_poll, ifp);
957 if (error)
958 return (error);
959
960 TSEC_GLOBAL_LOCK(sc);
961 /* Disable interrupts */
962 tsec_intrs_ctl(sc, 0);
963 ifp->if_capenable |= IFCAP_POLLING;
964 TSEC_GLOBAL_UNLOCK(sc);
965 } else {
966 error = ether_poll_deregister(ifp);
967 TSEC_GLOBAL_LOCK(sc);
968 /* Enable interrupts */
969 tsec_intrs_ctl(sc, 1);
970 ifp->if_capenable &= ~IFCAP_POLLING;
971 TSEC_GLOBAL_UNLOCK(sc);
972 }
973 }
974#endif
975 break;
976
977 default:
978 error = ether_ioctl(ifp, command, data);
979 }
980
981 /* Flush buffers if not empty */
982 if (ifp->if_flags & IFF_UP)
983 tsec_start(ifp);
984 return (error);
985}
986
987static int
988tsec_ifmedia_upd(struct ifnet *ifp)
989{
990 struct tsec_softc *sc = ifp->if_softc;
991 struct mii_data *mii;
992
993 TSEC_TRANSMIT_LOCK(sc);
994
995 mii = sc->tsec_mii;
996 mii_mediachg(mii);
997
998 TSEC_TRANSMIT_UNLOCK(sc);
999 return (0);
1000}
1001
1002static void
1003tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1004{
1005 struct tsec_softc *sc = ifp->if_softc;
1006 struct mii_data *mii;
1007
1008 TSEC_TRANSMIT_LOCK(sc);
1009
1010 mii = sc->tsec_mii;
1011 mii_pollstat(mii);
1012
1013 ifmr->ifm_active = mii->mii_media_active;
1014 ifmr->ifm_status = mii->mii_media_status;
1015
1016 TSEC_TRANSMIT_UNLOCK(sc);
1017}
1018
1019static int
1020tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp,
1021 uint32_t *paddr)
1022{
1023 struct mbuf *new_mbuf;
1024 bus_dma_segment_t seg[1];
1025 int error, nsegs;
1026
1027 KASSERT(mbufp != NULL, ("NULL mbuf pointer!"));
1028
1029 new_mbuf = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MCLBYTES);
1030 if (new_mbuf == NULL)
1031 return (ENOBUFS);
1032 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size;
1033
1034 if (*mbufp) {
1035 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD);
1036 bus_dmamap_unload(tag, map);
1037 }
1038
1039 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs,
1040 BUS_DMA_NOWAIT);
1041 KASSERT(nsegs == 1, ("Too many segments returned!"));
1042 if (nsegs != 1 || error)
1043 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error);
1044
1045#if 0
1046 if (error) {
1047 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n",
1048 error);
1049 m_freem(new_mbuf);
1050 return (ENOBUFS);
1051 }
1052#endif
1053
1054#if 0
1055 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0,
1056 ("Wrong alignment of RX buffer!"));
1057#endif
1058 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD);
1059
1060 (*mbufp) = new_mbuf;
1061 (*paddr) = seg->ds_addr;
1062 return (0);
1063}
1064
1065static void
1066tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1067{
1068 u_int32_t *paddr;
1069
1070 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
1071 paddr = arg;
1072 *paddr = segs->ds_addr;
1073}
1074
1075static int
1076tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap,
1077 bus_size_t dsize, void **vaddr, void *raddr, const char *dname)
1078{
1079 int error;
1080
1081 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1082 error = bus_dma_tag_create(NULL, /* parent */
1083 PAGE_SIZE, 0, /* alignment, boundary */
1084 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1085 BUS_SPACE_MAXADDR, /* highaddr */
1086 NULL, NULL, /* filtfunc, filtfuncarg */
1087 dsize, 1, /* maxsize, nsegments */
1088 dsize, 0, /* maxsegsz, flags */
1089 NULL, NULL, /* lockfunc, lockfuncarg */
1090 dtag); /* dmat */
1091
1092 if (error) {
1093 device_printf(dev, "failed to allocate busdma %s tag\n",
1094 dname);
1095 (*vaddr) = NULL;
1096 return (ENXIO);
1097 }
1098
1099 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1100 dmap);
1101 if (error) {
1102 device_printf(dev, "failed to allocate %s DMA safe memory\n",
1103 dname);
1104 bus_dma_tag_destroy(*dtag);
1105 (*vaddr) = NULL;
1106 return (ENXIO);
1107 }
1108
1109 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize,
1110 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT);
1111 if (error) {
1112 device_printf(dev, "cannot get address of the %s "
1113 "descriptors\n", dname);
1114 bus_dmamem_free(*dtag, *vaddr, *dmap);
1115 bus_dma_tag_destroy(*dtag);
1116 (*vaddr) = NULL;
1117 return (ENXIO);
1118 }
1119
1120 return (0);
1121}
1122
1123static void
1124tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr)
1125{
1126
1127 if (vaddr == NULL)
1128 return;
1129
1130 /* Unmap descriptors from DMA memory */
1131 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD |
1132 BUS_DMASYNC_POSTWRITE);
1133 bus_dmamap_unload(dtag, dmap);
1134
1135 /* Free descriptors memory */
1136 bus_dmamem_free(dtag, vaddr, dmap);
1137
1138 /* Destroy descriptors tag */
1139 bus_dma_tag_destroy(dtag);
1140}
1141
1142static void
1143tsec_free_dma(struct tsec_softc *sc)
1144{
1145 int i;
1146
1147 /* Free TX maps */
1148 for (i = 0; i < TSEC_TX_NUM_DESC; i++)
1149 if (sc->tx_map_data[i] != NULL)
1150 bus_dmamap_destroy(sc->tsec_tx_mtag,
1151 sc->tx_map_data[i]);
1152 /* Destroy tag for TX mbufs */
1153 bus_dma_tag_destroy(sc->tsec_tx_mtag);
1154
1155 /* Free RX mbufs and maps */
1156 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
1157 if (sc->rx_data[i].mbuf) {
1158 /* Unload buffer from DMA */
1159 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map,
1160 BUS_DMASYNC_POSTREAD);
1161 bus_dmamap_unload(sc->tsec_rx_mtag,
1162 sc->rx_data[i].map);
1163
1164 /* Free buffer */
1165 m_freem(sc->rx_data[i].mbuf);
1166 }
1167 /* Destroy map for this buffer */
1168 if (sc->rx_data[i].map != NULL)
1169 bus_dmamap_destroy(sc->tsec_rx_mtag,
1170 sc->rx_data[i].map);
1171 }
1172 /* Destroy tag for RX mbufs */
1173 bus_dma_tag_destroy(sc->tsec_rx_mtag);
1174
1175 /* Unload TX/RX descriptors */
1176 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1177 sc->tsec_tx_vaddr);
1178 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1179 sc->tsec_rx_vaddr);
1180}
1181
1182static void
1183tsec_stop(struct tsec_softc *sc)
1184{
1185 struct ifnet *ifp;
1186 struct mbuf *m0;
1187 bus_dmamap_t *mapp;
1188 uint32_t tmpval;
1189
1190 TSEC_GLOBAL_LOCK_ASSERT(sc);
1191
1192 ifp = sc->tsec_ifp;
1193
1194 /* Disable interface and watchdog timer */
1195 callout_stop(&sc->tsec_callout);
1196 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1197 sc->tsec_watchdog = 0;
1198
1199 /* Disable all interrupts and stop DMA */
1200 tsec_intrs_ctl(sc, 0);
1201 tsec_dma_ctl(sc, 0);
1202
1203 /* Remove pending data from TX queue */
1204 while (!TSEC_EMPTYQ_TX_MBUF(sc)) {
1205 m0 = TSEC_GET_TX_MBUF(sc);
1206 mapp = TSEC_GET_TX_MAP(sc);
1207
1208 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp,
1209 BUS_DMASYNC_POSTWRITE);
1210 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
1211
1212 TSEC_FREE_TX_MAP(sc, mapp);
1213 m_freem(m0);
1214 }
1215
1216 /* Disable RX and TX */
1217 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1);
1218 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
1219 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval);
1220 DELAY(10);
1221}
1222
1223static void
1224tsec_tick(void *arg)
1225{
1226 struct tsec_softc *sc = arg;
1227 struct ifnet *ifp;
1228 int link;
1229
1230 TSEC_GLOBAL_LOCK(sc);
1231
1232 tsec_watchdog(sc);
1233
1234 ifp = sc->tsec_ifp;
1235 link = sc->tsec_link;
1236
1237 mii_tick(sc->tsec_mii);
1238
1239 if (link == 0 && sc->tsec_link == 1 &&
1240 (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)))
1241 tsec_start_locked(ifp);
1242
1243 /* Schedule another timeout one second from now. */
1244 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
1245
1246 TSEC_GLOBAL_UNLOCK(sc);
1247}
1248
1249/*
1250 * This is the core RX routine. It replenishes mbufs in the descriptor and
1251 * sends data which have been dma'ed into host memory to upper layer.
1252 *
1253 * Loops at most count times if count is > 0, or until done if count < 0.
1254 */
1255static int
1256tsec_receive_intr_locked(struct tsec_softc *sc, int count)
1257{
1258 struct tsec_desc *rx_desc;
1259 struct ifnet *ifp;
1260 struct rx_data_type *rx_data;
1261 struct mbuf *m;
1262 device_t dev;
1263 uint32_t i;
1264 int c, rx_npkts;
1265 uint16_t flags;
1266
1267 TSEC_RECEIVE_LOCK_ASSERT(sc);
1268
1269 ifp = sc->tsec_ifp;
1270 rx_data = sc->rx_data;
1271 dev = sc->dev;
1272 rx_npkts = 0;
1273
1274 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1275 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1276
1277 for (c = 0; ; c++) {
1278 if (count >= 0 && count-- == 0)
1279 break;
1280
1281 rx_desc = TSEC_GET_CUR_RX_DESC(sc);
1282 flags = rx_desc->flags;
1283
1284 /* Check if there is anything to receive */
1285 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) {
1286 /*
1287 * Avoid generating another interrupt
1288 */
1289 if (flags & TSEC_RXBD_E)
1290 TSEC_WRITE(sc, TSEC_REG_IEVENT,
1291 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1292 /*
1293 * We didn't consume current descriptor and have to
1294 * return it to the queue
1295 */
1296 TSEC_BACK_CUR_RX_DESC(sc);
1297 break;
1298 }
1299
1300 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO |
1301 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) {
1302
1303 rx_desc->length = 0;
1304 rx_desc->flags = (rx_desc->flags &
1305 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I;
1306
1307 if (sc->frame != NULL) {
1308 m_free(sc->frame);
1309 sc->frame = NULL;
1310 }
1311
1312 continue;
1313 }
1314
1315 /* Ok... process frame */
1316 i = TSEC_GET_CUR_RX_DESC_CNT(sc);
1317 m = rx_data[i].mbuf;
1318 m->m_len = rx_desc->length;
1319
1320 if (sc->frame != NULL) {
1321 if ((flags & TSEC_RXBD_L) != 0)
1322 m->m_len -= m_length(sc->frame, NULL);
1323
1324 m->m_flags &= ~M_PKTHDR;
1325 m_cat(sc->frame, m);
1326 } else {
1327 sc->frame = m;
1328 }
1329
1330 m = NULL;
1331
1332 if ((flags & TSEC_RXBD_L) != 0) {
1333 m = sc->frame;
1334 sc->frame = NULL;
1335 }
1336
1337 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map,
1338 &rx_data[i].mbuf, &rx_data[i].paddr)) {
1339 ifp->if_ierrors++;
1340 /*
1341 * We ran out of mbufs; didn't consume current
1342 * descriptor and have to return it to the queue.
1343 */
1344 TSEC_BACK_CUR_RX_DESC(sc);
1345 break;
1346 }
1347
1348 /* Attach new buffer to descriptor and clear flags */
1349 rx_desc->bufptr = rx_data[i].paddr;
1350 rx_desc->length = 0;
1351 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) |
1352 TSEC_RXBD_E | TSEC_RXBD_I;
1353
1354 if (m != NULL) {
1355 m->m_pkthdr.rcvif = ifp;
1356
1357 m_fixhdr(m);
1358 m_adj(m, -ETHER_CRC_LEN);
1359
1360 if (sc->is_etsec)
1361 tsec_offload_process_frame(sc, m);
1362
1363 TSEC_RECEIVE_UNLOCK(sc);
1364 (*ifp->if_input)(ifp, m);
1365 TSEC_RECEIVE_LOCK(sc);
1366 rx_npkts++;
1367 }
1368 }
1369
1370 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1371 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1372
1373 /*
1374 * Make sure TSEC receiver is not halted.
1375 *
1376 * Various conditions can stop the TSEC receiver, but not all are
1377 * signaled and handled by error interrupt, so make sure the receiver
1378 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when
1379 * halted, and is harmless if already running.
1380 */
1381 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT);
1382 return (rx_npkts);
1383}
1384
1385void
1386tsec_receive_intr(void *arg)
1387{
1388 struct tsec_softc *sc = arg;
1389
1390 TSEC_RECEIVE_LOCK(sc);
1391
1392#ifdef DEVICE_POLLING
1393 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1394 TSEC_RECEIVE_UNLOCK(sc);
1395 return;
1396 }
1397#endif
1398
1399 /* Confirm the interrupt was received by driver */
1400 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1401 tsec_receive_intr_locked(sc, -1);
1402
1403 TSEC_RECEIVE_UNLOCK(sc);
1404}
1405
1406static void
1407tsec_transmit_intr_locked(struct tsec_softc *sc)
1408{
1409 struct tsec_desc *tx_desc;
1410 struct ifnet *ifp;
1411 struct mbuf *m0;
1412 bus_dmamap_t *mapp;
1413 int send = 0;
1414
1415 TSEC_TRANSMIT_LOCK_ASSERT(sc);
1416
1417 ifp = sc->tsec_ifp;
1418
1419 /* Update collision statistics */
1420 ifp->if_collisions += TSEC_READ(sc, TSEC_REG_MON_TNCL);
1421
1422 /* Reset collision counters in hardware */
1423 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
1424 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
1425 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
1426 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
1427 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
1428
1429 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1430 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1431
1432 while (TSEC_CUR_DIFF_DIRTY_TX_DESC(sc)) {
1433 tx_desc = TSEC_GET_DIRTY_TX_DESC(sc);
1434 if (tx_desc->flags & TSEC_TXBD_R) {
1435 TSEC_BACK_DIRTY_TX_DESC(sc);
1436 break;
1437 }
1438
1439 if ((tx_desc->flags & TSEC_TXBD_L) == 0)
1440 continue;
1441
1442 /*
1443 * This is the last buf in this packet, so unmap and free it.
1444 */
1445 m0 = TSEC_GET_TX_MBUF(sc);
1446 mapp = TSEC_GET_TX_MAP(sc);
1447
1448 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp,
1449 BUS_DMASYNC_POSTWRITE);
1450 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
1451
1452 TSEC_FREE_TX_MAP(sc, mapp);
1453 m_freem(m0);
1454
1455 ifp->if_opackets++;
1456 send = 1;
1457 }
1458 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1459 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1460
1461 if (send) {
1462 /* Now send anything that was pending */
1463 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1464 tsec_start_locked(ifp);
1465
1466 /* Stop wathdog if all sent */
1467 if (TSEC_EMPTYQ_TX_MBUF(sc))
1468 sc->tsec_watchdog = 0;
1469 }
1470}
1471
1472void
1473tsec_transmit_intr(void *arg)
1474{
1475 struct tsec_softc *sc = arg;
1476
1477 TSEC_TRANSMIT_LOCK(sc);
1478
1479#ifdef DEVICE_POLLING
1480 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1481 TSEC_TRANSMIT_UNLOCK(sc);
1482 return;
1483 }
1484#endif
1485 /* Confirm the interrupt was received by driver */
1486 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF);
1487 tsec_transmit_intr_locked(sc);
1488
1489 TSEC_TRANSMIT_UNLOCK(sc);
1490}
1491
1492static void
1493tsec_error_intr_locked(struct tsec_softc *sc, int count)
1494{
1495 struct ifnet *ifp;
1496 uint32_t eflags;
1497
1498 TSEC_GLOBAL_LOCK_ASSERT(sc);
1499
1500 ifp = sc->tsec_ifp;
1501
1502 eflags = TSEC_READ(sc, TSEC_REG_IEVENT);
1503
1504 /* Clear events bits in hardware */
1505 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY |
1506 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT |
1507 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC |
1508 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN);
1509
1510 /* Check transmitter errors */
1511 if (eflags & TSEC_IEVENT_TXE) {
1512 ifp->if_oerrors++;
1513
1514 if (eflags & TSEC_IEVENT_LC)
1515 ifp->if_collisions++;
1516
1517 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
1518 }
1519
1520 /* Check receiver errors */
1521 if (eflags & TSEC_IEVENT_BSY) {
1522 ifp->if_ierrors++;
1523 ifp->if_iqdrops++;
1524
1525 /* Get data from RX buffers */
1526 tsec_receive_intr_locked(sc, count);
1527 }
1528
1529 if (ifp->if_flags & IFF_DEBUG)
1530 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n",
1531 eflags);
1532
1533 if (eflags & TSEC_IEVENT_EBERR) {
1534 if_printf(ifp, "System bus error occurred during"
1535 "DMA transaction (flags: 0x%x)\n", eflags);
1536 tsec_init_locked(sc);
1537 }
1538
1539 if (eflags & TSEC_IEVENT_BABT)
1540 ifp->if_oerrors++;
1541
1542 if (eflags & TSEC_IEVENT_BABR)
1543 ifp->if_ierrors++;
1544}
1545
1546void
1547tsec_error_intr(void *arg)
1548{
1549 struct tsec_softc *sc = arg;
1550
1551 TSEC_GLOBAL_LOCK(sc);
1552 tsec_error_intr_locked(sc, -1);
1553 TSEC_GLOBAL_UNLOCK(sc);
1554}
1555
1556int
1557tsec_miibus_readreg(device_t dev, int phy, int reg)
1558{
1559 struct tsec_softc *sc;
1560 uint32_t timeout;
1561
|
1564 sc = tsec0_sc;
| 1562 sc = device_get_softc(dev);
|
1565
| 1563
|
1566 TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1567 TSEC_WRITE(sc, TSEC_REG_MIIMCOM, 0);
1568 TSEC_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE);
| 1564 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1565 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCOM, 0);
1566 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE);
|
1569
1570 timeout = TSEC_READ_RETRY;
| 1567
1568 timeout = TSEC_READ_RETRY;
|
1571 while (--timeout && TSEC_READ(sc, TSEC_REG_MIIMIND) &
| 1569 while (--timeout && TSEC_READ(sc->phy_sc, TSEC_REG_MIIMIND) &
|
1572 (TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY))
1573 DELAY(TSEC_READ_DELAY);
1574
1575 if (timeout == 0)
1576 device_printf(dev, "Timeout while reading from PHY!\n");
1577
| 1570 (TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY))
1571 DELAY(TSEC_READ_DELAY);
1572
1573 if (timeout == 0)
1574 device_printf(dev, "Timeout while reading from PHY!\n");
1575
|
1578 return (TSEC_READ(sc, TSEC_REG_MIIMSTAT));
| 1576 return (TSEC_READ(sc->phy_sc, TSEC_REG_MIIMSTAT));
|
1579}
1580
1581int
1582tsec_miibus_writereg(device_t dev, int phy, int reg, int value)
1583{
1584 struct tsec_softc *sc;
1585 uint32_t timeout;
1586
| 1577}
1578
1579int
1580tsec_miibus_writereg(device_t dev, int phy, int reg, int value)
1581{
1582 struct tsec_softc *sc;
1583 uint32_t timeout;
1584
|
1587 sc = tsec0_sc;
| 1585 sc = device_get_softc(dev);
|
1588
| 1586
|
1589 TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1590 TSEC_WRITE(sc, TSEC_REG_MIIMCON, value);
| 1587 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1588 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCON, value);
|
1591
1592 timeout = TSEC_READ_RETRY;
| 1589
1590 timeout = TSEC_READ_RETRY;
|
1593 while (--timeout && (TSEC_READ(sc, TSEC_REG_MIIMIND) &
| 1591 while (--timeout && (TSEC_READ(sc->phy_sc, TSEC_REG_MIIMIND) &
|
1594 TSEC_MIIMIND_BUSY))
1595 DELAY(TSEC_READ_DELAY);
1596
1597 if (timeout == 0)
1598 device_printf(dev, "Timeout while writing to PHY!\n");
1599
1600 return (0);
1601}
1602
1603void
1604tsec_miibus_statchg(device_t dev)
1605{
1606 struct tsec_softc *sc;
1607 struct mii_data *mii;
1608 uint32_t ecntrl, id, tmp;
1609 int link;
1610
1611 sc = device_get_softc(dev);
1612 mii = sc->tsec_mii;
1613 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0);
1614
1615 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF;
1616
1617 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
1618 tmp |= TSEC_MACCFG2_FULLDUPLEX;
1619 else
1620 tmp &= ~TSEC_MACCFG2_FULLDUPLEX;
1621
1622 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1623 case IFM_1000_T:
1624 case IFM_1000_SX:
1625 tmp |= TSEC_MACCFG2_GMII;
1626 sc->tsec_link = link;
1627 break;
1628 case IFM_100_TX:
1629 case IFM_10_T:
1630 tmp |= TSEC_MACCFG2_MII;
1631 sc->tsec_link = link;
1632 break;
1633 case IFM_NONE:
1634 if (link)
1635 device_printf(dev, "No speed selected but link "
1636 "active!\n");
1637 sc->tsec_link = 0;
1638 return;
1639 default:
1640 sc->tsec_link = 0;
1641 device_printf(dev, "Unknown speed (%d), link %s!\n",
1642 IFM_SUBTYPE(mii->mii_media_active),
1643 ((link) ? "up" : "down"));
1644 return;
1645 }
1646 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp);
1647
1648 /* XXX kludge - use circumstantial evidence for reduced mode. */
1649 id = TSEC_READ(sc, TSEC_REG_ID2);
1650 if (id & 0xffff) {
1651 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M;
1652 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0;
1653 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl);
1654 }
1655}
1656
1657static void
1658tsec_add_sysctls(struct tsec_softc *sc)
1659{
1660 struct sysctl_ctx_list *ctx;
1661 struct sysctl_oid_list *children;
1662 struct sysctl_oid *tree;
1663
1664 ctx = device_get_sysctl_ctx(sc->dev);
1665 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
1666 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal",
1667 CTLFLAG_RD, 0, "TSEC Interrupts coalescing");
1668 children = SYSCTL_CHILDREN(tree);
1669
1670 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time",
1671 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_time,
1672 "I", "IC RX time threshold (0-65535)");
1673 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count",
1674 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_count,
1675 "I", "IC RX frame count threshold (0-255)");
1676
1677 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time",
1678 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_time,
1679 "I", "IC TX time threshold (0-65535)");
1680 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count",
1681 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_count,
1682 "I", "IC TX frame count threshold (0-255)");
1683}
1684
1685/*
1686 * With Interrupt Coalescing (IC) active, a transmit/receive frame
1687 * interrupt is raised either upon:
1688 *
1689 * - threshold-defined period of time elapsed, or
1690 * - threshold-defined number of frames is received/transmitted,
1691 * whichever occurs first.
1692 *
1693 * The following sysctls regulate IC behaviour (for TX/RX separately):
1694 *
1695 * dev.tsec.<unit>.int_coal.rx_time
1696 * dev.tsec.<unit>.int_coal.rx_count
1697 * dev.tsec.<unit>.int_coal.tx_time
1698 * dev.tsec.<unit>.int_coal.tx_count
1699 *
1700 * Values:
1701 *
1702 * - 0 for either time or count disables IC on the given TX/RX path
1703 *
1704 * - count: 1-255 (expresses frame count number; note that value of 1 is
1705 * effectively IC off)
1706 *
1707 * - time: 1-65535 (value corresponds to a real time period and is
1708 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer
1709 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps,
1710 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the
1711 * TSEC reference manual.
1712 */
1713static int
1714tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS)
1715{
1716 int error;
1717 uint32_t time;
1718 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1719
1720 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time;
1721
1722 error = sysctl_handle_int(oidp, &time, 0, req);
1723 if (error != 0)
1724 return (error);
1725
1726 if (time > 65535)
1727 return (EINVAL);
1728
1729 TSEC_IC_LOCK(sc);
1730 if (arg2 == TSEC_IC_RX) {
1731 sc->rx_ic_time = time;
1732 tsec_set_rxic(sc);
1733 } else {
1734 sc->tx_ic_time = time;
1735 tsec_set_txic(sc);
1736 }
1737 TSEC_IC_UNLOCK(sc);
1738
1739 return (0);
1740}
1741
1742static int
1743tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS)
1744{
1745 int error;
1746 uint32_t count;
1747 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1748
1749 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count;
1750
1751 error = sysctl_handle_int(oidp, &count, 0, req);
1752 if (error != 0)
1753 return (error);
1754
1755 if (count > 255)
1756 return (EINVAL);
1757
1758 TSEC_IC_LOCK(sc);
1759 if (arg2 == TSEC_IC_RX) {
1760 sc->rx_ic_count = count;
1761 tsec_set_rxic(sc);
1762 } else {
1763 sc->tx_ic_count = count;
1764 tsec_set_txic(sc);
1765 }
1766 TSEC_IC_UNLOCK(sc);
1767
1768 return (0);
1769}
1770
1771static void
1772tsec_set_rxic(struct tsec_softc *sc)
1773{
1774 uint32_t rxic_val;
1775
1776 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0)
1777 /* Disable RX IC */
1778 rxic_val = 0;
1779 else {
1780 rxic_val = 0x80000000;
1781 rxic_val |= (sc->rx_ic_count << 21);
1782 rxic_val |= sc->rx_ic_time;
1783 }
1784
1785 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val);
1786}
1787
1788static void
1789tsec_set_txic(struct tsec_softc *sc)
1790{
1791 uint32_t txic_val;
1792
1793 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0)
1794 /* Disable TX IC */
1795 txic_val = 0;
1796 else {
1797 txic_val = 0x80000000;
1798 txic_val |= (sc->tx_ic_count << 21);
1799 txic_val |= sc->tx_ic_time;
1800 }
1801
1802 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val);
1803}
1804
1805static void
1806tsec_offload_setup(struct tsec_softc *sc)
1807{
1808 struct ifnet *ifp = sc->tsec_ifp;
1809 uint32_t reg;
1810
1811 TSEC_GLOBAL_LOCK_ASSERT(sc);
1812
1813 reg = TSEC_READ(sc, TSEC_REG_TCTRL);
1814 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN;
1815
1816 if (ifp->if_capenable & IFCAP_TXCSUM)
1817 ifp->if_hwassist = TSEC_CHECKSUM_FEATURES;
1818 else
1819 ifp->if_hwassist = 0;
1820
1821 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg);
1822
1823 reg = TSEC_READ(sc, TSEC_REG_RCTRL);
1824 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP);
1825 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX;
1826
1827 if (ifp->if_capenable & IFCAP_RXCSUM)
1828 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN |
1829 TSEC_RCTRL_PRSDEP_PARSE_L234;
1830
1831 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg);
1832}
1833
1834
1835static void
1836tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m)
1837{
1838 struct tsec_rx_fcb rx_fcb;
1839 int csum_flags = 0;
1840 int protocol, flags;
1841
1842 TSEC_RECEIVE_LOCK_ASSERT(sc);
1843
1844 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb));
1845 flags = rx_fcb.flags;
1846 protocol = rx_fcb.protocol;
1847
1848 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) {
1849 csum_flags |= CSUM_IP_CHECKED;
1850
1851 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0)
1852 csum_flags |= CSUM_IP_VALID;
1853 }
1854
1855 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) &&
1856 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) &&
1857 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) {
1858
1859 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1860 m->m_pkthdr.csum_data = 0xFFFF;
1861 }
1862
1863 m->m_pkthdr.csum_flags = csum_flags;
1864
1865 if (flags & TSEC_RX_FCB_VLAN) {
1866 m->m_pkthdr.ether_vtag = rx_fcb.vlan;
1867 m->m_flags |= M_VLANTAG;
1868 }
1869
1870 m_adj(m, sizeof(struct tsec_rx_fcb));
1871}
1872
1873static void
1874tsec_setup_multicast(struct tsec_softc *sc)
1875{
1876 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
1877 struct ifnet *ifp = sc->tsec_ifp;
1878 struct ifmultiaddr *ifma;
1879 uint32_t h;
1880 int i;
1881
1882 TSEC_GLOBAL_LOCK_ASSERT(sc);
1883
1884 if (ifp->if_flags & IFF_ALLMULTI) {
1885 for (i = 0; i < 8; i++)
1886 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF);
1887
1888 return;
1889 }
1890
1891 if_maddr_rlock(ifp);
1892 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1893
1894 if (ifma->ifma_addr->sa_family != AF_LINK)
1895 continue;
1896
1897 h = (ether_crc32_be(LLADDR((struct sockaddr_dl *)
1898 ifma->ifma_addr), ETHER_ADDR_LEN) >> 24) & 0xFF;
1899
1900 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F));
1901 }
1902 if_maddr_runlock(ifp);
1903
1904 for (i = 0; i < 8; i++)
1905 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]);
1906}
1907
1908static int
1909tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu)
1910{
1911
1912 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
1913
1914 TSEC_GLOBAL_LOCK_ASSERT(sc);
1915
1916 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) {
1917 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu);
1918 return (mtu);
1919 }
1920
1921 return (0);
1922}
| 1592 TSEC_MIIMIND_BUSY))
1593 DELAY(TSEC_READ_DELAY);
1594
1595 if (timeout == 0)
1596 device_printf(dev, "Timeout while writing to PHY!\n");
1597
1598 return (0);
1599}
1600
1601void
1602tsec_miibus_statchg(device_t dev)
1603{
1604 struct tsec_softc *sc;
1605 struct mii_data *mii;
1606 uint32_t ecntrl, id, tmp;
1607 int link;
1608
1609 sc = device_get_softc(dev);
1610 mii = sc->tsec_mii;
1611 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0);
1612
1613 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF;
1614
1615 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
1616 tmp |= TSEC_MACCFG2_FULLDUPLEX;
1617 else
1618 tmp &= ~TSEC_MACCFG2_FULLDUPLEX;
1619
1620 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1621 case IFM_1000_T:
1622 case IFM_1000_SX:
1623 tmp |= TSEC_MACCFG2_GMII;
1624 sc->tsec_link = link;
1625 break;
1626 case IFM_100_TX:
1627 case IFM_10_T:
1628 tmp |= TSEC_MACCFG2_MII;
1629 sc->tsec_link = link;
1630 break;
1631 case IFM_NONE:
1632 if (link)
1633 device_printf(dev, "No speed selected but link "
1634 "active!\n");
1635 sc->tsec_link = 0;
1636 return;
1637 default:
1638 sc->tsec_link = 0;
1639 device_printf(dev, "Unknown speed (%d), link %s!\n",
1640 IFM_SUBTYPE(mii->mii_media_active),
1641 ((link) ? "up" : "down"));
1642 return;
1643 }
1644 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp);
1645
1646 /* XXX kludge - use circumstantial evidence for reduced mode. */
1647 id = TSEC_READ(sc, TSEC_REG_ID2);
1648 if (id & 0xffff) {
1649 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M;
1650 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0;
1651 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl);
1652 }
1653}
1654
1655static void
1656tsec_add_sysctls(struct tsec_softc *sc)
1657{
1658 struct sysctl_ctx_list *ctx;
1659 struct sysctl_oid_list *children;
1660 struct sysctl_oid *tree;
1661
1662 ctx = device_get_sysctl_ctx(sc->dev);
1663 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
1664 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal",
1665 CTLFLAG_RD, 0, "TSEC Interrupts coalescing");
1666 children = SYSCTL_CHILDREN(tree);
1667
1668 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time",
1669 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_time,
1670 "I", "IC RX time threshold (0-65535)");
1671 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count",
1672 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_count,
1673 "I", "IC RX frame count threshold (0-255)");
1674
1675 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time",
1676 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_time,
1677 "I", "IC TX time threshold (0-65535)");
1678 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count",
1679 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_count,
1680 "I", "IC TX frame count threshold (0-255)");
1681}
1682
1683/*
1684 * With Interrupt Coalescing (IC) active, a transmit/receive frame
1685 * interrupt is raised either upon:
1686 *
1687 * - threshold-defined period of time elapsed, or
1688 * - threshold-defined number of frames is received/transmitted,
1689 * whichever occurs first.
1690 *
1691 * The following sysctls regulate IC behaviour (for TX/RX separately):
1692 *
1693 * dev.tsec.<unit>.int_coal.rx_time
1694 * dev.tsec.<unit>.int_coal.rx_count
1695 * dev.tsec.<unit>.int_coal.tx_time
1696 * dev.tsec.<unit>.int_coal.tx_count
1697 *
1698 * Values:
1699 *
1700 * - 0 for either time or count disables IC on the given TX/RX path
1701 *
1702 * - count: 1-255 (expresses frame count number; note that value of 1 is
1703 * effectively IC off)
1704 *
1705 * - time: 1-65535 (value corresponds to a real time period and is
1706 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer
1707 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps,
1708 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the
1709 * TSEC reference manual.
1710 */
1711static int
1712tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS)
1713{
1714 int error;
1715 uint32_t time;
1716 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1717
1718 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time;
1719
1720 error = sysctl_handle_int(oidp, &time, 0, req);
1721 if (error != 0)
1722 return (error);
1723
1724 if (time > 65535)
1725 return (EINVAL);
1726
1727 TSEC_IC_LOCK(sc);
1728 if (arg2 == TSEC_IC_RX) {
1729 sc->rx_ic_time = time;
1730 tsec_set_rxic(sc);
1731 } else {
1732 sc->tx_ic_time = time;
1733 tsec_set_txic(sc);
1734 }
1735 TSEC_IC_UNLOCK(sc);
1736
1737 return (0);
1738}
1739
1740static int
1741tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS)
1742{
1743 int error;
1744 uint32_t count;
1745 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1746
1747 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count;
1748
1749 error = sysctl_handle_int(oidp, &count, 0, req);
1750 if (error != 0)
1751 return (error);
1752
1753 if (count > 255)
1754 return (EINVAL);
1755
1756 TSEC_IC_LOCK(sc);
1757 if (arg2 == TSEC_IC_RX) {
1758 sc->rx_ic_count = count;
1759 tsec_set_rxic(sc);
1760 } else {
1761 sc->tx_ic_count = count;
1762 tsec_set_txic(sc);
1763 }
1764 TSEC_IC_UNLOCK(sc);
1765
1766 return (0);
1767}
1768
1769static void
1770tsec_set_rxic(struct tsec_softc *sc)
1771{
1772 uint32_t rxic_val;
1773
1774 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0)
1775 /* Disable RX IC */
1776 rxic_val = 0;
1777 else {
1778 rxic_val = 0x80000000;
1779 rxic_val |= (sc->rx_ic_count << 21);
1780 rxic_val |= sc->rx_ic_time;
1781 }
1782
1783 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val);
1784}
1785
1786static void
1787tsec_set_txic(struct tsec_softc *sc)
1788{
1789 uint32_t txic_val;
1790
1791 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0)
1792 /* Disable TX IC */
1793 txic_val = 0;
1794 else {
1795 txic_val = 0x80000000;
1796 txic_val |= (sc->tx_ic_count << 21);
1797 txic_val |= sc->tx_ic_time;
1798 }
1799
1800 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val);
1801}
1802
1803static void
1804tsec_offload_setup(struct tsec_softc *sc)
1805{
1806 struct ifnet *ifp = sc->tsec_ifp;
1807 uint32_t reg;
1808
1809 TSEC_GLOBAL_LOCK_ASSERT(sc);
1810
1811 reg = TSEC_READ(sc, TSEC_REG_TCTRL);
1812 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN;
1813
1814 if (ifp->if_capenable & IFCAP_TXCSUM)
1815 ifp->if_hwassist = TSEC_CHECKSUM_FEATURES;
1816 else
1817 ifp->if_hwassist = 0;
1818
1819 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg);
1820
1821 reg = TSEC_READ(sc, TSEC_REG_RCTRL);
1822 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP);
1823 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX;
1824
1825 if (ifp->if_capenable & IFCAP_RXCSUM)
1826 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN |
1827 TSEC_RCTRL_PRSDEP_PARSE_L234;
1828
1829 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg);
1830}
1831
1832
1833static void
1834tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m)
1835{
1836 struct tsec_rx_fcb rx_fcb;
1837 int csum_flags = 0;
1838 int protocol, flags;
1839
1840 TSEC_RECEIVE_LOCK_ASSERT(sc);
1841
1842 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb));
1843 flags = rx_fcb.flags;
1844 protocol = rx_fcb.protocol;
1845
1846 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) {
1847 csum_flags |= CSUM_IP_CHECKED;
1848
1849 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0)
1850 csum_flags |= CSUM_IP_VALID;
1851 }
1852
1853 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) &&
1854 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) &&
1855 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) {
1856
1857 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1858 m->m_pkthdr.csum_data = 0xFFFF;
1859 }
1860
1861 m->m_pkthdr.csum_flags = csum_flags;
1862
1863 if (flags & TSEC_RX_FCB_VLAN) {
1864 m->m_pkthdr.ether_vtag = rx_fcb.vlan;
1865 m->m_flags |= M_VLANTAG;
1866 }
1867
1868 m_adj(m, sizeof(struct tsec_rx_fcb));
1869}
1870
1871static void
1872tsec_setup_multicast(struct tsec_softc *sc)
1873{
1874 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
1875 struct ifnet *ifp = sc->tsec_ifp;
1876 struct ifmultiaddr *ifma;
1877 uint32_t h;
1878 int i;
1879
1880 TSEC_GLOBAL_LOCK_ASSERT(sc);
1881
1882 if (ifp->if_flags & IFF_ALLMULTI) {
1883 for (i = 0; i < 8; i++)
1884 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF);
1885
1886 return;
1887 }
1888
1889 if_maddr_rlock(ifp);
1890 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1891
1892 if (ifma->ifma_addr->sa_family != AF_LINK)
1893 continue;
1894
1895 h = (ether_crc32_be(LLADDR((struct sockaddr_dl *)
1896 ifma->ifma_addr), ETHER_ADDR_LEN) >> 24) & 0xFF;
1897
1898 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F));
1899 }
1900 if_maddr_runlock(ifp);
1901
1902 for (i = 0; i < 8; i++)
1903 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]);
1904}
1905
1906static int
1907tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu)
1908{
1909
1910 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
1911
1912 TSEC_GLOBAL_LOCK_ASSERT(sc);
1913
1914 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) {
1915 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu);
1916 return (mtu);
1917 }
1918
1919 return (0);
1920}
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