1/*-
2 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski
3 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27/*
28 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver.
29 */
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/tsec/if_tsec.c 232518 2012-03-04 19:22:52Z raj $");
32
33#ifdef HAVE_KERNEL_OPTION_HEADERS
34#include "opt_device_polling.h"
35#endif
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/bus.h>

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101static void tsec_transmit_intr_locked(struct tsec_softc *sc);
102static void tsec_error_intr_locked(struct tsec_softc *sc, int count);
103static void tsec_offload_setup(struct tsec_softc *sc);
104static void tsec_offload_process_frame(struct tsec_softc *sc,
105 struct mbuf *m);
106static void tsec_setup_multicast(struct tsec_softc *sc);
107static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu);
108
109devclass_t tsec_devclass;
110DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0);
111MODULE_DEPEND(tsec, ether, 1, 1, 1);
112MODULE_DEPEND(tsec, miibus, 1, 1, 1);
113
114int
115tsec_attach(struct tsec_softc *sc)
116{

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399
400 /*
401 * Step 5: Assign a Physical address to the TBI so as to not conflict
402 * with the external PHY physical address
403 */
404 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5);
405
406 /* Step 6: Reset the management interface */
407 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT);
408
409 /* Step 7: Setup the MII Mgmt clock speed */
410 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28);
411
412 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */
413 timeout = TSEC_READ_RETRY;
414 while (--timeout && (TSEC_READ(sc->phy_sc, TSEC_REG_MIIMIND) &
415 TSEC_MIIMIND_BUSY))
416 DELAY(TSEC_READ_DELAY);
417 if (timeout == 0) {
418 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n");
419 return;
420 }
421
422 /* Step 9: Setup the MII Mgmt */

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1554}
1555
1556int
1557tsec_miibus_readreg(device_t dev, int phy, int reg)
1558{
1559 struct tsec_softc *sc;
1560 uint32_t timeout;
1561
1562 sc = device_get_softc(dev);
1563
1564 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1565 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCOM, 0);
1566 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE);
1567
1568 timeout = TSEC_READ_RETRY;
1569 while (--timeout && TSEC_READ(sc->phy_sc, TSEC_REG_MIIMIND) &
1570 (TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY))
1571 DELAY(TSEC_READ_DELAY);
1572
1573 if (timeout == 0)
1574 device_printf(dev, "Timeout while reading from PHY!\n");
1575
1576 return (TSEC_READ(sc->phy_sc, TSEC_REG_MIIMSTAT));
1577}
1578
1579int
1580tsec_miibus_writereg(device_t dev, int phy, int reg, int value)
1581{
1582 struct tsec_softc *sc;
1583 uint32_t timeout;
1584
1585 sc = device_get_softc(dev);
1586
1587 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1588 TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCON, value);
1589
1590 timeout = TSEC_READ_RETRY;
1591 while (--timeout && (TSEC_READ(sc->phy_sc, TSEC_REG_MIIMIND) &
1592 TSEC_MIIMIND_BUSY))
1593 DELAY(TSEC_READ_DELAY);
1594
1595 if (timeout == 0)
1596 device_printf(dev, "Timeout while writing to PHY!\n");
1597
1598 return (0);
1599}

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