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if_tl.c (46561) if_tl.c (46568)
1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $Id: if_tl.c,v 1.29 1999/04/24 20:14:01 peter Exp $
32 * $Id: if_tl.c,v 1.30 1999/05/06 15:32:49 wpaul Exp $
33 */
34
35/*
36 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
37 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
38 * the National Semiconductor DP83840A physical interface and the
39 * Microchip Technology 24Cxx series serial EEPROM.
40 *
41 * Written using the following four documents:
42 *
43 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com)
44 * National Semiconductor DP83840A data sheet (www.national.com)
45 * Microchip Technology 24C02C data sheet (www.microchip.com)
46 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com)
47 *
48 * Written by Bill Paul <wpaul@ctr.columbia.edu>
49 * Electrical Engineering Department
50 * Columbia University, New York City
51 */
52
53/*
54 * Some notes about the ThunderLAN:
55 *
56 * The ThunderLAN controller is a single chip containing PCI controller
57 * logic, approximately 3K of on-board SRAM, a LAN controller, and media
58 * independent interface (MII) bus. The MII allows the ThunderLAN chip to
59 * control up to 32 different physical interfaces (PHYs). The ThunderLAN
60 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller
61 * to act as a complete ethernet interface.
62 *
63 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards
64 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec
65 * in full or half duplex. Some of the Compaq Deskpro machines use a
66 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters
67 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in
68 * concert with the ThunderLAN's internal PHY to provide full 10/100
69 * support. This is cheaper than using a standalone external PHY for both
70 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste.
71 * A serial EEPROM is also attached to the ThunderLAN chip to provide
72 * power-up default register settings and for storing the adapter's
73 * station address. Although not supported by this driver, the ThunderLAN
74 * chip can also be connected to token ring PHYs.
75 *
76 * The ThunderLAN has a set of registers which can be used to issue
77 * commands, acknowledge interrupts, and to manipulate other internal
78 * registers on its DIO bus. The primary registers can be accessed
79 * using either programmed I/O (inb/outb) or via PCI memory mapping,
80 * depending on how the card is configured during the PCI probing
81 * phase. It is even possible to have both PIO and memory mapped
82 * access turned on at the same time.
83 *
84 * Frame reception and transmission with the ThunderLAN chip is done
85 * using frame 'lists.' A list structure looks more or less like this:
86 *
87 * struct tl_frag {
88 * u_int32_t fragment_address;
89 * u_int32_t fragment_size;
90 * };
91 * struct tl_list {
92 * u_int32_t forward_pointer;
93 * u_int16_t cstat;
94 * u_int16_t frame_size;
95 * struct tl_frag fragments[10];
96 * };
97 *
98 * The forward pointer in the list header can be either a 0 or the address
99 * of another list, which allows several lists to be linked together. Each
100 * list contains up to 10 fragment descriptors. This means the chip allows
101 * ethernet frames to be broken up into up to 10 chunks for transfer to
102 * and from the SRAM. Note that the forward pointer and fragment buffer
103 * addresses are physical memory addresses, not virtual. Note also that
104 * a single ethernet frame can not span lists: if the host wants to
105 * transmit a frame and the frame data is split up over more than 10
106 * buffers, the frame has to collapsed before it can be transmitted.
107 *
108 * To receive frames, the driver sets up a number of lists and populates
109 * the fragment descriptors, then it sends an RX GO command to the chip.
110 * When a frame is received, the chip will DMA it into the memory regions
111 * specified by the fragment descriptors and then trigger an RX 'end of
112 * frame interrupt' when done. The driver may choose to use only one
113 * fragment per list; this may result is slighltly less efficient use
114 * of memory in exchange for improving performance.
115 *
116 * To transmit frames, the driver again sets up lists and fragment
117 * descriptors, only this time the buffers contain frame data that
118 * is to be DMA'ed into the chip instead of out of it. Once the chip
119 * has transfered the data into its on-board SRAM, it will trigger a
120 * TX 'end of frame' interrupt. It will also generate an 'end of channel'
121 * interrupt when it reaches the end of the list.
122 */
123
124/*
125 * Some notes about this driver:
126 *
127 * The ThunderLAN chip provides a couple of different ways to organize
128 * reception, transmission and interrupt handling. The simplest approach
129 * is to use one list each for transmission and reception. In this mode,
130 * the ThunderLAN will generate two interrupts for every received frame
131 * (one RX EOF and one RX EOC) and two for each transmitted frame (one
132 * TX EOF and one TX EOC). This may make the driver simpler but it hurts
133 * performance to have to handle so many interrupts.
134 *
135 * Initially I wanted to create a circular list of receive buffers so
136 * that the ThunderLAN chip would think there was an infinitely long
137 * receive channel and never deliver an RXEOC interrupt. However this
138 * doesn't work correctly under heavy load: while the manual says the
139 * chip will trigger an RXEOF interrupt each time a frame is copied into
140 * memory, you can't count on the chip waiting around for you to acknowledge
141 * the interrupt before it starts trying to DMA the next frame. The result
142 * is that the chip might traverse the entire circular list and then wrap
143 * around before you have a chance to do anything about it. Consequently,
144 * the receive list is terminated (with a 0 in the forward pointer in the
145 * last element). Each time an RXEOF interrupt arrives, the used list
146 * is shifted to the end of the list. This gives the appearance of an
147 * infinitely large RX chain so long as the driver doesn't fall behind
148 * the chip and allow all of the lists to be filled up.
149 *
150 * If all the lists are filled, the adapter will deliver an RX 'end of
151 * channel' interrupt when it hits the 0 forward pointer at the end of
152 * the chain. The RXEOC handler then cleans out the RX chain and resets
153 * the list head pointer in the ch_parm register and restarts the receiver.
154 *
155 * For frame transmission, it is possible to program the ThunderLAN's
156 * transmit interrupt threshold so that the chip can acknowledge multiple
157 * lists with only a single TX EOF interrupt. This allows the driver to
158 * queue several frames in one shot, and only have to handle a total
159 * two interrupts (one TX EOF and one TX EOC) no matter how many frames
160 * are transmitted. Frame transmission is done directly out of the
161 * mbufs passed to the tl_start() routine via the interface send queue.
162 * The driver simply sets up the fragment descriptors in the transmit
163 * lists to point to the mbuf data regions and sends a TX GO command.
164 *
165 * Note that since the RX and TX lists themselves are always used
166 * only by the driver, the are malloc()ed once at driver initialization
167 * time and never free()ed.
168 *
169 * Also, in order to remain as platform independent as possible, this
170 * driver uses memory mapped register access to manipulate the card
171 * as opposed to programmed I/O. This avoids the use of the inb/outb
172 * (and related) instructions which are specific to the i386 platform.
173 *
174 * Using these techniques, this driver achieves very high performance
175 * by minimizing the amount of interrupts generated during large
176 * transfers and by completely avoiding buffer copies. Frame transfer
177 * to and from the ThunderLAN chip is performed entirely by the chip
178 * itself thereby reducing the load on the host CPU.
179 */
180
181#include "bpfilter.h"
182
183#include <sys/param.h>
184#include <sys/systm.h>
185#include <sys/sockio.h>
186#include <sys/mbuf.h>
187#include <sys/malloc.h>
188#include <sys/kernel.h>
189#include <sys/socket.h>
190
191#include <net/if.h>
192#include <net/if_arp.h>
193#include <net/ethernet.h>
194#include <net/if_dl.h>
195#include <net/if_media.h>
196
197#if NBPFILTER > 0
198#include <net/bpf.h>
199#endif
200
201#include <vm/vm.h> /* for vtophys */
202#include <vm/pmap.h> /* for vtophys */
203#include <machine/clock.h> /* for DELAY */
204#include <machine/bus_memio.h>
205#include <machine/bus_pio.h>
206#include <machine/bus.h>
207
208#include <pci/pcireg.h>
209#include <pci/pcivar.h>
210
211/*
212 * Default to using PIO register access mode to pacify certain
213 * laptop docking stations with built-in ThunderLAN chips that
214 * don't seem to handle memory mapped mode properly.
215 */
216#define TL_USEIOSPACE
217
218/* #define TL_BACKGROUND_AUTONEG */
219
220#include <pci/if_tlreg.h>
221
222#if !defined(lint)
223static const char rcsid[] =
33 */
34
35/*
36 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
37 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
38 * the National Semiconductor DP83840A physical interface and the
39 * Microchip Technology 24Cxx series serial EEPROM.
40 *
41 * Written using the following four documents:
42 *
43 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com)
44 * National Semiconductor DP83840A data sheet (www.national.com)
45 * Microchip Technology 24C02C data sheet (www.microchip.com)
46 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com)
47 *
48 * Written by Bill Paul <wpaul@ctr.columbia.edu>
49 * Electrical Engineering Department
50 * Columbia University, New York City
51 */
52
53/*
54 * Some notes about the ThunderLAN:
55 *
56 * The ThunderLAN controller is a single chip containing PCI controller
57 * logic, approximately 3K of on-board SRAM, a LAN controller, and media
58 * independent interface (MII) bus. The MII allows the ThunderLAN chip to
59 * control up to 32 different physical interfaces (PHYs). The ThunderLAN
60 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller
61 * to act as a complete ethernet interface.
62 *
63 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards
64 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec
65 * in full or half duplex. Some of the Compaq Deskpro machines use a
66 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters
67 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in
68 * concert with the ThunderLAN's internal PHY to provide full 10/100
69 * support. This is cheaper than using a standalone external PHY for both
70 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste.
71 * A serial EEPROM is also attached to the ThunderLAN chip to provide
72 * power-up default register settings and for storing the adapter's
73 * station address. Although not supported by this driver, the ThunderLAN
74 * chip can also be connected to token ring PHYs.
75 *
76 * The ThunderLAN has a set of registers which can be used to issue
77 * commands, acknowledge interrupts, and to manipulate other internal
78 * registers on its DIO bus. The primary registers can be accessed
79 * using either programmed I/O (inb/outb) or via PCI memory mapping,
80 * depending on how the card is configured during the PCI probing
81 * phase. It is even possible to have both PIO and memory mapped
82 * access turned on at the same time.
83 *
84 * Frame reception and transmission with the ThunderLAN chip is done
85 * using frame 'lists.' A list structure looks more or less like this:
86 *
87 * struct tl_frag {
88 * u_int32_t fragment_address;
89 * u_int32_t fragment_size;
90 * };
91 * struct tl_list {
92 * u_int32_t forward_pointer;
93 * u_int16_t cstat;
94 * u_int16_t frame_size;
95 * struct tl_frag fragments[10];
96 * };
97 *
98 * The forward pointer in the list header can be either a 0 or the address
99 * of another list, which allows several lists to be linked together. Each
100 * list contains up to 10 fragment descriptors. This means the chip allows
101 * ethernet frames to be broken up into up to 10 chunks for transfer to
102 * and from the SRAM. Note that the forward pointer and fragment buffer
103 * addresses are physical memory addresses, not virtual. Note also that
104 * a single ethernet frame can not span lists: if the host wants to
105 * transmit a frame and the frame data is split up over more than 10
106 * buffers, the frame has to collapsed before it can be transmitted.
107 *
108 * To receive frames, the driver sets up a number of lists and populates
109 * the fragment descriptors, then it sends an RX GO command to the chip.
110 * When a frame is received, the chip will DMA it into the memory regions
111 * specified by the fragment descriptors and then trigger an RX 'end of
112 * frame interrupt' when done. The driver may choose to use only one
113 * fragment per list; this may result is slighltly less efficient use
114 * of memory in exchange for improving performance.
115 *
116 * To transmit frames, the driver again sets up lists and fragment
117 * descriptors, only this time the buffers contain frame data that
118 * is to be DMA'ed into the chip instead of out of it. Once the chip
119 * has transfered the data into its on-board SRAM, it will trigger a
120 * TX 'end of frame' interrupt. It will also generate an 'end of channel'
121 * interrupt when it reaches the end of the list.
122 */
123
124/*
125 * Some notes about this driver:
126 *
127 * The ThunderLAN chip provides a couple of different ways to organize
128 * reception, transmission and interrupt handling. The simplest approach
129 * is to use one list each for transmission and reception. In this mode,
130 * the ThunderLAN will generate two interrupts for every received frame
131 * (one RX EOF and one RX EOC) and two for each transmitted frame (one
132 * TX EOF and one TX EOC). This may make the driver simpler but it hurts
133 * performance to have to handle so many interrupts.
134 *
135 * Initially I wanted to create a circular list of receive buffers so
136 * that the ThunderLAN chip would think there was an infinitely long
137 * receive channel and never deliver an RXEOC interrupt. However this
138 * doesn't work correctly under heavy load: while the manual says the
139 * chip will trigger an RXEOF interrupt each time a frame is copied into
140 * memory, you can't count on the chip waiting around for you to acknowledge
141 * the interrupt before it starts trying to DMA the next frame. The result
142 * is that the chip might traverse the entire circular list and then wrap
143 * around before you have a chance to do anything about it. Consequently,
144 * the receive list is terminated (with a 0 in the forward pointer in the
145 * last element). Each time an RXEOF interrupt arrives, the used list
146 * is shifted to the end of the list. This gives the appearance of an
147 * infinitely large RX chain so long as the driver doesn't fall behind
148 * the chip and allow all of the lists to be filled up.
149 *
150 * If all the lists are filled, the adapter will deliver an RX 'end of
151 * channel' interrupt when it hits the 0 forward pointer at the end of
152 * the chain. The RXEOC handler then cleans out the RX chain and resets
153 * the list head pointer in the ch_parm register and restarts the receiver.
154 *
155 * For frame transmission, it is possible to program the ThunderLAN's
156 * transmit interrupt threshold so that the chip can acknowledge multiple
157 * lists with only a single TX EOF interrupt. This allows the driver to
158 * queue several frames in one shot, and only have to handle a total
159 * two interrupts (one TX EOF and one TX EOC) no matter how many frames
160 * are transmitted. Frame transmission is done directly out of the
161 * mbufs passed to the tl_start() routine via the interface send queue.
162 * The driver simply sets up the fragment descriptors in the transmit
163 * lists to point to the mbuf data regions and sends a TX GO command.
164 *
165 * Note that since the RX and TX lists themselves are always used
166 * only by the driver, the are malloc()ed once at driver initialization
167 * time and never free()ed.
168 *
169 * Also, in order to remain as platform independent as possible, this
170 * driver uses memory mapped register access to manipulate the card
171 * as opposed to programmed I/O. This avoids the use of the inb/outb
172 * (and related) instructions which are specific to the i386 platform.
173 *
174 * Using these techniques, this driver achieves very high performance
175 * by minimizing the amount of interrupts generated during large
176 * transfers and by completely avoiding buffer copies. Frame transfer
177 * to and from the ThunderLAN chip is performed entirely by the chip
178 * itself thereby reducing the load on the host CPU.
179 */
180
181#include "bpfilter.h"
182
183#include <sys/param.h>
184#include <sys/systm.h>
185#include <sys/sockio.h>
186#include <sys/mbuf.h>
187#include <sys/malloc.h>
188#include <sys/kernel.h>
189#include <sys/socket.h>
190
191#include <net/if.h>
192#include <net/if_arp.h>
193#include <net/ethernet.h>
194#include <net/if_dl.h>
195#include <net/if_media.h>
196
197#if NBPFILTER > 0
198#include <net/bpf.h>
199#endif
200
201#include <vm/vm.h> /* for vtophys */
202#include <vm/pmap.h> /* for vtophys */
203#include <machine/clock.h> /* for DELAY */
204#include <machine/bus_memio.h>
205#include <machine/bus_pio.h>
206#include <machine/bus.h>
207
208#include <pci/pcireg.h>
209#include <pci/pcivar.h>
210
211/*
212 * Default to using PIO register access mode to pacify certain
213 * laptop docking stations with built-in ThunderLAN chips that
214 * don't seem to handle memory mapped mode properly.
215 */
216#define TL_USEIOSPACE
217
218/* #define TL_BACKGROUND_AUTONEG */
219
220#include <pci/if_tlreg.h>
221
222#if !defined(lint)
223static const char rcsid[] =
224 "$Id: if_tl.c,v 1.29 1999/04/24 20:14:01 peter Exp $";
224 "$Id: if_tl.c,v 1.30 1999/05/06 15:32:49 wpaul Exp $";
225#endif
226
227/*
228 * Various supported device vendors/types and their names.
229 */
230
231static struct tl_type tl_devs[] = {
232 { TI_VENDORID, TI_DEVICEID_THUNDERLAN,
233 "Texas Instruments ThunderLAN" },
234 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
235 "Compaq Netelligent 10" },
236 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
237 "Compaq Netelligent 10/100" },
238 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
239 "Compaq Netelligent 10/100 Proliant" },
240 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL,
241 "Compaq Netelligent 10/100 Dual Port" },
242 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED,
243 "Compaq NetFlex-3/P Integrated" },
244 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P,
245 "Compaq NetFlex-3/P" },
246 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC,
247 "Compaq NetFlex 3/P w/ BNC" },
248 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED,
249 "Compaq Netelligent 10/100 TX Embedded UTP" },
250 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX,
251 "Compaq Netelligent 10 T/2 PCI UTP/Coax" },
252 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP,
253 "Compaq Netelligent 10/100 TX UTP" },
254 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183,
255 "Olicom OC-2183/2185" },
256 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325,
257 "Olicom OC-2325" },
258 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326,
259 "Olicom OC-2326 10/100 TX UTP" },
260 { 0, 0, NULL }
261};
262
263/*
264 * Various supported PHY vendors/types and their names. Note that
265 * this driver will work with pretty much any MII-compliant PHY,
266 * so failure to positively identify the chip is not a fatal error.
267 */
268
269static struct tl_type tl_phys[] = {
270 { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" },
271 { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" },
272 { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"},
273 { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" },
274 { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" },
275 { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" },
276 { 0, 0, "<MII-compliant physical interface>" }
277};
278
279static unsigned long tl_count;
280
281static const char *tl_probe __P((pcici_t, pcidi_t));
282static void tl_attach __P((pcici_t, int));
283static int tl_attach_phy __P((struct tl_softc *));
284static int tl_intvec_rxeoc __P((void *, u_int32_t));
285static int tl_intvec_txeoc __P((void *, u_int32_t));
286static int tl_intvec_txeof __P((void *, u_int32_t));
287static int tl_intvec_rxeof __P((void *, u_int32_t));
288static int tl_intvec_adchk __P((void *, u_int32_t));
289static int tl_intvec_netsts __P((void *, u_int32_t));
290
291static int tl_newbuf __P((struct tl_softc *,
292 struct tl_chain_onefrag *));
293static void tl_stats_update __P((void *));
294static int tl_encap __P((struct tl_softc *, struct tl_chain *,
295 struct mbuf *));
296
297static void tl_intr __P((void *));
298static void tl_start __P((struct ifnet *));
299static int tl_ioctl __P((struct ifnet *, u_long, caddr_t));
300static void tl_init __P((void *));
301static void tl_stop __P((struct tl_softc *));
302static void tl_watchdog __P((struct ifnet *));
303static void tl_shutdown __P((int, void *));
304static int tl_ifmedia_upd __P((struct ifnet *));
305static void tl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
306
307static u_int8_t tl_eeprom_putbyte __P((struct tl_softc *, int));
308static u_int8_t tl_eeprom_getbyte __P((struct tl_softc *,
309 int, u_int8_t *));
310static int tl_read_eeprom __P((struct tl_softc *, caddr_t, int, int));
311
312static void tl_mii_sync __P((struct tl_softc *));
313static void tl_mii_send __P((struct tl_softc *, u_int32_t, int));
314static int tl_mii_readreg __P((struct tl_softc *, struct tl_mii_frame *));
315static int tl_mii_writereg __P((struct tl_softc *, struct tl_mii_frame *));
316static u_int16_t tl_phy_readreg __P((struct tl_softc *, int));
317static void tl_phy_writereg __P((struct tl_softc *, int, int));
318
319static void tl_autoneg __P((struct tl_softc *, int, int));
320static void tl_setmode __P((struct tl_softc *, int));
321static int tl_calchash __P((caddr_t));
322static void tl_setmulti __P((struct tl_softc *));
323static void tl_setfilt __P((struct tl_softc *, caddr_t, int));
324static void tl_softreset __P((struct tl_softc *, int));
325static void tl_hardreset __P((struct tl_softc *));
326static int tl_list_rx_init __P((struct tl_softc *));
327static int tl_list_tx_init __P((struct tl_softc *));
328
329static u_int8_t tl_dio_read8 __P((struct tl_softc *, int));
330static u_int16_t tl_dio_read16 __P((struct tl_softc *, int));
331static u_int32_t tl_dio_read32 __P((struct tl_softc *, int));
332static void tl_dio_write8 __P((struct tl_softc *, int, int));
333static void tl_dio_write16 __P((struct tl_softc *, int, int));
334static void tl_dio_write32 __P((struct tl_softc *, int, int));
335static void tl_dio_setbit __P((struct tl_softc *, int, int));
336static void tl_dio_clrbit __P((struct tl_softc *, int, int));
337static void tl_dio_setbit16 __P((struct tl_softc *, int, int));
338static void tl_dio_clrbit16 __P((struct tl_softc *, int, int));
339
340static u_int8_t tl_dio_read8(sc, reg)
341 struct tl_softc *sc;
342 int reg;
343{
344 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
345 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
346}
347
348static u_int16_t tl_dio_read16(sc, reg)
349 struct tl_softc *sc;
350 int reg;
351{
352 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
353 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
354}
355
356static u_int32_t tl_dio_read32(sc, reg)
357 struct tl_softc *sc;
358 int reg;
359{
360 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
361 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
362}
363
364static void tl_dio_write8(sc, reg, val)
365 struct tl_softc *sc;
366 int reg;
367 int val;
368{
369 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
370 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
371 return;
372}
373
374static void tl_dio_write16(sc, reg, val)
375 struct tl_softc *sc;
376 int reg;
377 int val;
378{
379 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
380 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
381 return;
382}
383
384static void tl_dio_write32(sc, reg, val)
385 struct tl_softc *sc;
386 int reg;
387 int val;
388{
389 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
390 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
391 return;
392}
393
394static void tl_dio_setbit(sc, reg, bit)
395 struct tl_softc *sc;
396 int reg;
397 int bit;
398{
399 u_int8_t f;
400
401 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
402 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
403 f |= bit;
404 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
405
406 return;
407}
408
409static void tl_dio_clrbit(sc, reg, bit)
410 struct tl_softc *sc;
411 int reg;
412 int bit;
413{
414 u_int8_t f;
415
416 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
417 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
418 f &= ~bit;
419 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
420
421 return;
422}
423
424static void tl_dio_setbit16(sc, reg, bit)
425 struct tl_softc *sc;
426 int reg;
427 int bit;
428{
429 u_int16_t f;
430
431 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
432 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
433 f |= bit;
434 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
435
436 return;
437}
438
439static void tl_dio_clrbit16(sc, reg, bit)
440 struct tl_softc *sc;
441 int reg;
442 int bit;
443{
444 u_int16_t f;
445
446 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
447 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
448 f &= ~bit;
449 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
450
451 return;
452}
453
454/*
455 * Send an instruction or address to the EEPROM, check for ACK.
456 */
457static u_int8_t tl_eeprom_putbyte(sc, byte)
458 struct tl_softc *sc;
459 int byte;
460{
461 register int i, ack = 0;
462
463 /*
464 * Make sure we're in TX mode.
465 */
466 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN);
467
468 /*
469 * Feed in each bit and stobe the clock.
470 */
471 for (i = 0x80; i; i >>= 1) {
472 if (byte & i) {
473 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA);
474 } else {
475 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA);
476 }
477 DELAY(1);
478 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
479 DELAY(1);
480 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
481 }
482
483 /*
484 * Turn off TX mode.
485 */
486 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
487
488 /*
489 * Check for ack.
490 */
491 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
492 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA;
493 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
494
495 return(ack);
496}
497
498/*
499 * Read a byte of data stored in the EEPROM at address 'addr.'
500 */
501static u_int8_t tl_eeprom_getbyte(sc, addr, dest)
502 struct tl_softc *sc;
503 int addr;
504 u_int8_t *dest;
505{
506 register int i;
507 u_int8_t byte = 0;
508
509 tl_dio_write8(sc, TL_NETSIO, 0);
510
511 EEPROM_START;
512
513 /*
514 * Send write control code to EEPROM.
515 */
516 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
517 printf("tl%d: failed to send write command, status: %x\n",
518 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
519 return(1);
520 }
521
522 /*
523 * Send address of byte we want to read.
524 */
525 if (tl_eeprom_putbyte(sc, addr)) {
526 printf("tl%d: failed to send address, status: %x\n",
527 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
528 return(1);
529 }
530
531 EEPROM_STOP;
532 EEPROM_START;
533 /*
534 * Send read control code to EEPROM.
535 */
536 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
537 printf("tl%d: failed to send write command, status: %x\n",
538 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
539 return(1);
540 }
541
542 /*
543 * Start reading bits from EEPROM.
544 */
545 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
546 for (i = 0x80; i; i >>= 1) {
547 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
548 DELAY(1);
549 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA)
550 byte |= i;
551 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
552 DELAY(1);
553 }
554
555 EEPROM_STOP;
556
557 /*
558 * No ACK generated for read, so just return byte.
559 */
560
561 *dest = byte;
562
563 return(0);
564}
565
566/*
567 * Read a sequence of bytes from the EEPROM.
568 */
569static int tl_read_eeprom(sc, dest, off, cnt)
570 struct tl_softc *sc;
571 caddr_t dest;
572 int off;
573 int cnt;
574{
575 int err = 0, i;
576 u_int8_t byte = 0;
577
578 for (i = 0; i < cnt; i++) {
579 err = tl_eeprom_getbyte(sc, off + i, &byte);
580 if (err)
581 break;
582 *(dest + i) = byte;
583 }
584
585 return(err ? 1 : 0);
586}
587
588static void tl_mii_sync(sc)
589 struct tl_softc *sc;
590{
591 register int i;
592
593 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
594
595 for (i = 0; i < 32; i++) {
596 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
597 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
598 }
599
600 return;
601}
602
603static void tl_mii_send(sc, bits, cnt)
604 struct tl_softc *sc;
605 u_int32_t bits;
606 int cnt;
607{
608 int i;
609
610 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
611 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
612 if (bits & i) {
613 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA);
614 } else {
615 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA);
616 }
617 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
618 }
619}
620
621static int tl_mii_readreg(sc, frame)
622 struct tl_softc *sc;
623 struct tl_mii_frame *frame;
624
625{
626 int i, ack, s;
627 int minten = 0;
628
629 s = splimp();
630
631 tl_mii_sync(sc);
632
633 /*
634 * Set up frame for RX.
635 */
636 frame->mii_stdelim = TL_MII_STARTDELIM;
637 frame->mii_opcode = TL_MII_READOP;
638 frame->mii_turnaround = 0;
639 frame->mii_data = 0;
640
641 /*
642 * Turn off MII interrupt by forcing MINTEN low.
643 */
644 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
645 if (minten) {
646 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
647 }
648
649 /*
650 * Turn on data xmit.
651 */
652 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
653
654 /*
655 * Send command/address info.
656 */
657 tl_mii_send(sc, frame->mii_stdelim, 2);
658 tl_mii_send(sc, frame->mii_opcode, 2);
659 tl_mii_send(sc, frame->mii_phyaddr, 5);
660 tl_mii_send(sc, frame->mii_regaddr, 5);
661
662 /*
663 * Turn off xmit.
664 */
665 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
666
667 /* Idle bit */
668 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
669 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
670
671 /* Check for ack */
672 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
673 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA;
674
675 /* Complete the cycle */
676 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
677
678 /*
679 * Now try reading data bits. If the ack failed, we still
680 * need to clock through 16 cycles to keep the PHYs in sync.
681 */
682 if (ack) {
683 for(i = 0; i < 16; i++) {
684 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
685 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
686 }
687 goto fail;
688 }
689
690 for (i = 0x8000; i; i >>= 1) {
691 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
692 if (!ack) {
693 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA)
694 frame->mii_data |= i;
695 }
696 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
697 }
698
699fail:
700
701 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
702 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
703
704 /* Reenable interrupts */
705 if (minten) {
706 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
707 }
708
709 splx(s);
710
711 if (ack)
712 return(1);
713 return(0);
714}
715
716static int tl_mii_writereg(sc, frame)
717 struct tl_softc *sc;
718 struct tl_mii_frame *frame;
719
720{
721 int s;
722 int minten;
723
724 tl_mii_sync(sc);
725
726 s = splimp();
727 /*
728 * Set up frame for TX.
729 */
730
731 frame->mii_stdelim = TL_MII_STARTDELIM;
732 frame->mii_opcode = TL_MII_WRITEOP;
733 frame->mii_turnaround = TL_MII_TURNAROUND;
734
735 /*
736 * Turn off MII interrupt by forcing MINTEN low.
737 */
738 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
739 if (minten) {
740 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
741 }
742
743 /*
744 * Turn on data output.
745 */
746 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
747
748 tl_mii_send(sc, frame->mii_stdelim, 2);
749 tl_mii_send(sc, frame->mii_opcode, 2);
750 tl_mii_send(sc, frame->mii_phyaddr, 5);
751 tl_mii_send(sc, frame->mii_regaddr, 5);
752 tl_mii_send(sc, frame->mii_turnaround, 2);
753 tl_mii_send(sc, frame->mii_data, 16);
754
755 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
756 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
757
758 /*
759 * Turn off xmit.
760 */
761 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
762
763 /* Reenable interrupts */
764 if (minten)
765 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
766
767 splx(s);
768
769 return(0);
770}
771
772static u_int16_t tl_phy_readreg(sc, reg)
773 struct tl_softc *sc;
774 int reg;
775{
776 struct tl_mii_frame frame;
777
778 bzero((char *)&frame, sizeof(frame));
779
780 frame.mii_phyaddr = sc->tl_phy_addr;
781 frame.mii_regaddr = reg;
782 tl_mii_readreg(sc, &frame);
783
784 /* Reenable MII interrupts, just in case. */
785 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
786
787 return(frame.mii_data);
788}
789
790static void tl_phy_writereg(sc, reg, data)
791 struct tl_softc *sc;
792 int reg;
793 int data;
794{
795 struct tl_mii_frame frame;
796
797 bzero((char *)&frame, sizeof(frame));
798
799 frame.mii_phyaddr = sc->tl_phy_addr;
800 frame.mii_regaddr = reg;
801 frame.mii_data = data;
802
803 tl_mii_writereg(sc, &frame);
804
805 /* Reenable MII interrupts, just in case. */
806 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
807
808 return;
809}
810
811/*
812 * Initiate autonegotiation with a link partner.
813 *
814 * Note that the Texas Instruments ThunderLAN programmer's guide
815 * fails to mention one very important point about autonegotiation.
816 * Autonegotiation is done largely by the PHY, independent of the
817 * ThunderLAN chip itself: the PHY sets the flags in the BMCR
818 * register to indicate what modes were selected and if link status
819 * is good. In fact, the PHY does pretty much all of the work itself,
820 * except for one small detail.
821 *
822 * The PHY may negotiate a full-duplex of half-duplex link, and set
823 * the PHY_BMCR_DUPLEX bit accordingly, but the ThunderLAN's 'NetCommand'
824 * register _also_ has a half-duplex/full-duplex bit, and you MUST ALSO
825 * SET THIS BIT MANUALLY TO CORRESPOND TO THE MODE SELECTED FOR THE PHY!
826 * In other words, both the ThunderLAN chip and the PHY have to be
827 * programmed for full-duplex mode in order for full-duplex to actually
828 * work. So in order for autonegotiation to really work right, we have
829 * to wait for the link to come up, check the BMCR register, then set
830 * the ThunderLAN for full or half-duplex as needed.
831 *
832 * I struggled for two days to figure this out, so I'm making a point
833 * of drawing attention to this fact. I think it's very strange that
834 * the ThunderLAN doesn't automagically track the duplex state of the
835 * PHY, but there you have it.
836 *
837 * Also when, using a National Semiconductor DP83840A PHY, we have to
838 * allow a full three seconds for autonegotiation to complete. So what
839 * we do is flip the autonegotiation restart bit, then set a timeout
840 * to wake us up in three seconds to check the link state.
841 *
842 * Note that there are some versions of the Olicom 2326 that use a
843 * Micro Linear ML6692 100BaseTX PHY. This particular PHY is designed
844 * to provide 100BaseTX support only, but can be used with a controller
845 * that supports an internal 10Mbps PHY to provide a complete
846 * 10/100Mbps solution. However, the ML6692 does not have vendor and
847 * device ID registers, and hence always shows up with a vendor/device
848 * ID of 0.
849 *
850 * We detect this configuration by checking the phy vendor ID in the
851 * softc structure. If it's a zero, and we're negotiating a high-speed
852 * mode, then we turn off the internal PHY. If it's a zero and we've
853 * negotiated a high-speed mode, we turn on the internal PHY. Note
854 * that to make things even more fun, we have to make extra sure that
855 * the loopback bit in the internal PHY's control register is turned
856 * off.
857 */
858static void tl_autoneg(sc, flag, verbose)
859 struct tl_softc *sc;
860 int flag;
861 int verbose;
862{
863 u_int16_t phy_sts = 0, media = 0, advert, ability;
864 struct ifnet *ifp;
865 struct ifmedia *ifm;
866
867 ifm = &sc->ifmedia;
868 ifp = &sc->arpcom.ac_if;
869
870 /*
871 * First, see if autoneg is supported. If not, there's
872 * no point in continuing.
873 */
874 phy_sts = tl_phy_readreg(sc, PHY_BMSR);
875 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
876 if (verbose)
877 printf("tl%d: autonegotiation not supported\n",
878 sc->tl_unit);
879 return;
880 }
881
882 switch (flag) {
883 case TL_FLAG_FORCEDELAY:
884 /*
885 * XXX Never use this option anywhere but in the probe
886 * routine: making the kernel stop dead in its tracks
887 * for three whole seconds after we've gone multi-user
888 * is really bad manners.
889 */
890 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
891 DELAY(500);
892 phy_sts = tl_phy_readreg(sc, PHY_BMCR);
893 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
894 tl_phy_writereg(sc, PHY_BMCR, phy_sts);
895 DELAY(5000000);
896 break;
897 case TL_FLAG_SCHEDDELAY:
898 /*
899 * Wait for the transmitter to go idle before starting
900 * an autoneg session, otherwise tl_start() may clobber
901 * our timeout, and we don't want to allow transmission
902 * during an autoneg session since that can screw it up.
903 */
904 if (!sc->tl_txeoc) {
905 sc->tl_want_auto = 1;
906 return;
907 }
908 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
909 DELAY(500);
910 phy_sts = tl_phy_readreg(sc, PHY_BMCR);
911 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
912 tl_phy_writereg(sc, PHY_BMCR, phy_sts);
913 ifp->if_timer = 5;
914 sc->tl_autoneg = 1;
915 sc->tl_want_auto = 0;
916 return;
917 case TL_FLAG_DELAYTIMEO:
918 ifp->if_timer = 0;
919 sc->tl_autoneg = 0;
920 break;
921 default:
922 printf("tl%d: invalid autoneg flag: %d\n", sc->tl_unit, flag);
923 return;
924 }
925
926 /*
927 * Read the BMSR register twice: the LINKSTAT bit is a
928 * latching bit.
929 */
930 tl_phy_readreg(sc, PHY_BMSR);
931 phy_sts = tl_phy_readreg(sc, PHY_BMSR);
932 if (phy_sts & PHY_BMSR_AUTONEGCOMP) {
933 if (verbose)
934 printf("tl%d: autoneg complete, ", sc->tl_unit);
935 phy_sts = tl_phy_readreg(sc, PHY_BMSR);
936 } else {
937 if (verbose)
938 printf("tl%d: autoneg not complete, ", sc->tl_unit);
939 }
940
941 /* Link is good. Report modes and set duplex mode. */
942 if (phy_sts & PHY_BMSR_LINKSTAT) {
943 if (verbose)
944 printf("link status good ");
945
946 advert = tl_phy_readreg(sc, TL_PHY_ANAR);
947 ability = tl_phy_readreg(sc, TL_PHY_LPAR);
948 media = tl_phy_readreg(sc, PHY_BMCR);
949
950 /*
951 * Be sure to turn off the ISOLATE and
952 * LOOPBACK bits in the control register,
953 * otherwise we may not be able to communicate.
954 */
955 media &= ~(PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE);
956 /* Set the DUPLEX bit in the NetCmd register accordingly. */
957 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
958 ifm->ifm_media = IFM_ETHER|IFM_100_T4;
959 media |= PHY_BMCR_SPEEDSEL;
960 media &= ~PHY_BMCR_DUPLEX;
961 if (verbose)
962 printf("(100baseT4)\n");
963 } else if (advert & PHY_ANAR_100BTXFULL &&
964 ability & PHY_ANAR_100BTXFULL) {
965 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
966 media |= PHY_BMCR_SPEEDSEL;
967 media |= PHY_BMCR_DUPLEX;
968 if (verbose)
969 printf("(full-duplex, 100Mbps)\n");
970 } else if (advert & PHY_ANAR_100BTXHALF &&
971 ability & PHY_ANAR_100BTXHALF) {
972 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
973 media |= PHY_BMCR_SPEEDSEL;
974 media &= ~PHY_BMCR_DUPLEX;
975 if (verbose)
976 printf("(half-duplex, 100Mbps)\n");
977 } else if (advert & PHY_ANAR_10BTFULL &&
978 ability & PHY_ANAR_10BTFULL) {
979 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
980 media &= ~PHY_BMCR_SPEEDSEL;
981 media |= PHY_BMCR_DUPLEX;
982 if (verbose)
983 printf("(full-duplex, 10Mbps)\n");
984 } else {
985 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
986 media &= ~PHY_BMCR_SPEEDSEL;
987 media &= ~PHY_BMCR_DUPLEX;
988 if (verbose)
989 printf("(half-duplex, 10Mbps)\n");
990 }
991
992 if (media & PHY_BMCR_DUPLEX)
993 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
994 else
995 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
996
997 media &= ~PHY_BMCR_AUTONEGENBL;
998 tl_phy_writereg(sc, PHY_BMCR, media);
999 } else {
1000 if (verbose)
1001 printf("no carrier\n");
1002 }
1003
1004 tl_init(sc);
1005
1006 if (sc->tl_tx_pend) {
1007 sc->tl_autoneg = 0;
1008 sc->tl_tx_pend = 0;
1009 tl_start(ifp);
1010 }
1011
1012 return;
1013}
1014
1015/*
1016 * Set speed and duplex mode. Also program autoneg advertisements
1017 * accordingly.
1018 */
1019static void tl_setmode(sc, media)
1020 struct tl_softc *sc;
1021 int media;
1022{
1023 u_int16_t bmcr;
1024
1025 if (sc->tl_bitrate) {
1026 if (IFM_SUBTYPE(media) == IFM_10_5)
1027 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
1028 if (IFM_SUBTYPE(media) == IFM_10_T) {
1029 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
1030 if ((media & IFM_GMASK) == IFM_FDX) {
1031 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
1032 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
1033 } else {
1034 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
1035 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
1036 }
1037 }
1038 return;
1039 }
1040
1041 bmcr = tl_phy_readreg(sc, PHY_BMCR);
1042
1043 bmcr &= ~(PHY_BMCR_SPEEDSEL|PHY_BMCR_DUPLEX|PHY_BMCR_AUTONEGENBL|
1044 PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE);
1045
1046 if (IFM_SUBTYPE(media) == IFM_LOOP)
1047 bmcr |= PHY_BMCR_LOOPBK;
1048
1049 if (IFM_SUBTYPE(media) == IFM_AUTO)
1050 bmcr |= PHY_BMCR_AUTONEGENBL;
1051
1052 /*
1053 * The ThunderLAN's internal PHY has an AUI transceiver
1054 * that can be selected. This is usually attached to a
1055 * 10base2/BNC port. In order to activate this port, we
1056 * have to set the AUISEL bit in the internal PHY's
1057 * special control register.
1058 */
1059 if (IFM_SUBTYPE(media) == IFM_10_5) {
1060 u_int16_t addr, ctl;
1061 addr = sc->tl_phy_addr;
1062 sc->tl_phy_addr = TL_PHYADDR_MAX;
1063 ctl = tl_phy_readreg(sc, TL_PHY_CTL);
1064 ctl |= PHY_CTL_AUISEL;
1065 tl_phy_writereg(sc, TL_PHY_CTL, ctl);
1066 tl_phy_writereg(sc, PHY_BMCR, bmcr);
1067 sc->tl_phy_addr = addr;
1068 bmcr |= PHY_BMCR_ISOLATE;
1069 } else {
1070 u_int16_t addr, ctl;
1071 addr = sc->tl_phy_addr;
1072 sc->tl_phy_addr = TL_PHYADDR_MAX;
1073 ctl = tl_phy_readreg(sc, TL_PHY_CTL);
1074 ctl &= ~PHY_CTL_AUISEL;
1075 tl_phy_writereg(sc, TL_PHY_CTL, ctl);
1076 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_ISOLATE);
1077 sc->tl_phy_addr = addr;
1078 bmcr &= ~PHY_BMCR_ISOLATE;
1079 }
1080
1081 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1082 bmcr |= PHY_BMCR_SPEEDSEL;
1083 if ((media & IFM_GMASK) == IFM_FDX) {
1084 bmcr |= PHY_BMCR_DUPLEX;
1085 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
1086 } else {
1087 bmcr &= ~PHY_BMCR_DUPLEX;
1088 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
1089 }
1090 }
1091
1092 if (IFM_SUBTYPE(media) == IFM_10_T) {
1093 bmcr &= ~PHY_BMCR_SPEEDSEL;
1094 if ((media & IFM_GMASK) == IFM_FDX) {
1095 bmcr |= PHY_BMCR_DUPLEX;
1096 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
1097 } else {
1098 bmcr &= ~PHY_BMCR_DUPLEX;
1099 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
1100 }
1101 }
1102
1103 tl_phy_writereg(sc, PHY_BMCR, bmcr);
1104
1105 tl_init(sc);
1106
1107 return;
1108}
1109
1110/*
1111 * Calculate the hash of a MAC address for programming the multicast hash
1112 * table. This hash is simply the address split into 6-bit chunks
1113 * XOR'd, e.g.
1114 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
1115 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210
1116 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then
1117 * the folded 24-bit value is split into 6-bit portions and XOR'd.
1118 */
1119static int tl_calchash(addr)
1120 caddr_t addr;
1121{
1122 int t;
1123
1124 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 |
1125 (addr[2] ^ addr[5]);
1126 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f;
1127}
1128
1129/*
1130 * The ThunderLAN has a perfect MAC address filter in addition to
1131 * the multicast hash filter. The perfect filter can be programmed
1132 * with up to four MAC addresses. The first one is always used to
1133 * hold the station address, which leaves us free to use the other
1134 * three for multicast addresses.
1135 */
1136static void tl_setfilt(sc, addr, slot)
1137 struct tl_softc *sc;
1138 caddr_t addr;
1139 int slot;
1140{
1141 int i;
1142 u_int16_t regaddr;
1143
1144 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
1145
1146 for (i = 0; i < ETHER_ADDR_LEN; i++)
1147 tl_dio_write8(sc, regaddr + i, *(addr + i));
1148
1149 return;
1150}
1151
1152/*
1153 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly
1154 * linked list. This is fine, except addresses are added from the head
1155 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts")
1156 * group to always be in the perfect filter, but as more groups are added,
1157 * the 224.0.0.1 entry (which is always added first) gets pushed down
1158 * the list and ends up at the tail. So after 3 or 4 multicast groups
1159 * are added, the all-hosts entry gets pushed out of the perfect filter
1160 * and into the hash table.
1161 *
1162 * Because the multicast list is a doubly-linked list as opposed to a
1163 * circular queue, we don't have the ability to just grab the tail of
1164 * the list and traverse it backwards. Instead, we have to traverse
1165 * the list once to find the tail, then traverse it again backwards to
1166 * update the multicast filter.
1167 */
1168static void tl_setmulti(sc)
1169 struct tl_softc *sc;
1170{
1171 struct ifnet *ifp;
1172 u_int32_t hashes[2] = { 0, 0 };
1173 int h, i;
1174 struct ifmultiaddr *ifma;
1175 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
1176 ifp = &sc->arpcom.ac_if;
1177
1178 /* First, zot all the existing filters. */
1179 for (i = 1; i < 4; i++)
1180 tl_setfilt(sc, (caddr_t)&dummy, i);
1181 tl_dio_write32(sc, TL_HASH1, 0);
1182 tl_dio_write32(sc, TL_HASH2, 0);
1183
1184 /* Now program new ones. */
1185 if (ifp->if_flags & IFF_ALLMULTI) {
1186 hashes[0] = 0xFFFFFFFF;
1187 hashes[1] = 0xFFFFFFFF;
1188 } else {
1189 i = 1;
1190 /* First find the tail of the list. */
1191 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1192 ifma = ifma->ifma_link.le_next) {
1193 if (ifma->ifma_link.le_next == NULL)
1194 break;
1195 }
1196 /* Now traverse the list backwards. */
1197 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
1198 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
1199 if (ifma->ifma_addr->sa_family != AF_LINK)
1200 continue;
1201 /*
1202 * Program the first three multicast groups
1203 * into the perfect filter. For all others,
1204 * use the hash table.
1205 */
1206 if (i < 4) {
1207 tl_setfilt(sc,
1208 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
1209 i++;
1210 continue;
1211 }
1212
1213 h = tl_calchash(
1214 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1215 if (h < 32)
1216 hashes[0] |= (1 << h);
1217 else
1218 hashes[1] |= (1 << (h - 32));
1219 }
1220 }
1221
1222 tl_dio_write32(sc, TL_HASH1, hashes[0]);
1223 tl_dio_write32(sc, TL_HASH2, hashes[1]);
1224
1225 return;
1226}
1227
1228/*
1229 * This routine is recommended by the ThunderLAN manual to insure that
1230 * the internal PHY is powered up correctly. It also recommends a one
1231 * second pause at the end to 'wait for the clocks to start' but in my
1232 * experience this isn't necessary.
1233 */
1234static void tl_hardreset(sc)
1235 struct tl_softc *sc;
1236{
1237 int i;
1238 u_int16_t old_addr, flags;
1239
1240 old_addr = sc->tl_phy_addr;
1241
1242 for (i = 0; i < TL_PHYADDR_MAX + 1; i++) {
1243 sc->tl_phy_addr = i;
1244 tl_mii_sync(sc);
1245 }
1246
1247 flags = PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE|PHY_BMCR_PWRDOWN;
1248
1249 for (i = 0; i < TL_PHYADDR_MAX + 1; i++) {
1250 sc->tl_phy_addr = i;
1251 tl_phy_writereg(sc, PHY_BMCR, flags);
1252 }
1253
1254 sc->tl_phy_addr = TL_PHYADDR_MAX;
1255 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_ISOLATE);
1256
1257 DELAY(50000);
1258
1259 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE);
1260
1261 tl_mii_sync(sc);
1262
1263 while(tl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
1264
1265 sc->tl_phy_addr = old_addr;
1266
1267 return;
1268}
1269
1270static void tl_softreset(sc, internal)
1271 struct tl_softc *sc;
1272 int internal;
1273{
1274 u_int32_t cmd, dummy, i;
1275
1276 /* Assert the adapter reset bit. */
1277 CMD_SET(sc, TL_CMD_ADRST);
1278 /* Turn off interrupts */
1279 CMD_SET(sc, TL_CMD_INTSOFF);
1280
1281 /* First, clear the stats registers. */
1282 for (i = 0; i < 5; i++)
1283 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES);
1284
1285 /* Clear Areg and Hash registers */
1286 for (i = 0; i < 8; i++)
1287 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000);
1288
1289 /*
1290 * Set up Netconfig register. Enable one channel and
1291 * one fragment mode.
1292 */
1293 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG);
1294 if (internal && !sc->tl_bitrate) {
1295 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1296 } else {
1297 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1298 }
1299
1300 /* Handle cards with bitrate devices. */
1301 if (sc->tl_bitrate)
1302 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE);
1303
1304 /* Set PCI burst size */
1305 tl_dio_write8(sc, TL_BSIZEREG, 0x33);
1306
1307 /*
1308 * Load adapter irq pacing timer and tx threshold.
1309 * We make the transmit threshold 1 initially but we may
1310 * change that later.
1311 */
1312 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1313 cmd |= TL_CMD_NES;
1314 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK);
1315 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR));
1316 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003));
1317
1318 /* Unreset the MII */
1319 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
1320
1321 /* Clear status register */
1322 tl_dio_setbit16(sc, TL_NETSTS, TL_STS_MIRQ);
1323 tl_dio_setbit16(sc, TL_NETSTS, TL_STS_HBEAT);
1324 tl_dio_setbit16(sc, TL_NETSTS, TL_STS_TXSTOP);
1325 tl_dio_setbit16(sc, TL_NETSTS, TL_STS_RXSTOP);
1326
1327 /* Enable network status interrupts for everything. */
1328 tl_dio_setbit(sc, TL_NETMASK, TL_MASK_MASK7|TL_MASK_MASK6|
1329 TL_MASK_MASK5|TL_MASK_MASK4);
1330
1331 /* Take the adapter out of reset */
1332 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
1333
1334 /* Wait for things to settle down a little. */
1335 DELAY(500);
1336
1337 return;
1338}
1339
1340/*
1341 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
1342 * against our list and return its name if we find a match.
1343 */
1344static const char *
1345tl_probe(config_id, device_id)
1346 pcici_t config_id;
1347 pcidi_t device_id;
1348{
1349 struct tl_type *t;
1350
1351 t = tl_devs;
1352
1353 while(t->tl_name != NULL) {
1354 if ((device_id & 0xFFFF) == t->tl_vid &&
1355 ((device_id >> 16) & 0xFFFF) == t->tl_did)
1356 return(t->tl_name);
1357 t++;
1358 }
1359
1360 return(NULL);
1361}
1362
1363/*
1364 * Do the interface setup and attach for a PHY on a particular
1365 * ThunderLAN chip. Also also set up interrupt vectors.
1366 */
1367static int tl_attach_phy(sc)
1368 struct tl_softc *sc;
1369{
1370 int phy_ctl;
1371 struct tl_type *p = tl_phys;
1372 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1373 struct ifnet *ifp;
1374
1375 ifp = &sc->arpcom.ac_if;
1376
1377 sc->tl_phy_did = tl_phy_readreg(sc, TL_PHY_DEVID);
1378 sc->tl_phy_vid = tl_phy_readreg(sc, TL_PHY_VENID);
1379 sc->tl_phy_sts = tl_phy_readreg(sc, TL_PHY_GENSTS);
1380 phy_ctl = tl_phy_readreg(sc, TL_PHY_GENCTL);
1381
1382 /*
1383 * PHY revision numbers tend to vary a bit. Our algorithm here
1384 * is to check everything but the 8 least significant bits.
1385 */
1386 while(p->tl_vid) {
1387 if (sc->tl_phy_vid == p->tl_vid &&
1388 (sc->tl_phy_did | 0x000F) == p->tl_did) {
1389 sc->tl_pinfo = p;
1390 break;
1391 }
1392 p++;
1393 }
1394 if (sc->tl_pinfo == NULL) {
1395 sc->tl_pinfo = &tl_phys[PHY_UNKNOWN];
1396 }
1397
1398 if (sc->tl_phy_sts & PHY_BMSR_100BT4 ||
1399 sc->tl_phy_sts & PHY_BMSR_100BTXFULL ||
1400 sc->tl_phy_sts & PHY_BMSR_100BTXHALF)
1401 ifp->if_baudrate = 100000000;
1402 else
1403 ifp->if_baudrate = 10000000;
1404
1405 if (bootverbose) {
1406 printf("tl%d: phy at mii address %d\n", sc->tl_unit,
1407 sc->tl_phy_addr);
1408
1409 printf("tl%d: %s ", sc->tl_unit, sc->tl_pinfo->tl_name);
1410 }
1411
1412 if (sc->tl_phy_sts & PHY_BMSR_100BT4 ||
1413 sc->tl_phy_sts & PHY_BMSR_100BTXHALF ||
225#endif
226
227/*
228 * Various supported device vendors/types and their names.
229 */
230
231static struct tl_type tl_devs[] = {
232 { TI_VENDORID, TI_DEVICEID_THUNDERLAN,
233 "Texas Instruments ThunderLAN" },
234 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
235 "Compaq Netelligent 10" },
236 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
237 "Compaq Netelligent 10/100" },
238 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
239 "Compaq Netelligent 10/100 Proliant" },
240 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL,
241 "Compaq Netelligent 10/100 Dual Port" },
242 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED,
243 "Compaq NetFlex-3/P Integrated" },
244 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P,
245 "Compaq NetFlex-3/P" },
246 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC,
247 "Compaq NetFlex 3/P w/ BNC" },
248 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED,
249 "Compaq Netelligent 10/100 TX Embedded UTP" },
250 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX,
251 "Compaq Netelligent 10 T/2 PCI UTP/Coax" },
252 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP,
253 "Compaq Netelligent 10/100 TX UTP" },
254 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183,
255 "Olicom OC-2183/2185" },
256 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325,
257 "Olicom OC-2325" },
258 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326,
259 "Olicom OC-2326 10/100 TX UTP" },
260 { 0, 0, NULL }
261};
262
263/*
264 * Various supported PHY vendors/types and their names. Note that
265 * this driver will work with pretty much any MII-compliant PHY,
266 * so failure to positively identify the chip is not a fatal error.
267 */
268
269static struct tl_type tl_phys[] = {
270 { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" },
271 { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" },
272 { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"},
273 { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" },
274 { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" },
275 { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" },
276 { 0, 0, "<MII-compliant physical interface>" }
277};
278
279static unsigned long tl_count;
280
281static const char *tl_probe __P((pcici_t, pcidi_t));
282static void tl_attach __P((pcici_t, int));
283static int tl_attach_phy __P((struct tl_softc *));
284static int tl_intvec_rxeoc __P((void *, u_int32_t));
285static int tl_intvec_txeoc __P((void *, u_int32_t));
286static int tl_intvec_txeof __P((void *, u_int32_t));
287static int tl_intvec_rxeof __P((void *, u_int32_t));
288static int tl_intvec_adchk __P((void *, u_int32_t));
289static int tl_intvec_netsts __P((void *, u_int32_t));
290
291static int tl_newbuf __P((struct tl_softc *,
292 struct tl_chain_onefrag *));
293static void tl_stats_update __P((void *));
294static int tl_encap __P((struct tl_softc *, struct tl_chain *,
295 struct mbuf *));
296
297static void tl_intr __P((void *));
298static void tl_start __P((struct ifnet *));
299static int tl_ioctl __P((struct ifnet *, u_long, caddr_t));
300static void tl_init __P((void *));
301static void tl_stop __P((struct tl_softc *));
302static void tl_watchdog __P((struct ifnet *));
303static void tl_shutdown __P((int, void *));
304static int tl_ifmedia_upd __P((struct ifnet *));
305static void tl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
306
307static u_int8_t tl_eeprom_putbyte __P((struct tl_softc *, int));
308static u_int8_t tl_eeprom_getbyte __P((struct tl_softc *,
309 int, u_int8_t *));
310static int tl_read_eeprom __P((struct tl_softc *, caddr_t, int, int));
311
312static void tl_mii_sync __P((struct tl_softc *));
313static void tl_mii_send __P((struct tl_softc *, u_int32_t, int));
314static int tl_mii_readreg __P((struct tl_softc *, struct tl_mii_frame *));
315static int tl_mii_writereg __P((struct tl_softc *, struct tl_mii_frame *));
316static u_int16_t tl_phy_readreg __P((struct tl_softc *, int));
317static void tl_phy_writereg __P((struct tl_softc *, int, int));
318
319static void tl_autoneg __P((struct tl_softc *, int, int));
320static void tl_setmode __P((struct tl_softc *, int));
321static int tl_calchash __P((caddr_t));
322static void tl_setmulti __P((struct tl_softc *));
323static void tl_setfilt __P((struct tl_softc *, caddr_t, int));
324static void tl_softreset __P((struct tl_softc *, int));
325static void tl_hardreset __P((struct tl_softc *));
326static int tl_list_rx_init __P((struct tl_softc *));
327static int tl_list_tx_init __P((struct tl_softc *));
328
329static u_int8_t tl_dio_read8 __P((struct tl_softc *, int));
330static u_int16_t tl_dio_read16 __P((struct tl_softc *, int));
331static u_int32_t tl_dio_read32 __P((struct tl_softc *, int));
332static void tl_dio_write8 __P((struct tl_softc *, int, int));
333static void tl_dio_write16 __P((struct tl_softc *, int, int));
334static void tl_dio_write32 __P((struct tl_softc *, int, int));
335static void tl_dio_setbit __P((struct tl_softc *, int, int));
336static void tl_dio_clrbit __P((struct tl_softc *, int, int));
337static void tl_dio_setbit16 __P((struct tl_softc *, int, int));
338static void tl_dio_clrbit16 __P((struct tl_softc *, int, int));
339
340static u_int8_t tl_dio_read8(sc, reg)
341 struct tl_softc *sc;
342 int reg;
343{
344 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
345 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
346}
347
348static u_int16_t tl_dio_read16(sc, reg)
349 struct tl_softc *sc;
350 int reg;
351{
352 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
353 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
354}
355
356static u_int32_t tl_dio_read32(sc, reg)
357 struct tl_softc *sc;
358 int reg;
359{
360 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
361 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
362}
363
364static void tl_dio_write8(sc, reg, val)
365 struct tl_softc *sc;
366 int reg;
367 int val;
368{
369 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
370 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
371 return;
372}
373
374static void tl_dio_write16(sc, reg, val)
375 struct tl_softc *sc;
376 int reg;
377 int val;
378{
379 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
380 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
381 return;
382}
383
384static void tl_dio_write32(sc, reg, val)
385 struct tl_softc *sc;
386 int reg;
387 int val;
388{
389 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
390 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
391 return;
392}
393
394static void tl_dio_setbit(sc, reg, bit)
395 struct tl_softc *sc;
396 int reg;
397 int bit;
398{
399 u_int8_t f;
400
401 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
402 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
403 f |= bit;
404 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
405
406 return;
407}
408
409static void tl_dio_clrbit(sc, reg, bit)
410 struct tl_softc *sc;
411 int reg;
412 int bit;
413{
414 u_int8_t f;
415
416 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
417 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
418 f &= ~bit;
419 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
420
421 return;
422}
423
424static void tl_dio_setbit16(sc, reg, bit)
425 struct tl_softc *sc;
426 int reg;
427 int bit;
428{
429 u_int16_t f;
430
431 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
432 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
433 f |= bit;
434 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
435
436 return;
437}
438
439static void tl_dio_clrbit16(sc, reg, bit)
440 struct tl_softc *sc;
441 int reg;
442 int bit;
443{
444 u_int16_t f;
445
446 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
447 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
448 f &= ~bit;
449 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
450
451 return;
452}
453
454/*
455 * Send an instruction or address to the EEPROM, check for ACK.
456 */
457static u_int8_t tl_eeprom_putbyte(sc, byte)
458 struct tl_softc *sc;
459 int byte;
460{
461 register int i, ack = 0;
462
463 /*
464 * Make sure we're in TX mode.
465 */
466 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN);
467
468 /*
469 * Feed in each bit and stobe the clock.
470 */
471 for (i = 0x80; i; i >>= 1) {
472 if (byte & i) {
473 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA);
474 } else {
475 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA);
476 }
477 DELAY(1);
478 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
479 DELAY(1);
480 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
481 }
482
483 /*
484 * Turn off TX mode.
485 */
486 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
487
488 /*
489 * Check for ack.
490 */
491 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
492 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA;
493 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
494
495 return(ack);
496}
497
498/*
499 * Read a byte of data stored in the EEPROM at address 'addr.'
500 */
501static u_int8_t tl_eeprom_getbyte(sc, addr, dest)
502 struct tl_softc *sc;
503 int addr;
504 u_int8_t *dest;
505{
506 register int i;
507 u_int8_t byte = 0;
508
509 tl_dio_write8(sc, TL_NETSIO, 0);
510
511 EEPROM_START;
512
513 /*
514 * Send write control code to EEPROM.
515 */
516 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
517 printf("tl%d: failed to send write command, status: %x\n",
518 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
519 return(1);
520 }
521
522 /*
523 * Send address of byte we want to read.
524 */
525 if (tl_eeprom_putbyte(sc, addr)) {
526 printf("tl%d: failed to send address, status: %x\n",
527 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
528 return(1);
529 }
530
531 EEPROM_STOP;
532 EEPROM_START;
533 /*
534 * Send read control code to EEPROM.
535 */
536 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
537 printf("tl%d: failed to send write command, status: %x\n",
538 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
539 return(1);
540 }
541
542 /*
543 * Start reading bits from EEPROM.
544 */
545 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
546 for (i = 0x80; i; i >>= 1) {
547 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
548 DELAY(1);
549 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA)
550 byte |= i;
551 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
552 DELAY(1);
553 }
554
555 EEPROM_STOP;
556
557 /*
558 * No ACK generated for read, so just return byte.
559 */
560
561 *dest = byte;
562
563 return(0);
564}
565
566/*
567 * Read a sequence of bytes from the EEPROM.
568 */
569static int tl_read_eeprom(sc, dest, off, cnt)
570 struct tl_softc *sc;
571 caddr_t dest;
572 int off;
573 int cnt;
574{
575 int err = 0, i;
576 u_int8_t byte = 0;
577
578 for (i = 0; i < cnt; i++) {
579 err = tl_eeprom_getbyte(sc, off + i, &byte);
580 if (err)
581 break;
582 *(dest + i) = byte;
583 }
584
585 return(err ? 1 : 0);
586}
587
588static void tl_mii_sync(sc)
589 struct tl_softc *sc;
590{
591 register int i;
592
593 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
594
595 for (i = 0; i < 32; i++) {
596 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
597 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
598 }
599
600 return;
601}
602
603static void tl_mii_send(sc, bits, cnt)
604 struct tl_softc *sc;
605 u_int32_t bits;
606 int cnt;
607{
608 int i;
609
610 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
611 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
612 if (bits & i) {
613 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA);
614 } else {
615 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA);
616 }
617 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
618 }
619}
620
621static int tl_mii_readreg(sc, frame)
622 struct tl_softc *sc;
623 struct tl_mii_frame *frame;
624
625{
626 int i, ack, s;
627 int minten = 0;
628
629 s = splimp();
630
631 tl_mii_sync(sc);
632
633 /*
634 * Set up frame for RX.
635 */
636 frame->mii_stdelim = TL_MII_STARTDELIM;
637 frame->mii_opcode = TL_MII_READOP;
638 frame->mii_turnaround = 0;
639 frame->mii_data = 0;
640
641 /*
642 * Turn off MII interrupt by forcing MINTEN low.
643 */
644 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
645 if (minten) {
646 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
647 }
648
649 /*
650 * Turn on data xmit.
651 */
652 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
653
654 /*
655 * Send command/address info.
656 */
657 tl_mii_send(sc, frame->mii_stdelim, 2);
658 tl_mii_send(sc, frame->mii_opcode, 2);
659 tl_mii_send(sc, frame->mii_phyaddr, 5);
660 tl_mii_send(sc, frame->mii_regaddr, 5);
661
662 /*
663 * Turn off xmit.
664 */
665 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
666
667 /* Idle bit */
668 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
669 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
670
671 /* Check for ack */
672 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
673 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA;
674
675 /* Complete the cycle */
676 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
677
678 /*
679 * Now try reading data bits. If the ack failed, we still
680 * need to clock through 16 cycles to keep the PHYs in sync.
681 */
682 if (ack) {
683 for(i = 0; i < 16; i++) {
684 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
685 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
686 }
687 goto fail;
688 }
689
690 for (i = 0x8000; i; i >>= 1) {
691 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
692 if (!ack) {
693 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA)
694 frame->mii_data |= i;
695 }
696 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
697 }
698
699fail:
700
701 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
702 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
703
704 /* Reenable interrupts */
705 if (minten) {
706 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
707 }
708
709 splx(s);
710
711 if (ack)
712 return(1);
713 return(0);
714}
715
716static int tl_mii_writereg(sc, frame)
717 struct tl_softc *sc;
718 struct tl_mii_frame *frame;
719
720{
721 int s;
722 int minten;
723
724 tl_mii_sync(sc);
725
726 s = splimp();
727 /*
728 * Set up frame for TX.
729 */
730
731 frame->mii_stdelim = TL_MII_STARTDELIM;
732 frame->mii_opcode = TL_MII_WRITEOP;
733 frame->mii_turnaround = TL_MII_TURNAROUND;
734
735 /*
736 * Turn off MII interrupt by forcing MINTEN low.
737 */
738 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
739 if (minten) {
740 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
741 }
742
743 /*
744 * Turn on data output.
745 */
746 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
747
748 tl_mii_send(sc, frame->mii_stdelim, 2);
749 tl_mii_send(sc, frame->mii_opcode, 2);
750 tl_mii_send(sc, frame->mii_phyaddr, 5);
751 tl_mii_send(sc, frame->mii_regaddr, 5);
752 tl_mii_send(sc, frame->mii_turnaround, 2);
753 tl_mii_send(sc, frame->mii_data, 16);
754
755 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
756 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
757
758 /*
759 * Turn off xmit.
760 */
761 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
762
763 /* Reenable interrupts */
764 if (minten)
765 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
766
767 splx(s);
768
769 return(0);
770}
771
772static u_int16_t tl_phy_readreg(sc, reg)
773 struct tl_softc *sc;
774 int reg;
775{
776 struct tl_mii_frame frame;
777
778 bzero((char *)&frame, sizeof(frame));
779
780 frame.mii_phyaddr = sc->tl_phy_addr;
781 frame.mii_regaddr = reg;
782 tl_mii_readreg(sc, &frame);
783
784 /* Reenable MII interrupts, just in case. */
785 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
786
787 return(frame.mii_data);
788}
789
790static void tl_phy_writereg(sc, reg, data)
791 struct tl_softc *sc;
792 int reg;
793 int data;
794{
795 struct tl_mii_frame frame;
796
797 bzero((char *)&frame, sizeof(frame));
798
799 frame.mii_phyaddr = sc->tl_phy_addr;
800 frame.mii_regaddr = reg;
801 frame.mii_data = data;
802
803 tl_mii_writereg(sc, &frame);
804
805 /* Reenable MII interrupts, just in case. */
806 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
807
808 return;
809}
810
811/*
812 * Initiate autonegotiation with a link partner.
813 *
814 * Note that the Texas Instruments ThunderLAN programmer's guide
815 * fails to mention one very important point about autonegotiation.
816 * Autonegotiation is done largely by the PHY, independent of the
817 * ThunderLAN chip itself: the PHY sets the flags in the BMCR
818 * register to indicate what modes were selected and if link status
819 * is good. In fact, the PHY does pretty much all of the work itself,
820 * except for one small detail.
821 *
822 * The PHY may negotiate a full-duplex of half-duplex link, and set
823 * the PHY_BMCR_DUPLEX bit accordingly, but the ThunderLAN's 'NetCommand'
824 * register _also_ has a half-duplex/full-duplex bit, and you MUST ALSO
825 * SET THIS BIT MANUALLY TO CORRESPOND TO THE MODE SELECTED FOR THE PHY!
826 * In other words, both the ThunderLAN chip and the PHY have to be
827 * programmed for full-duplex mode in order for full-duplex to actually
828 * work. So in order for autonegotiation to really work right, we have
829 * to wait for the link to come up, check the BMCR register, then set
830 * the ThunderLAN for full or half-duplex as needed.
831 *
832 * I struggled for two days to figure this out, so I'm making a point
833 * of drawing attention to this fact. I think it's very strange that
834 * the ThunderLAN doesn't automagically track the duplex state of the
835 * PHY, but there you have it.
836 *
837 * Also when, using a National Semiconductor DP83840A PHY, we have to
838 * allow a full three seconds for autonegotiation to complete. So what
839 * we do is flip the autonegotiation restart bit, then set a timeout
840 * to wake us up in three seconds to check the link state.
841 *
842 * Note that there are some versions of the Olicom 2326 that use a
843 * Micro Linear ML6692 100BaseTX PHY. This particular PHY is designed
844 * to provide 100BaseTX support only, but can be used with a controller
845 * that supports an internal 10Mbps PHY to provide a complete
846 * 10/100Mbps solution. However, the ML6692 does not have vendor and
847 * device ID registers, and hence always shows up with a vendor/device
848 * ID of 0.
849 *
850 * We detect this configuration by checking the phy vendor ID in the
851 * softc structure. If it's a zero, and we're negotiating a high-speed
852 * mode, then we turn off the internal PHY. If it's a zero and we've
853 * negotiated a high-speed mode, we turn on the internal PHY. Note
854 * that to make things even more fun, we have to make extra sure that
855 * the loopback bit in the internal PHY's control register is turned
856 * off.
857 */
858static void tl_autoneg(sc, flag, verbose)
859 struct tl_softc *sc;
860 int flag;
861 int verbose;
862{
863 u_int16_t phy_sts = 0, media = 0, advert, ability;
864 struct ifnet *ifp;
865 struct ifmedia *ifm;
866
867 ifm = &sc->ifmedia;
868 ifp = &sc->arpcom.ac_if;
869
870 /*
871 * First, see if autoneg is supported. If not, there's
872 * no point in continuing.
873 */
874 phy_sts = tl_phy_readreg(sc, PHY_BMSR);
875 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
876 if (verbose)
877 printf("tl%d: autonegotiation not supported\n",
878 sc->tl_unit);
879 return;
880 }
881
882 switch (flag) {
883 case TL_FLAG_FORCEDELAY:
884 /*
885 * XXX Never use this option anywhere but in the probe
886 * routine: making the kernel stop dead in its tracks
887 * for three whole seconds after we've gone multi-user
888 * is really bad manners.
889 */
890 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
891 DELAY(500);
892 phy_sts = tl_phy_readreg(sc, PHY_BMCR);
893 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
894 tl_phy_writereg(sc, PHY_BMCR, phy_sts);
895 DELAY(5000000);
896 break;
897 case TL_FLAG_SCHEDDELAY:
898 /*
899 * Wait for the transmitter to go idle before starting
900 * an autoneg session, otherwise tl_start() may clobber
901 * our timeout, and we don't want to allow transmission
902 * during an autoneg session since that can screw it up.
903 */
904 if (!sc->tl_txeoc) {
905 sc->tl_want_auto = 1;
906 return;
907 }
908 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
909 DELAY(500);
910 phy_sts = tl_phy_readreg(sc, PHY_BMCR);
911 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR;
912 tl_phy_writereg(sc, PHY_BMCR, phy_sts);
913 ifp->if_timer = 5;
914 sc->tl_autoneg = 1;
915 sc->tl_want_auto = 0;
916 return;
917 case TL_FLAG_DELAYTIMEO:
918 ifp->if_timer = 0;
919 sc->tl_autoneg = 0;
920 break;
921 default:
922 printf("tl%d: invalid autoneg flag: %d\n", sc->tl_unit, flag);
923 return;
924 }
925
926 /*
927 * Read the BMSR register twice: the LINKSTAT bit is a
928 * latching bit.
929 */
930 tl_phy_readreg(sc, PHY_BMSR);
931 phy_sts = tl_phy_readreg(sc, PHY_BMSR);
932 if (phy_sts & PHY_BMSR_AUTONEGCOMP) {
933 if (verbose)
934 printf("tl%d: autoneg complete, ", sc->tl_unit);
935 phy_sts = tl_phy_readreg(sc, PHY_BMSR);
936 } else {
937 if (verbose)
938 printf("tl%d: autoneg not complete, ", sc->tl_unit);
939 }
940
941 /* Link is good. Report modes and set duplex mode. */
942 if (phy_sts & PHY_BMSR_LINKSTAT) {
943 if (verbose)
944 printf("link status good ");
945
946 advert = tl_phy_readreg(sc, TL_PHY_ANAR);
947 ability = tl_phy_readreg(sc, TL_PHY_LPAR);
948 media = tl_phy_readreg(sc, PHY_BMCR);
949
950 /*
951 * Be sure to turn off the ISOLATE and
952 * LOOPBACK bits in the control register,
953 * otherwise we may not be able to communicate.
954 */
955 media &= ~(PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE);
956 /* Set the DUPLEX bit in the NetCmd register accordingly. */
957 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
958 ifm->ifm_media = IFM_ETHER|IFM_100_T4;
959 media |= PHY_BMCR_SPEEDSEL;
960 media &= ~PHY_BMCR_DUPLEX;
961 if (verbose)
962 printf("(100baseT4)\n");
963 } else if (advert & PHY_ANAR_100BTXFULL &&
964 ability & PHY_ANAR_100BTXFULL) {
965 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX;
966 media |= PHY_BMCR_SPEEDSEL;
967 media |= PHY_BMCR_DUPLEX;
968 if (verbose)
969 printf("(full-duplex, 100Mbps)\n");
970 } else if (advert & PHY_ANAR_100BTXHALF &&
971 ability & PHY_ANAR_100BTXHALF) {
972 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX;
973 media |= PHY_BMCR_SPEEDSEL;
974 media &= ~PHY_BMCR_DUPLEX;
975 if (verbose)
976 printf("(half-duplex, 100Mbps)\n");
977 } else if (advert & PHY_ANAR_10BTFULL &&
978 ability & PHY_ANAR_10BTFULL) {
979 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX;
980 media &= ~PHY_BMCR_SPEEDSEL;
981 media |= PHY_BMCR_DUPLEX;
982 if (verbose)
983 printf("(full-duplex, 10Mbps)\n");
984 } else {
985 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX;
986 media &= ~PHY_BMCR_SPEEDSEL;
987 media &= ~PHY_BMCR_DUPLEX;
988 if (verbose)
989 printf("(half-duplex, 10Mbps)\n");
990 }
991
992 if (media & PHY_BMCR_DUPLEX)
993 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
994 else
995 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
996
997 media &= ~PHY_BMCR_AUTONEGENBL;
998 tl_phy_writereg(sc, PHY_BMCR, media);
999 } else {
1000 if (verbose)
1001 printf("no carrier\n");
1002 }
1003
1004 tl_init(sc);
1005
1006 if (sc->tl_tx_pend) {
1007 sc->tl_autoneg = 0;
1008 sc->tl_tx_pend = 0;
1009 tl_start(ifp);
1010 }
1011
1012 return;
1013}
1014
1015/*
1016 * Set speed and duplex mode. Also program autoneg advertisements
1017 * accordingly.
1018 */
1019static void tl_setmode(sc, media)
1020 struct tl_softc *sc;
1021 int media;
1022{
1023 u_int16_t bmcr;
1024
1025 if (sc->tl_bitrate) {
1026 if (IFM_SUBTYPE(media) == IFM_10_5)
1027 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
1028 if (IFM_SUBTYPE(media) == IFM_10_T) {
1029 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
1030 if ((media & IFM_GMASK) == IFM_FDX) {
1031 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
1032 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
1033 } else {
1034 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
1035 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
1036 }
1037 }
1038 return;
1039 }
1040
1041 bmcr = tl_phy_readreg(sc, PHY_BMCR);
1042
1043 bmcr &= ~(PHY_BMCR_SPEEDSEL|PHY_BMCR_DUPLEX|PHY_BMCR_AUTONEGENBL|
1044 PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE);
1045
1046 if (IFM_SUBTYPE(media) == IFM_LOOP)
1047 bmcr |= PHY_BMCR_LOOPBK;
1048
1049 if (IFM_SUBTYPE(media) == IFM_AUTO)
1050 bmcr |= PHY_BMCR_AUTONEGENBL;
1051
1052 /*
1053 * The ThunderLAN's internal PHY has an AUI transceiver
1054 * that can be selected. This is usually attached to a
1055 * 10base2/BNC port. In order to activate this port, we
1056 * have to set the AUISEL bit in the internal PHY's
1057 * special control register.
1058 */
1059 if (IFM_SUBTYPE(media) == IFM_10_5) {
1060 u_int16_t addr, ctl;
1061 addr = sc->tl_phy_addr;
1062 sc->tl_phy_addr = TL_PHYADDR_MAX;
1063 ctl = tl_phy_readreg(sc, TL_PHY_CTL);
1064 ctl |= PHY_CTL_AUISEL;
1065 tl_phy_writereg(sc, TL_PHY_CTL, ctl);
1066 tl_phy_writereg(sc, PHY_BMCR, bmcr);
1067 sc->tl_phy_addr = addr;
1068 bmcr |= PHY_BMCR_ISOLATE;
1069 } else {
1070 u_int16_t addr, ctl;
1071 addr = sc->tl_phy_addr;
1072 sc->tl_phy_addr = TL_PHYADDR_MAX;
1073 ctl = tl_phy_readreg(sc, TL_PHY_CTL);
1074 ctl &= ~PHY_CTL_AUISEL;
1075 tl_phy_writereg(sc, TL_PHY_CTL, ctl);
1076 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_ISOLATE);
1077 sc->tl_phy_addr = addr;
1078 bmcr &= ~PHY_BMCR_ISOLATE;
1079 }
1080
1081 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1082 bmcr |= PHY_BMCR_SPEEDSEL;
1083 if ((media & IFM_GMASK) == IFM_FDX) {
1084 bmcr |= PHY_BMCR_DUPLEX;
1085 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
1086 } else {
1087 bmcr &= ~PHY_BMCR_DUPLEX;
1088 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
1089 }
1090 }
1091
1092 if (IFM_SUBTYPE(media) == IFM_10_T) {
1093 bmcr &= ~PHY_BMCR_SPEEDSEL;
1094 if ((media & IFM_GMASK) == IFM_FDX) {
1095 bmcr |= PHY_BMCR_DUPLEX;
1096 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
1097 } else {
1098 bmcr &= ~PHY_BMCR_DUPLEX;
1099 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
1100 }
1101 }
1102
1103 tl_phy_writereg(sc, PHY_BMCR, bmcr);
1104
1105 tl_init(sc);
1106
1107 return;
1108}
1109
1110/*
1111 * Calculate the hash of a MAC address for programming the multicast hash
1112 * table. This hash is simply the address split into 6-bit chunks
1113 * XOR'd, e.g.
1114 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
1115 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210
1116 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then
1117 * the folded 24-bit value is split into 6-bit portions and XOR'd.
1118 */
1119static int tl_calchash(addr)
1120 caddr_t addr;
1121{
1122 int t;
1123
1124 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 |
1125 (addr[2] ^ addr[5]);
1126 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f;
1127}
1128
1129/*
1130 * The ThunderLAN has a perfect MAC address filter in addition to
1131 * the multicast hash filter. The perfect filter can be programmed
1132 * with up to four MAC addresses. The first one is always used to
1133 * hold the station address, which leaves us free to use the other
1134 * three for multicast addresses.
1135 */
1136static void tl_setfilt(sc, addr, slot)
1137 struct tl_softc *sc;
1138 caddr_t addr;
1139 int slot;
1140{
1141 int i;
1142 u_int16_t regaddr;
1143
1144 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
1145
1146 for (i = 0; i < ETHER_ADDR_LEN; i++)
1147 tl_dio_write8(sc, regaddr + i, *(addr + i));
1148
1149 return;
1150}
1151
1152/*
1153 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly
1154 * linked list. This is fine, except addresses are added from the head
1155 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts")
1156 * group to always be in the perfect filter, but as more groups are added,
1157 * the 224.0.0.1 entry (which is always added first) gets pushed down
1158 * the list and ends up at the tail. So after 3 or 4 multicast groups
1159 * are added, the all-hosts entry gets pushed out of the perfect filter
1160 * and into the hash table.
1161 *
1162 * Because the multicast list is a doubly-linked list as opposed to a
1163 * circular queue, we don't have the ability to just grab the tail of
1164 * the list and traverse it backwards. Instead, we have to traverse
1165 * the list once to find the tail, then traverse it again backwards to
1166 * update the multicast filter.
1167 */
1168static void tl_setmulti(sc)
1169 struct tl_softc *sc;
1170{
1171 struct ifnet *ifp;
1172 u_int32_t hashes[2] = { 0, 0 };
1173 int h, i;
1174 struct ifmultiaddr *ifma;
1175 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
1176 ifp = &sc->arpcom.ac_if;
1177
1178 /* First, zot all the existing filters. */
1179 for (i = 1; i < 4; i++)
1180 tl_setfilt(sc, (caddr_t)&dummy, i);
1181 tl_dio_write32(sc, TL_HASH1, 0);
1182 tl_dio_write32(sc, TL_HASH2, 0);
1183
1184 /* Now program new ones. */
1185 if (ifp->if_flags & IFF_ALLMULTI) {
1186 hashes[0] = 0xFFFFFFFF;
1187 hashes[1] = 0xFFFFFFFF;
1188 } else {
1189 i = 1;
1190 /* First find the tail of the list. */
1191 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1192 ifma = ifma->ifma_link.le_next) {
1193 if (ifma->ifma_link.le_next == NULL)
1194 break;
1195 }
1196 /* Now traverse the list backwards. */
1197 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
1198 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
1199 if (ifma->ifma_addr->sa_family != AF_LINK)
1200 continue;
1201 /*
1202 * Program the first three multicast groups
1203 * into the perfect filter. For all others,
1204 * use the hash table.
1205 */
1206 if (i < 4) {
1207 tl_setfilt(sc,
1208 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
1209 i++;
1210 continue;
1211 }
1212
1213 h = tl_calchash(
1214 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1215 if (h < 32)
1216 hashes[0] |= (1 << h);
1217 else
1218 hashes[1] |= (1 << (h - 32));
1219 }
1220 }
1221
1222 tl_dio_write32(sc, TL_HASH1, hashes[0]);
1223 tl_dio_write32(sc, TL_HASH2, hashes[1]);
1224
1225 return;
1226}
1227
1228/*
1229 * This routine is recommended by the ThunderLAN manual to insure that
1230 * the internal PHY is powered up correctly. It also recommends a one
1231 * second pause at the end to 'wait for the clocks to start' but in my
1232 * experience this isn't necessary.
1233 */
1234static void tl_hardreset(sc)
1235 struct tl_softc *sc;
1236{
1237 int i;
1238 u_int16_t old_addr, flags;
1239
1240 old_addr = sc->tl_phy_addr;
1241
1242 for (i = 0; i < TL_PHYADDR_MAX + 1; i++) {
1243 sc->tl_phy_addr = i;
1244 tl_mii_sync(sc);
1245 }
1246
1247 flags = PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE|PHY_BMCR_PWRDOWN;
1248
1249 for (i = 0; i < TL_PHYADDR_MAX + 1; i++) {
1250 sc->tl_phy_addr = i;
1251 tl_phy_writereg(sc, PHY_BMCR, flags);
1252 }
1253
1254 sc->tl_phy_addr = TL_PHYADDR_MAX;
1255 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_ISOLATE);
1256
1257 DELAY(50000);
1258
1259 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE);
1260
1261 tl_mii_sync(sc);
1262
1263 while(tl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
1264
1265 sc->tl_phy_addr = old_addr;
1266
1267 return;
1268}
1269
1270static void tl_softreset(sc, internal)
1271 struct tl_softc *sc;
1272 int internal;
1273{
1274 u_int32_t cmd, dummy, i;
1275
1276 /* Assert the adapter reset bit. */
1277 CMD_SET(sc, TL_CMD_ADRST);
1278 /* Turn off interrupts */
1279 CMD_SET(sc, TL_CMD_INTSOFF);
1280
1281 /* First, clear the stats registers. */
1282 for (i = 0; i < 5; i++)
1283 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES);
1284
1285 /* Clear Areg and Hash registers */
1286 for (i = 0; i < 8; i++)
1287 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000);
1288
1289 /*
1290 * Set up Netconfig register. Enable one channel and
1291 * one fragment mode.
1292 */
1293 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG);
1294 if (internal && !sc->tl_bitrate) {
1295 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1296 } else {
1297 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1298 }
1299
1300 /* Handle cards with bitrate devices. */
1301 if (sc->tl_bitrate)
1302 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE);
1303
1304 /* Set PCI burst size */
1305 tl_dio_write8(sc, TL_BSIZEREG, 0x33);
1306
1307 /*
1308 * Load adapter irq pacing timer and tx threshold.
1309 * We make the transmit threshold 1 initially but we may
1310 * change that later.
1311 */
1312 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1313 cmd |= TL_CMD_NES;
1314 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK);
1315 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR));
1316 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003));
1317
1318 /* Unreset the MII */
1319 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
1320
1321 /* Clear status register */
1322 tl_dio_setbit16(sc, TL_NETSTS, TL_STS_MIRQ);
1323 tl_dio_setbit16(sc, TL_NETSTS, TL_STS_HBEAT);
1324 tl_dio_setbit16(sc, TL_NETSTS, TL_STS_TXSTOP);
1325 tl_dio_setbit16(sc, TL_NETSTS, TL_STS_RXSTOP);
1326
1327 /* Enable network status interrupts for everything. */
1328 tl_dio_setbit(sc, TL_NETMASK, TL_MASK_MASK7|TL_MASK_MASK6|
1329 TL_MASK_MASK5|TL_MASK_MASK4);
1330
1331 /* Take the adapter out of reset */
1332 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
1333
1334 /* Wait for things to settle down a little. */
1335 DELAY(500);
1336
1337 return;
1338}
1339
1340/*
1341 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
1342 * against our list and return its name if we find a match.
1343 */
1344static const char *
1345tl_probe(config_id, device_id)
1346 pcici_t config_id;
1347 pcidi_t device_id;
1348{
1349 struct tl_type *t;
1350
1351 t = tl_devs;
1352
1353 while(t->tl_name != NULL) {
1354 if ((device_id & 0xFFFF) == t->tl_vid &&
1355 ((device_id >> 16) & 0xFFFF) == t->tl_did)
1356 return(t->tl_name);
1357 t++;
1358 }
1359
1360 return(NULL);
1361}
1362
1363/*
1364 * Do the interface setup and attach for a PHY on a particular
1365 * ThunderLAN chip. Also also set up interrupt vectors.
1366 */
1367static int tl_attach_phy(sc)
1368 struct tl_softc *sc;
1369{
1370 int phy_ctl;
1371 struct tl_type *p = tl_phys;
1372 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1373 struct ifnet *ifp;
1374
1375 ifp = &sc->arpcom.ac_if;
1376
1377 sc->tl_phy_did = tl_phy_readreg(sc, TL_PHY_DEVID);
1378 sc->tl_phy_vid = tl_phy_readreg(sc, TL_PHY_VENID);
1379 sc->tl_phy_sts = tl_phy_readreg(sc, TL_PHY_GENSTS);
1380 phy_ctl = tl_phy_readreg(sc, TL_PHY_GENCTL);
1381
1382 /*
1383 * PHY revision numbers tend to vary a bit. Our algorithm here
1384 * is to check everything but the 8 least significant bits.
1385 */
1386 while(p->tl_vid) {
1387 if (sc->tl_phy_vid == p->tl_vid &&
1388 (sc->tl_phy_did | 0x000F) == p->tl_did) {
1389 sc->tl_pinfo = p;
1390 break;
1391 }
1392 p++;
1393 }
1394 if (sc->tl_pinfo == NULL) {
1395 sc->tl_pinfo = &tl_phys[PHY_UNKNOWN];
1396 }
1397
1398 if (sc->tl_phy_sts & PHY_BMSR_100BT4 ||
1399 sc->tl_phy_sts & PHY_BMSR_100BTXFULL ||
1400 sc->tl_phy_sts & PHY_BMSR_100BTXHALF)
1401 ifp->if_baudrate = 100000000;
1402 else
1403 ifp->if_baudrate = 10000000;
1404
1405 if (bootverbose) {
1406 printf("tl%d: phy at mii address %d\n", sc->tl_unit,
1407 sc->tl_phy_addr);
1408
1409 printf("tl%d: %s ", sc->tl_unit, sc->tl_pinfo->tl_name);
1410 }
1411
1412 if (sc->tl_phy_sts & PHY_BMSR_100BT4 ||
1413 sc->tl_phy_sts & PHY_BMSR_100BTXHALF ||
1414 sc->tl_phy_sts & PHY_BMSR_100BTXHALF)
1414 sc->tl_phy_sts & PHY_BMSR_100BTXHALF) {
1415 if (bootverbose)
1416 printf("10/100Mbps ");
1415 if (bootverbose)
1416 printf("10/100Mbps ");
1417 else {
1417 } else {
1418 media &= ~IFM_100_TX;
1419 media |= IFM_10_T;
1420 if (bootverbose)
1421 printf("10Mbps ");
1422 }
1423
1424 if (sc->tl_phy_sts & PHY_BMSR_100BTXFULL ||
1418 media &= ~IFM_100_TX;
1419 media |= IFM_10_T;
1420 if (bootverbose)
1421 printf("10Mbps ");
1422 }
1423
1424 if (sc->tl_phy_sts & PHY_BMSR_100BTXFULL ||
1425 sc->tl_phy_sts & PHY_BMSR_10BTFULL)
1425 sc->tl_phy_sts & PHY_BMSR_10BTFULL) {
1426 if (bootverbose)
1427 printf("full duplex ");
1426 if (bootverbose)
1427 printf("full duplex ");
1428 else {
1428 } else {
1429 if (bootverbose)
1430 printf("half duplex ");
1431 media &= ~IFM_FDX;
1432 }
1433
1434 if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG) {
1435 media = IFM_ETHER|IFM_AUTO;
1436 if (bootverbose)
1437 printf("autonegotiating\n");
1438 } else
1439 if (bootverbose)
1440 printf("\n");
1441
1442 /* If this isn't a known PHY, print the PHY indentifier info. */
1443 if (sc->tl_pinfo->tl_vid == 0 && bootverbose)
1444 printf("tl%d: vendor id: %04x product id: %04x\n",
1445 sc->tl_unit, sc->tl_phy_vid, sc->tl_phy_did);
1446
1447 /* Set up ifmedia data and callbacks. */
1448 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
1449
1450 /*
1451 * All ThunderLANs support at least 10baseT half duplex.
1452 * They also support AUI selection if used in 10Mb/s modes.
1453 */
1454 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1455 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1456 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1457
1458 /* Some ThunderLAN PHYs support autonegotiation. */
1459 if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG)
1460 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1461
1462 /* Some support 10baseT full duplex. */
1463 if (sc->tl_phy_sts & PHY_BMSR_10BTFULL)
1464 ifmedia_add(&sc->ifmedia,
1465 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1466
1467 /* Some support 100BaseTX half duplex. */
1468 if (sc->tl_phy_sts & PHY_BMSR_100BTXHALF)
1469 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
1470 if (sc->tl_phy_sts & PHY_BMSR_100BTXHALF)
1471 ifmedia_add(&sc->ifmedia,
1472 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
1473
1474 /* Some support 100BaseTX full duplex. */
1475 if (sc->tl_phy_sts & PHY_BMSR_100BTXFULL)
1476 ifmedia_add(&sc->ifmedia,
1477 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
1478
1479 /* Some also support 100BaseT4. */
1480 if (sc->tl_phy_sts & PHY_BMSR_100BT4)
1481 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL);
1482
1483 /* Set default media. */
1484 ifmedia_set(&sc->ifmedia, media);
1485
1486 /*
1487 * Kick off an autonegotiation session if this PHY supports it.
1488 * This is necessary to make sure the chip's duplex mode matches
1489 * the PHY's duplex mode. It may not: once enabled, the PHY may
1490 * autonegotiate full-duplex mode with its link partner, but the
1491 * ThunderLAN chip defaults to half-duplex and stays there unless
1492 * told otherwise.
1493 */
1494 if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG) {
1495 tl_init(sc);
1496#ifdef TL_BACKGROUND_AUTONEG
1497 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1);
1498#else
1499 tl_autoneg(sc, TL_FLAG_FORCEDELAY, 1);
1500#endif
1501 }
1502
1503 return(0);
1504}
1505
1506static void
1507tl_attach(config_id, unit)
1508 pcici_t config_id;
1509 int unit;
1510{
1511 int s, i, phys = 0;
1512#ifndef TL_USEIOSPACE
1513 vm_offset_t pbase, vbase;
1514#endif
1515 u_int32_t command;
1516 u_int16_t did, vid;
1517 struct tl_type *t;
1518 struct ifnet *ifp;
1519 struct tl_softc *sc;
1520 unsigned int round;
1521 caddr_t roundptr;
1522
1523 s = splimp();
1524
1525 vid = pci_cfgread(config_id, PCIR_VENDOR, 2);
1526 did = pci_cfgread(config_id, PCIR_DEVICE, 2);
1527
1528 t = tl_devs;
1529 while(t->tl_name != NULL) {
1530 if (vid == t->tl_vid && did == t->tl_did)
1531 break;
1532 t++;
1533 }
1534
1535 if (t->tl_name == NULL) {
1536 printf("tl%d: unknown device!?\n", unit);
1537 goto fail;
1538 }
1539
1540 /* First, allocate memory for the softc struct. */
1541 sc = malloc(sizeof(struct tl_softc), M_DEVBUF, M_NOWAIT);
1542 if (sc == NULL) {
1543 printf("tl%d: no memory for softc struct!\n", unit);
1544 goto fail;
1545 }
1546
1547 bzero(sc, sizeof(struct tl_softc));
1548
1549 /*
1550 * Map control/status registers.
1551 */
1552 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1553 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1554 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command);
1555 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1556
1557#ifdef TL_USEIOSPACE
1558 if (!(command & PCIM_CMD_PORTEN)) {
1559 printf("tl%d: failed to enable I/O ports!\n", unit);
1560 free(sc, M_DEVBUF);
1561 goto fail;
1562 }
1563
1564 if (!pci_map_port(config_id, TL_PCI_LOIO,
1565 (u_short *)&(sc->tl_bhandle))) {
1566 if (!pci_map_port(config_id, TL_PCI_LOMEM,
1567 (u_short *)&(sc->tl_bhandle))) {
1568 printf ("tl%d: couldn't map ports\n", unit);
1569 goto fail;
1570 }
1571 }
1572#ifdef __alpha__
1573 sc->tl_btag = ALPHA_BUS_SPACE_IO;
1574#endif
1575#ifdef __i386__
1576 sc->tl_btag = I386_BUS_SPACE_IO;
1577#endif
1578#else
1579 if (!(command & PCIM_CMD_MEMEN)) {
1580 printf("tl%d: failed to enable memory mapping!\n", unit);
1581 goto fail;
1582 }
1583
1584 if (!pci_map_mem(config_id, TL_PCI_LOMEM, &vbase, &pbase)) {
1585 if (!pci_map_mem(config_id, TL_PCI_LOIO, &vbase, &pbase)) {
1586 printf ("tl%d: couldn't map memory\n", unit);
1587 goto fail;
1588 }
1589 }
1590
1591#ifdef __alpha__
1592 sc->tl_btag = ALPHA_BUS_SPACE_MEM;
1593#endif
1594#ifdef __i386__
1595 sc->tl_btag = I386_BUS_SPACE_MEM;
1596#endif
1597 sc->tl_bhandle = vbase;
1598#endif
1599
1600#ifdef notdef
1601 /*
1602 * The ThunderLAN manual suggests jacking the PCI latency
1603 * timer all the way up to its maximum value. I'm not sure
1604 * if this is really necessary, but what the manual wants,
1605 * the manual gets.
1606 */
1607 command = pci_conf_read(config_id, TL_PCI_LATENCY_TIMER);
1608 command |= 0x0000FF00;
1609 pci_conf_write(config_id, TL_PCI_LATENCY_TIMER, command);
1610#endif
1611
1612 /* Allocate interrupt */
1613 if (!pci_map_int(config_id, tl_intr, sc, &net_imask)) {
1614 printf("tl%d: couldn't map interrupt\n", unit);
1615 goto fail;
1616 }
1617
1618 /*
1619 * Now allocate memory for the TX and RX lists. Note that
1620 * we actually allocate 8 bytes more than we really need:
1621 * this is because we need to adjust the final address to
1622 * be aligned on a quadword (64-bit) boundary in order to
1623 * make the chip happy. If the list structures aren't properly
1624 * aligned, DMA fails and the chip generates an adapter check
1625 * interrupt and has to be reset. If you set up the softc struct
1626 * just right you can sort of obtain proper alignment 'by chance.'
1627 * But I don't want to depend on this, so instead the alignment
1628 * is forced here.
1629 */
1630 sc->tl_ldata_ptr = malloc(sizeof(struct tl_list_data) + 8,
1631 M_DEVBUF, M_NOWAIT);
1632
1633 if (sc->tl_ldata_ptr == NULL) {
1634 free(sc, M_DEVBUF);
1635 printf("tl%d: no memory for list buffers!\n", unit);
1636 goto fail;
1637 }
1638
1639 /*
1640 * Convoluted but satisfies my ANSI sensibilities. GCC lets
1641 * you do casts on the LHS of an assignment, but ANSI doesn't
1642 * allow that.
1643 */
1644 sc->tl_ldata = (struct tl_list_data *)sc->tl_ldata_ptr;
1645 round = (unsigned int)sc->tl_ldata_ptr & 0xF;
1646 roundptr = sc->tl_ldata_ptr;
1647 for (i = 0; i < 8; i++) {
1648 if (round % 8) {
1649 round++;
1650 roundptr++;
1651 } else
1652 break;
1653 }
1654 sc->tl_ldata = (struct tl_list_data *)roundptr;
1655
1656 bzero(sc->tl_ldata, sizeof(struct tl_list_data));
1657
1658 sc->tl_unit = unit;
1659 sc->tl_dinfo = t;
1660 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID)
1661 sc->tl_eeaddr = TL_EEPROM_EADDR;
1662 if (t->tl_vid == OLICOM_VENDORID)
1663 sc->tl_eeaddr = TL_EEPROM_EADDR_OC;
1664
1665 /* Reset the adapter. */
1666 tl_softreset(sc, 1);
1667 tl_hardreset(sc);
1668 tl_softreset(sc, 1);
1669
1670 /*
1671 * Get station address from the EEPROM.
1672 */
1673 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1674 sc->tl_eeaddr, ETHER_ADDR_LEN)) {
1675 printf("tl%d: failed to read station address\n", unit);
1676 goto fail;
1677 }
1678
1679 /*
1680 * XXX Olicom, in its desire to be different from the
1681 * rest of the world, has done strange things with the
1682 * encoding of the station address in the EEPROM. First
1683 * of all, they store the address at offset 0xF8 rather
1684 * than at 0x83 like the ThunderLAN manual suggests.
1685 * Second, they store the address in three 16-bit words in
1686 * network byte order, as opposed to storing it sequentially
1687 * like all the other ThunderLAN cards. In order to get
1688 * the station address in a form that matches what the Olicom
1689 * diagnostic utility specifies, we have to byte-swap each
1690 * word. To make things even more confusing, neither 00:00:28
1691 * nor 00:00:24 appear in the IEEE OUI database.
1692 */
1693 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) {
1694 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1695 u_int16_t *p;
1696 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i];
1697 *p = ntohs(*p);
1698 }
1699 }
1700
1701 /*
1702 * A ThunderLAN chip was detected. Inform the world.
1703 */
1704 printf("tl%d: Ethernet address: %6D\n", unit,
1705 sc->arpcom.ac_enaddr, ":");
1706
1707 ifp = &sc->arpcom.ac_if;
1708 ifp->if_softc = sc;
1709 ifp->if_unit = sc->tl_unit;
1710 ifp->if_name = "tl";
1711 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1712 ifp->if_ioctl = tl_ioctl;
1713 ifp->if_output = ether_output;
1714 ifp->if_start = tl_start;
1715 ifp->if_watchdog = tl_watchdog;
1716 ifp->if_init = tl_init;
1717 ifp->if_mtu = ETHERMTU;
1718 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1719 callout_handle_init(&sc->tl_stat_ch);
1720
1721 /* Reset the adapter again. */
1722 tl_softreset(sc, 1);
1723 tl_hardreset(sc);
1724 tl_softreset(sc, 1);
1725
1726 /*
1727 * Now attach the ThunderLAN's PHYs. There will always
1728 * be at least one PHY; if the PHY address is 0x1F, then
1729 * it's the internal one.
1730 */
1731
1732 for (i = TL_PHYADDR_MIN; i < TL_PHYADDR_MAX + 1; i++) {
1733 sc->tl_phy_addr = i;
1734 if (bootverbose)
1735 printf("tl%d: looking for phy at addr %x\n", unit, i);
1736 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
1737 DELAY(500);
1738 while(tl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
1739 sc->tl_phy_sts = tl_phy_readreg(sc, PHY_BMSR);
1740 if (bootverbose)
1741 printf("tl%d: status: %x\n", unit, sc->tl_phy_sts);
1742 if (!sc->tl_phy_sts)
1743 continue;
1744 if (tl_attach_phy(sc)) {
1745 printf("tl%d: failed to attach a phy %d\n", unit, i);
1746 goto fail;
1747 }
1748 phys++;
1749 if (phys && i != TL_PHYADDR_MAX)
1750 break;
1751 }
1752
1753 /*
1754 * If no MII-based PHYs were detected, then this is a
1755 * TNETE110 device with a bit rate PHY. There's no autoneg
1756 * support, so just default to 10baseT mode.
1757 */
1758 if (!phys) {
1759 struct ifmedia *ifm;
1760 sc->tl_bitrate = 1;
1761 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
1762 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1763 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1764 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1765 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1766 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T);
1767 /* Reset again, this time setting bitrate mode. */
1768 tl_softreset(sc, 1);
1769 ifm = &sc->ifmedia;
1770 ifm->ifm_media = ifm->ifm_cur->ifm_media;
1771 tl_ifmedia_upd(ifp);
1772 }
1773
1774 tl_intvec_adchk((void *)sc, 0);
1775 tl_stop(sc);
1776
1777 /*
1778 * Attempt to clear any stray interrupts
1779 * that may be lurking.
1780 */
1781 tl_intr((void *)sc);
1782
1783 /*
1784 * Call MI attach routines.
1785 */
1786 if_attach(ifp);
1787 ether_ifattach(ifp);
1788
1789#if NBPFILTER > 0
1790 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1791#endif
1792
1793 at_shutdown(tl_shutdown, sc, SHUTDOWN_POST_SYNC);
1794
1795fail:
1796 splx(s);
1797 return;
1798}
1799
1800/*
1801 * Initialize the transmit lists.
1802 */
1803static int tl_list_tx_init(sc)
1804 struct tl_softc *sc;
1805{
1806 struct tl_chain_data *cd;
1807 struct tl_list_data *ld;
1808 int i;
1809
1810 cd = &sc->tl_cdata;
1811 ld = sc->tl_ldata;
1812 for (i = 0; i < TL_TX_LIST_CNT; i++) {
1813 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i];
1814 if (i == (TL_TX_LIST_CNT - 1))
1815 cd->tl_tx_chain[i].tl_next = NULL;
1816 else
1817 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1];
1818 }
1819
1820 cd->tl_tx_free = &cd->tl_tx_chain[0];
1821 cd->tl_tx_tail = cd->tl_tx_head = NULL;
1822 sc->tl_txeoc = 1;
1823
1824 return(0);
1825}
1826
1827/*
1828 * Initialize the RX lists and allocate mbufs for them.
1829 */
1830static int tl_list_rx_init(sc)
1831 struct tl_softc *sc;
1832{
1833 struct tl_chain_data *cd;
1834 struct tl_list_data *ld;
1835 int i;
1836
1837 cd = &sc->tl_cdata;
1838 ld = sc->tl_ldata;
1839
1840 for (i = 0; i < TL_RX_LIST_CNT; i++) {
1841 cd->tl_rx_chain[i].tl_ptr =
1842 (struct tl_list_onefrag *)&ld->tl_rx_list[i];
1843 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)
1844 return(ENOBUFS);
1845 if (i == (TL_RX_LIST_CNT - 1)) {
1846 cd->tl_rx_chain[i].tl_next = NULL;
1847 ld->tl_rx_list[i].tlist_fptr = 0;
1848 } else {
1849 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1];
1850 ld->tl_rx_list[i].tlist_fptr =
1851 vtophys(&ld->tl_rx_list[i + 1]);
1852 }
1853 }
1854
1855 cd->tl_rx_head = &cd->tl_rx_chain[0];
1856 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1857
1858 return(0);
1859}
1860
1861static int tl_newbuf(sc, c)
1862 struct tl_softc *sc;
1863 struct tl_chain_onefrag *c;
1864{
1865 struct mbuf *m_new = NULL;
1866
1867 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1868 if (m_new == NULL) {
1869 printf("tl%d: no memory for rx list -- packet dropped!",
1870 sc->tl_unit);
1871 return(ENOBUFS);
1872 }
1873
1874 MCLGET(m_new, M_DONTWAIT);
1875 if (!(m_new->m_flags & M_EXT)) {
1876 printf("tl%d: no memory for rx list -- packet dropped!",
1877 sc->tl_unit);
1878 m_freem(m_new);
1879 return(ENOBUFS);
1880 }
1881
1882#ifdef __alpha__
1883 m_new->m_data += 2;
1884#endif
1885
1886 c->tl_mbuf = m_new;
1887 c->tl_next = NULL;
1888 c->tl_ptr->tlist_frsize = MCLBYTES;
1889 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1890 c->tl_ptr->tlist_fptr = 0;
1891 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t));
1892 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1893
1894 return(0);
1895}
1896/*
1897 * Interrupt handler for RX 'end of frame' condition (EOF). This
1898 * tells us that a full ethernet frame has been captured and we need
1899 * to handle it.
1900 *
1901 * Reception is done using 'lists' which consist of a header and a
1902 * series of 10 data count/data address pairs that point to buffers.
1903 * Initially you're supposed to create a list, populate it with pointers
1904 * to buffers, then load the physical address of the list into the
1905 * ch_parm register. The adapter is then supposed to DMA the received
1906 * frame into the buffers for you.
1907 *
1908 * To make things as fast as possible, we have the chip DMA directly
1909 * into mbufs. This saves us from having to do a buffer copy: we can
1910 * just hand the mbufs directly to ether_input(). Once the frame has
1911 * been sent on its way, the 'list' structure is assigned a new buffer
1912 * and moved to the end of the RX chain. As long we we stay ahead of
1913 * the chip, it will always think it has an endless receive channel.
1914 *
1915 * If we happen to fall behind and the chip manages to fill up all of
1916 * the buffers, it will generate an end of channel interrupt and wait
1917 * for us to empty the chain and restart the receiver.
1918 */
1919static int tl_intvec_rxeof(xsc, type)
1920 void *xsc;
1921 u_int32_t type;
1922{
1923 struct tl_softc *sc;
1924 int r = 0, total_len = 0;
1925 struct ether_header *eh;
1926 struct mbuf *m;
1927 struct ifnet *ifp;
1928 struct tl_chain_onefrag *cur_rx;
1929
1930 sc = xsc;
1931 ifp = &sc->arpcom.ac_if;
1932
1933 while(sc->tl_cdata.tl_rx_head->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP){
1934 r++;
1935 cur_rx = sc->tl_cdata.tl_rx_head;
1936 sc->tl_cdata.tl_rx_head = cur_rx->tl_next;
1937 m = cur_rx->tl_mbuf;
1938 total_len = cur_rx->tl_ptr->tlist_frsize;
1939
1940 if (tl_newbuf(sc, cur_rx) == ENOBUFS) {
1941 ifp->if_ierrors++;
1942 cur_rx->tl_ptr->tlist_frsize = MCLBYTES;
1943 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1944 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1945 continue;
1946 }
1947
1948 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr =
1949 vtophys(cur_rx->tl_ptr);
1950 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx;
1951 sc->tl_cdata.tl_rx_tail = cur_rx;
1952
1953 eh = mtod(m, struct ether_header *);
1954 m->m_pkthdr.rcvif = ifp;
1955
1956 /*
1957 * Note: when the ThunderLAN chip is in 'capture all
1958 * frames' mode, it will receive its own transmissions.
1959 * We drop don't need to process our own transmissions,
1960 * so we drop them here and continue.
1961 */
1962 /*if (ifp->if_flags & IFF_PROMISC && */
1963 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr,
1964 ETHER_ADDR_LEN)) {
1965 m_freem(m);
1966 continue;
1967 }
1968
1969#if NBPFILTER > 0
1970 /*
1971 * Handle BPF listeners. Let the BPF user see the packet, but
1972 * don't pass it up to the ether_input() layer unless it's
1973 * a broadcast packet, multicast packet, matches our ethernet
1974 * address or the interface is in promiscuous mode. If we don't
1975 * want the packet, just forget it. We leave the mbuf in place
1976 * since it can be used again later.
1977 */
1978 if (ifp->if_bpf) {
1979 m->m_pkthdr.len = m->m_len = total_len;
1980 bpf_mtap(ifp, m);
1981 if (ifp->if_flags & IFF_PROMISC &&
1982 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1983 ETHER_ADDR_LEN) &&
1984 (eh->ether_dhost[0] & 1) == 0)) {
1985 m_freem(m);
1986 continue;
1987 }
1988 }
1989#endif
1990 /* Remove header from mbuf and pass it on. */
1991 m->m_pkthdr.len = m->m_len =
1992 total_len - sizeof(struct ether_header);
1993 m->m_data += sizeof(struct ether_header);
1994 ether_input(ifp, eh, m);
1995 }
1996
1997 return(r);
1998}
1999
2000/*
2001 * The RX-EOC condition hits when the ch_parm address hasn't been
2002 * initialized or the adapter reached a list with a forward pointer
2003 * of 0 (which indicates the end of the chain). In our case, this means
2004 * the card has hit the end of the receive buffer chain and we need to
2005 * empty out the buffers and shift the pointer back to the beginning again.
2006 */
2007static int tl_intvec_rxeoc(xsc, type)
2008 void *xsc;
2009 u_int32_t type;
2010{
2011 struct tl_softc *sc;
2012 int r;
2013
2014 sc = xsc;
2015
2016 /* Flush out the receive queue and ack RXEOF interrupts. */
2017 r = tl_intvec_rxeof(xsc, type);
2018 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000)));
2019 r = 1;
2020 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr));
2021 r |= (TL_CMD_GO|TL_CMD_RT);
2022 return(r);
2023}
2024
2025static int tl_intvec_txeof(xsc, type)
2026 void *xsc;
2027 u_int32_t type;
2028{
2029 struct tl_softc *sc;
2030 int r = 0;
2031 struct tl_chain *cur_tx;
2032
2033 sc = xsc;
2034
2035 /*
2036 * Go through our tx list and free mbufs for those
2037 * frames that have been sent.
2038 */
2039 while (sc->tl_cdata.tl_tx_head != NULL) {
2040 cur_tx = sc->tl_cdata.tl_tx_head;
2041 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
2042 break;
2043 sc->tl_cdata.tl_tx_head = cur_tx->tl_next;
2044
2045 r++;
2046 m_freem(cur_tx->tl_mbuf);
2047 cur_tx->tl_mbuf = NULL;
2048
2049 cur_tx->tl_next = sc->tl_cdata.tl_tx_free;
2050 sc->tl_cdata.tl_tx_free = cur_tx;
2051 if (!cur_tx->tl_ptr->tlist_fptr)
2052 break;
2053 }
2054
2055 return(r);
2056}
2057
2058/*
2059 * The transmit end of channel interrupt. The adapter triggers this
2060 * interrupt to tell us it hit the end of the current transmit list.
2061 *
2062 * A note about this: it's possible for a condition to arise where
2063 * tl_start() may try to send frames between TXEOF and TXEOC interrupts.
2064 * You have to avoid this since the chip expects things to go in a
2065 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC.
2066 * When the TXEOF handler is called, it will free all of the transmitted
2067 * frames and reset the tx_head pointer to NULL. However, a TXEOC
2068 * interrupt should be received and acknowledged before any more frames
2069 * are queued for transmission. If tl_statrt() is called after TXEOF
2070 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives,
2071 * it could attempt to issue a transmit command prematurely.
2072 *
2073 * To guard against this, tl_start() will only issue transmit commands
2074 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler
2075 * can set this flag once tl_start() has cleared it.
2076 */
2077static int tl_intvec_txeoc(xsc, type)
2078 void *xsc;
2079 u_int32_t type;
2080{
2081 struct tl_softc *sc;
2082 struct ifnet *ifp;
2083 u_int32_t cmd;
2084
2085 sc = xsc;
2086 ifp = &sc->arpcom.ac_if;
2087
2088 /* Clear the timeout timer. */
2089 ifp->if_timer = 0;
2090
2091 if (sc->tl_cdata.tl_tx_head == NULL) {
2092 ifp->if_flags &= ~IFF_OACTIVE;
2093 sc->tl_cdata.tl_tx_tail = NULL;
2094 sc->tl_txeoc = 1;
2095 /*
2096 * If we just drained the TX queue and
2097 * there's an autoneg request waiting, set
2098 * it in motion. This will block the transmitter
2099 * until the autoneg session completes which will
2100 * no doubt piss off any processes waiting to
2101 * transmit, but that's the way the ball bounces.
2102 */
2103 if (sc->tl_want_auto)
2104 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1);
2105 } else {
2106 sc->tl_txeoc = 0;
2107 /* First we have to ack the EOC interrupt. */
2108 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type);
2109 /* Then load the address of the next TX list. */
2110 CSR_WRITE_4(sc, TL_CH_PARM,
2111 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr));
2112 /* Restart TX channel. */
2113 cmd = CSR_READ_4(sc, TL_HOSTCMD);
2114 cmd &= ~TL_CMD_RT;
2115 cmd |= TL_CMD_GO|TL_CMD_INTSON;
2116 CMD_PUT(sc, cmd);
2117 return(0);
2118 }
2119
2120 return(1);
2121}
2122
2123static int tl_intvec_adchk(xsc, type)
2124 void *xsc;
2125 u_int32_t type;
2126{
2127 struct tl_softc *sc;
2128 u_int16_t bmcr, ctl;
2129
2130 sc = xsc;
2131
2132 if (type)
2133 printf("tl%d: adapter check: %x\n", sc->tl_unit,
2134 (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
2135
2136 /*
2137 * Before resetting the adapter, try reading the PHY
2138 * settings so we can put them back later. This is
2139 * necessary to keep the chip operating at the same
2140 * speed and duplex settings after the reset completes.
2141 */
2142 if (!sc->tl_bitrate) {
2143 bmcr = tl_phy_readreg(sc, PHY_BMCR);
2144 ctl = tl_phy_readreg(sc, TL_PHY_CTL);
2145 tl_softreset(sc, 1);
2146 tl_phy_writereg(sc, PHY_BMCR, bmcr);
2147 tl_phy_writereg(sc, TL_PHY_CTL, ctl);
2148 if (bmcr & PHY_BMCR_DUPLEX) {
2149 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
2150 } else {
2151 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
2152 }
2153 }
2154 tl_stop(sc);
2155 tl_init(sc);
2156 CMD_SET(sc, TL_CMD_INTSON);
2157
2158 return(0);
2159}
2160
2161static int tl_intvec_netsts(xsc, type)
2162 void *xsc;
2163 u_int32_t type;
2164{
2165 struct tl_softc *sc;
2166 u_int16_t netsts;
2167
2168 sc = xsc;
2169
2170 netsts = tl_dio_read16(sc, TL_NETSTS);
2171 tl_dio_write16(sc, TL_NETSTS, netsts);
2172
2173 printf("tl%d: network status: %x\n", sc->tl_unit, netsts);
2174
2175 return(1);
2176}
2177
2178static void tl_intr(xsc)
2179 void *xsc;
2180{
2181 struct tl_softc *sc;
2182 struct ifnet *ifp;
2183 int r = 0;
2184 u_int32_t type = 0;
2185 u_int16_t ints = 0;
2186 u_int8_t ivec = 0;
2187
2188 sc = xsc;
2189
2190 /* Disable interrupts */
2191 ints = CSR_READ_2(sc, TL_HOST_INT);
2192 CSR_WRITE_2(sc, TL_HOST_INT, ints);
2193 type = (ints << 16) & 0xFFFF0000;
2194 ivec = (ints & TL_VEC_MASK) >> 5;
2195 ints = (ints & TL_INT_MASK) >> 2;
2196
2197 ifp = &sc->arpcom.ac_if;
2198
2199 switch(ints) {
2200 case (TL_INTR_INVALID):
2201#ifdef DIAGNOSTIC
2202 printf("tl%d: got an invalid interrupt!\n", sc->tl_unit);
2203#endif
2204 /* Re-enable interrupts but don't ack this one. */
2205 CMD_PUT(sc, type);
2206 r = 0;
2207 break;
2208 case (TL_INTR_TXEOF):
2209 r = tl_intvec_txeof((void *)sc, type);
2210 break;
2211 case (TL_INTR_TXEOC):
2212 r = tl_intvec_txeoc((void *)sc, type);
2213 break;
2214 case (TL_INTR_STATOFLOW):
2215 tl_stats_update(sc);
2216 r = 1;
2217 break;
2218 case (TL_INTR_RXEOF):
2219 r = tl_intvec_rxeof((void *)sc, type);
2220 break;
2221 case (TL_INTR_DUMMY):
2222 printf("tl%d: got a dummy interrupt\n", sc->tl_unit);
2223 r = 1;
2224 break;
2225 case (TL_INTR_ADCHK):
2226 if (ivec)
2227 r = tl_intvec_adchk((void *)sc, type);
2228 else
2229 r = tl_intvec_netsts((void *)sc, type);
2230 break;
2231 case (TL_INTR_RXEOC):
2232 r = tl_intvec_rxeoc((void *)sc, type);
2233 break;
2234 default:
2235 printf("tl%d: bogus interrupt type\n", ifp->if_unit);
2236 break;
2237 }
2238
2239 /* Re-enable interrupts */
2240 if (r) {
2241 CMD_PUT(sc, TL_CMD_ACK | r | type);
2242 }
2243
2244 if (ifp->if_snd.ifq_head != NULL)
2245 tl_start(ifp);
2246
2247 return;
2248}
2249
2250static void tl_stats_update(xsc)
2251 void *xsc;
2252{
2253 struct tl_softc *sc;
2254 struct ifnet *ifp;
2255 struct tl_stats tl_stats;
2256 u_int32_t *p;
2257
2258 bzero((char *)&tl_stats, sizeof(struct tl_stats));
2259
2260 sc = xsc;
2261 ifp = &sc->arpcom.ac_if;
2262
2263 p = (u_int32_t *)&tl_stats;
2264
2265 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);
2266 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
2267 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
2268 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
2269 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
2270 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
2271
2272 ifp->if_opackets += tl_tx_goodframes(tl_stats);
2273 ifp->if_collisions += tl_stats.tl_tx_single_collision +
2274 tl_stats.tl_tx_multi_collision;
2275 ifp->if_ipackets += tl_rx_goodframes(tl_stats);
2276 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors +
2277 tl_rx_overrun(tl_stats);
2278 ifp->if_oerrors += tl_tx_underrun(tl_stats);
2279
2280 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz);
2281
2282 return;
2283}
2284
2285/*
2286 * Encapsulate an mbuf chain in a list by coupling the mbuf data
2287 * pointers to the fragment pointers.
2288 */
2289static int tl_encap(sc, c, m_head)
2290 struct tl_softc *sc;
2291 struct tl_chain *c;
2292 struct mbuf *m_head;
2293{
2294 int frag = 0;
2295 struct tl_frag *f = NULL;
2296 int total_len;
2297 struct mbuf *m;
2298
2299 /*
2300 * Start packing the mbufs in this chain into
2301 * the fragment pointers. Stop when we run out
2302 * of fragments or hit the end of the mbuf chain.
2303 */
2304 m = m_head;
2305 total_len = 0;
2306
2307 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
2308 if (m->m_len != 0) {
2309 if (frag == TL_MAXFRAGS)
2310 break;
2311 total_len+= m->m_len;
2312 c->tl_ptr->tl_frag[frag].tlist_dadr =
2313 vtophys(mtod(m, vm_offset_t));
2314 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len;
2315 frag++;
2316 }
2317 }
2318
2319 /*
2320 * Handle special cases.
2321 * Special case #1: we used up all 10 fragments, but
2322 * we have more mbufs left in the chain. Copy the
2323 * data into an mbuf cluster. Note that we don't
2324 * bother clearing the values in the other fragment
2325 * pointers/counters; it wouldn't gain us anything,
2326 * and would waste cycles.
2327 */
2328 if (m != NULL) {
2329 struct mbuf *m_new = NULL;
2330
2331 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
2332 if (m_new == NULL) {
2333 printf("tl%d: no memory for tx list", sc->tl_unit);
2334 return(1);
2335 }
2336 if (m_head->m_pkthdr.len > MHLEN) {
2337 MCLGET(m_new, M_DONTWAIT);
2338 if (!(m_new->m_flags & M_EXT)) {
2339 m_freem(m_new);
2340 printf("tl%d: no memory for tx list",
2341 sc->tl_unit);
2342 return(1);
2343 }
2344 }
2345 m_copydata(m_head, 0, m_head->m_pkthdr.len,
2346 mtod(m_new, caddr_t));
2347 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
2348 m_freem(m_head);
2349 m_head = m_new;
2350 f = &c->tl_ptr->tl_frag[0];
2351 f->tlist_dadr = vtophys(mtod(m_new, caddr_t));
2352 f->tlist_dcnt = total_len = m_new->m_len;
2353 frag = 1;
2354 }
2355
2356 /*
2357 * Special case #2: the frame is smaller than the minimum
2358 * frame size. We have to pad it to make the chip happy.
2359 */
2360 if (total_len < TL_MIN_FRAMELEN) {
2361 if (frag == TL_MAXFRAGS)
2362 printf("tl%d: all frags filled but "
2363 "frame still to small!\n", sc->tl_unit);
2364 f = &c->tl_ptr->tl_frag[frag];
2365 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len;
2366 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad);
2367 total_len += f->tlist_dcnt;
2368 frag++;
2369 }
2370
2371 c->tl_mbuf = m_head;
2372 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG;
2373 c->tl_ptr->tlist_frsize = total_len;
2374 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
2375 c->tl_ptr->tlist_fptr = 0;
2376
2377 return(0);
2378}
2379
2380/*
2381 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2382 * to the mbuf data regions directly in the transmit lists. We also save a
2383 * copy of the pointers since the transmit list fragment pointers are
2384 * physical addresses.
2385 */
2386static void tl_start(ifp)
2387 struct ifnet *ifp;
2388{
2389 struct tl_softc *sc;
2390 struct mbuf *m_head = NULL;
2391 u_int32_t cmd;
2392 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2393
2394 sc = ifp->if_softc;
2395
2396 if (sc->tl_autoneg) {
2397 sc->tl_tx_pend = 1;
2398 return;
2399 }
2400
2401 /*
2402 * Check for an available queue slot. If there are none,
2403 * punt.
2404 */
2405 if (sc->tl_cdata.tl_tx_free == NULL) {
2406 ifp->if_flags |= IFF_OACTIVE;
2407 return;
2408 }
2409
2410 start_tx = sc->tl_cdata.tl_tx_free;
2411
2412 while(sc->tl_cdata.tl_tx_free != NULL) {
2413 IF_DEQUEUE(&ifp->if_snd, m_head);
2414 if (m_head == NULL)
2415 break;
2416
2417 /* Pick a chain member off the free list. */
2418 cur_tx = sc->tl_cdata.tl_tx_free;
2419 sc->tl_cdata.tl_tx_free = cur_tx->tl_next;
2420
2421 cur_tx->tl_next = NULL;
2422
2423 /* Pack the data into the list. */
2424 tl_encap(sc, cur_tx, m_head);
2425
2426 /* Chain it together */
2427 if (prev != NULL) {
2428 prev->tl_next = cur_tx;
2429 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr);
2430 }
2431 prev = cur_tx;
2432
2433 /*
2434 * If there's a BPF listener, bounce a copy of this frame
2435 * to him.
2436 */
2437#if NBPFILTER > 0
2438 if (ifp->if_bpf)
2439 bpf_mtap(ifp, cur_tx->tl_mbuf);
2440#endif
2441 }
2442
2443 /*
2444 * If there are no packets queued, bail.
2445 */
2446 if (cur_tx == NULL)
2447 return;
2448
2449 /*
2450 * That's all we can stands, we can't stands no more.
2451 * If there are no other transfers pending, then issue the
2452 * TX GO command to the adapter to start things moving.
2453 * Otherwise, just leave the data in the queue and let
2454 * the EOF/EOC interrupt handler send.
2455 */
2456 if (sc->tl_cdata.tl_tx_head == NULL) {
2457 sc->tl_cdata.tl_tx_head = start_tx;
2458 sc->tl_cdata.tl_tx_tail = cur_tx;
2459
2460 if (sc->tl_txeoc) {
2461 sc->tl_txeoc = 0;
2462 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr));
2463 cmd = CSR_READ_4(sc, TL_HOSTCMD);
2464 cmd &= ~TL_CMD_RT;
2465 cmd |= TL_CMD_GO|TL_CMD_INTSON;
2466 CMD_PUT(sc, cmd);
2467 }
2468 } else {
2469 sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
2470 sc->tl_cdata.tl_tx_tail = cur_tx;
2471 }
2472
2473 /*
2474 * Set a timeout in case the chip goes out to lunch.
2475 */
2476 ifp->if_timer = 5;
2477
2478 return;
2479}
2480
2481static void tl_init(xsc)
2482 void *xsc;
2483{
2484 struct tl_softc *sc = xsc;
2485 struct ifnet *ifp = &sc->arpcom.ac_if;
2486 int s;
2487 u_int16_t phy_sts;
2488
2489 if (sc->tl_autoneg)
2490 return;
2491
2492 s = splimp();
2493
2494 ifp = &sc->arpcom.ac_if;
2495
2496 /*
2497 * Cancel pending I/O.
2498 */
2499 tl_stop(sc);
2500
2501 /*
2502 * Set 'capture all frames' bit for promiscuous mode.
2503 */
2504 if (ifp->if_flags & IFF_PROMISC)
2505 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2506 else
2507 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2508
2509 /*
2510 * Set capture broadcast bit to capture broadcast frames.
2511 */
2512 if (ifp->if_flags & IFF_BROADCAST)
2513 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2514 else
2515 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2516
2517 /* Init our MAC address */
2518 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0);
2519
2520 /* Init multicast filter, if needed. */
2521 tl_setmulti(sc);
2522
2523 /* Init circular RX list. */
2524 if (tl_list_rx_init(sc) == ENOBUFS) {
2525 printf("tl%d: initialization failed: no "
2526 "memory for rx buffers\n", sc->tl_unit);
2527 tl_stop(sc);
2528 return;
2529 }
2530
2531 /* Init TX pointers. */
2532 tl_list_tx_init(sc);
2533
2534 /*
2535 * Enable PHY interrupts.
2536 */
2537 phy_sts = tl_phy_readreg(sc, TL_PHY_CTL);
2538 phy_sts |= PHY_CTL_INTEN;
2539 tl_phy_writereg(sc, TL_PHY_CTL, phy_sts);
2540
2541 /* Enable MII interrupts. */
2542 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
2543
2544 /* Enable PCI interrupts. */
2545 CMD_SET(sc, TL_CMD_INTSON);
2546
2547 /* Load the address of the rx list */
2548 CMD_SET(sc, TL_CMD_RT);
2549 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0]));
2550
2551 /*
2552 * XXX This is a kludge to handle adapters with the Micro Linear
2553 * ML6692 100BaseTX PHY, which only supports 100Mbps modes and
2554 * relies on the controller's internal 10Mbps PHY to provide
2555 * 10Mbps modes. The ML6692 always shows up with a vendor/device ID
2556 * of 0 (it doesn't actually have vendor/device ID registers)
2557 * so we use that property to detect it. In theory there ought to
2558 * be a better way to 'spot the looney' but I can't find one.
2559 */
2560 if (!sc->tl_phy_vid) {
2561 u_int8_t addr = 0;
2562 u_int16_t bmcr;
2563
2564 bmcr = tl_phy_readreg(sc, PHY_BMCR);
2565 addr = sc->tl_phy_addr;
2566 sc->tl_phy_addr = TL_PHYADDR_MAX;
2567 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
2568 if (bmcr & PHY_BMCR_SPEEDSEL)
2569 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_ISOLATE);
2570 else
2571 tl_phy_writereg(sc, PHY_BMCR, bmcr);
2572 sc->tl_phy_addr = addr;
2573 }
2574
2575 /* Send the RX go command */
2576 CMD_SET(sc, TL_CMD_GO|TL_CMD_RT);
2577
2578 ifp->if_flags |= IFF_RUNNING;
2579 ifp->if_flags &= ~IFF_OACTIVE;
2580
2581 (void)splx(s);
2582
2583 /* Start the stats update counter */
2584 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz);
2585
2586 return;
2587}
2588
2589/*
2590 * Set media options.
2591 */
2592static int tl_ifmedia_upd(ifp)
2593 struct ifnet *ifp;
2594{
2595 struct tl_softc *sc;
2596 struct ifmedia *ifm;
2597
2598 sc = ifp->if_softc;
2599 ifm = &sc->ifmedia;
2600
2601 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2602 return(EINVAL);
2603
2604 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
2605 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1);
2606 else
2607 tl_setmode(sc, ifm->ifm_media);
2608
2609 return(0);
2610}
2611
2612/*
2613 * Report current media status.
2614 */
2615static void tl_ifmedia_sts(ifp, ifmr)
2616 struct ifnet *ifp;
2617 struct ifmediareq *ifmr;
2618{
2619 u_int16_t phy_ctl;
2620 u_int16_t phy_sts;
2621 struct tl_softc *sc;
2622
2623 sc = ifp->if_softc;
2624
2625 ifmr->ifm_active = IFM_ETHER;
2626
2627 if (sc->tl_bitrate) {
2628 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1)
2629 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2630 else
2631 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2632 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3)
2633 ifmr->ifm_active |= IFM_HDX;
2634 else
2635 ifmr->ifm_active |= IFM_FDX;
2636 return;
2637 }
2638
2639 phy_ctl = tl_phy_readreg(sc, PHY_BMCR);
2640 phy_sts = tl_phy_readreg(sc, TL_PHY_CTL);
2641
2642 if (phy_sts & PHY_CTL_AUISEL)
2643 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2644
2645 if (phy_ctl & PHY_BMCR_LOOPBK)
2646 ifmr->ifm_active = IFM_ETHER|IFM_LOOP;
2647
2648 if (phy_ctl & PHY_BMCR_SPEEDSEL)
2649 ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
2650 else
2651 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2652
2653 if (phy_ctl & PHY_BMCR_DUPLEX) {
2654 ifmr->ifm_active |= IFM_FDX;
2655 ifmr->ifm_active &= ~IFM_HDX;
2656 } else {
2657 ifmr->ifm_active &= ~IFM_FDX;
2658 ifmr->ifm_active |= IFM_HDX;
2659 }
2660
2661 return;
2662}
2663
2664static int tl_ioctl(ifp, command, data)
2665 struct ifnet *ifp;
2666 u_long command;
2667 caddr_t data;
2668{
2669 struct tl_softc *sc = ifp->if_softc;
2670 struct ifreq *ifr = (struct ifreq *) data;
2671 int s, error = 0;
2672
2673 s = splimp();
2674
2675 switch(command) {
2676 case SIOCSIFADDR:
2677 case SIOCGIFADDR:
2678 case SIOCSIFMTU:
2679 error = ether_ioctl(ifp, command, data);
2680 break;
2681 case SIOCSIFFLAGS:
2682 if (ifp->if_flags & IFF_UP) {
2683 tl_init(sc);
2684 } else {
2685 if (ifp->if_flags & IFF_RUNNING) {
2686 tl_stop(sc);
2687 }
2688 }
2689 error = 0;
2690 break;
2691 case SIOCADDMULTI:
2692 case SIOCDELMULTI:
2693 tl_setmulti(sc);
2694 error = 0;
2695 break;
2696 case SIOCSIFMEDIA:
2697 case SIOCGIFMEDIA:
2698 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2699 break;
2700 default:
2701 error = EINVAL;
2702 break;
2703 }
2704
2705 (void)splx(s);
2706
2707 return(error);
2708}
2709
2710static void tl_watchdog(ifp)
2711 struct ifnet *ifp;
2712{
2713 struct tl_softc *sc;
2714 u_int16_t bmsr;
2715
2716 sc = ifp->if_softc;
2717
2718 if (sc->tl_autoneg) {
2719 tl_autoneg(sc, TL_FLAG_DELAYTIMEO, 1);
2720 return;
2721 }
2722
2723 /* Check that we're still connected. */
2724 tl_phy_readreg(sc, PHY_BMSR);
2725 bmsr = tl_phy_readreg(sc, PHY_BMSR);
2726 if (!(bmsr & PHY_BMSR_LINKSTAT)) {
2727 printf("tl%d: no carrier\n", sc->tl_unit);
2728 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1);
2729 } else
2730 printf("tl%d: device timeout\n", sc->tl_unit);
2731
2732 ifp->if_oerrors++;
2733
2734 tl_init(sc);
2735
2736 return;
2737}
2738
2739/*
2740 * Stop the adapter and free any mbufs allocated to the
2741 * RX and TX lists.
2742 */
2743static void tl_stop(sc)
2744 struct tl_softc *sc;
2745{
2746 register int i;
2747 struct ifnet *ifp;
2748
2749 ifp = &sc->arpcom.ac_if;
2750
2751 /* Stop the stats updater. */
2752 untimeout(tl_stats_update, sc, sc->tl_stat_ch);
2753
2754 /* Stop the transmitter */
2755 CMD_CLR(sc, TL_CMD_RT);
2756 CMD_SET(sc, TL_CMD_STOP);
2757 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2758
2759 /* Stop the receiver */
2760 CMD_SET(sc, TL_CMD_RT);
2761 CMD_SET(sc, TL_CMD_STOP);
2762 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2763
2764 /*
2765 * Disable host interrupts.
2766 */
2767 CMD_SET(sc, TL_CMD_INTSOFF);
2768
2769 /*
2770 * Disable MII interrupts.
2771 */
2772 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
2773
2774 /*
2775 * Clear list pointer.
2776 */
2777 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2778
2779 /*
2780 * Free the RX lists.
2781 */
2782 for (i = 0; i < TL_RX_LIST_CNT; i++) {
2783 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) {
2784 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf);
2785 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL;
2786 }
2787 }
2788 bzero((char *)&sc->tl_ldata->tl_rx_list,
2789 sizeof(sc->tl_ldata->tl_rx_list));
2790
2791 /*
2792 * Free the TX list buffers.
2793 */
2794 for (i = 0; i < TL_TX_LIST_CNT; i++) {
2795 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) {
2796 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
2797 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
2798 }
2799 }
2800 bzero((char *)&sc->tl_ldata->tl_tx_list,
2801 sizeof(sc->tl_ldata->tl_tx_list));
2802
2803 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2804
2805 return;
2806}
2807
2808/*
2809 * Stop all chip I/O so that the kernel's probe routines don't
2810 * get confused by errant DMAs when rebooting.
2811 */
2812static void tl_shutdown(howto, xsc)
2813 int howto;
2814 void *xsc;
2815{
2816 struct tl_softc *sc;
2817
2818 sc = xsc;
2819
2820 tl_stop(sc);
2821
2822 return;
2823}
2824
2825
2826static struct pci_device tl_device = {
2827 "tl",
2828 tl_probe,
2829 tl_attach,
2830 &tl_count,
2831 NULL
2832};
2833#ifdef COMPAT_PCI_DRIVER
2834COMPAT_PCI_DRIVER(tl, tl_device);
2835#else
2836DATA_SET(pcidevice_set, tl_device);
2837#endif /* COMPAT_PCI_DRIVER */
1429 if (bootverbose)
1430 printf("half duplex ");
1431 media &= ~IFM_FDX;
1432 }
1433
1434 if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG) {
1435 media = IFM_ETHER|IFM_AUTO;
1436 if (bootverbose)
1437 printf("autonegotiating\n");
1438 } else
1439 if (bootverbose)
1440 printf("\n");
1441
1442 /* If this isn't a known PHY, print the PHY indentifier info. */
1443 if (sc->tl_pinfo->tl_vid == 0 && bootverbose)
1444 printf("tl%d: vendor id: %04x product id: %04x\n",
1445 sc->tl_unit, sc->tl_phy_vid, sc->tl_phy_did);
1446
1447 /* Set up ifmedia data and callbacks. */
1448 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
1449
1450 /*
1451 * All ThunderLANs support at least 10baseT half duplex.
1452 * They also support AUI selection if used in 10Mb/s modes.
1453 */
1454 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1455 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1456 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1457
1458 /* Some ThunderLAN PHYs support autonegotiation. */
1459 if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG)
1460 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1461
1462 /* Some support 10baseT full duplex. */
1463 if (sc->tl_phy_sts & PHY_BMSR_10BTFULL)
1464 ifmedia_add(&sc->ifmedia,
1465 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1466
1467 /* Some support 100BaseTX half duplex. */
1468 if (sc->tl_phy_sts & PHY_BMSR_100BTXHALF)
1469 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
1470 if (sc->tl_phy_sts & PHY_BMSR_100BTXHALF)
1471 ifmedia_add(&sc->ifmedia,
1472 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
1473
1474 /* Some support 100BaseTX full duplex. */
1475 if (sc->tl_phy_sts & PHY_BMSR_100BTXFULL)
1476 ifmedia_add(&sc->ifmedia,
1477 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
1478
1479 /* Some also support 100BaseT4. */
1480 if (sc->tl_phy_sts & PHY_BMSR_100BT4)
1481 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL);
1482
1483 /* Set default media. */
1484 ifmedia_set(&sc->ifmedia, media);
1485
1486 /*
1487 * Kick off an autonegotiation session if this PHY supports it.
1488 * This is necessary to make sure the chip's duplex mode matches
1489 * the PHY's duplex mode. It may not: once enabled, the PHY may
1490 * autonegotiate full-duplex mode with its link partner, but the
1491 * ThunderLAN chip defaults to half-duplex and stays there unless
1492 * told otherwise.
1493 */
1494 if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG) {
1495 tl_init(sc);
1496#ifdef TL_BACKGROUND_AUTONEG
1497 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1);
1498#else
1499 tl_autoneg(sc, TL_FLAG_FORCEDELAY, 1);
1500#endif
1501 }
1502
1503 return(0);
1504}
1505
1506static void
1507tl_attach(config_id, unit)
1508 pcici_t config_id;
1509 int unit;
1510{
1511 int s, i, phys = 0;
1512#ifndef TL_USEIOSPACE
1513 vm_offset_t pbase, vbase;
1514#endif
1515 u_int32_t command;
1516 u_int16_t did, vid;
1517 struct tl_type *t;
1518 struct ifnet *ifp;
1519 struct tl_softc *sc;
1520 unsigned int round;
1521 caddr_t roundptr;
1522
1523 s = splimp();
1524
1525 vid = pci_cfgread(config_id, PCIR_VENDOR, 2);
1526 did = pci_cfgread(config_id, PCIR_DEVICE, 2);
1527
1528 t = tl_devs;
1529 while(t->tl_name != NULL) {
1530 if (vid == t->tl_vid && did == t->tl_did)
1531 break;
1532 t++;
1533 }
1534
1535 if (t->tl_name == NULL) {
1536 printf("tl%d: unknown device!?\n", unit);
1537 goto fail;
1538 }
1539
1540 /* First, allocate memory for the softc struct. */
1541 sc = malloc(sizeof(struct tl_softc), M_DEVBUF, M_NOWAIT);
1542 if (sc == NULL) {
1543 printf("tl%d: no memory for softc struct!\n", unit);
1544 goto fail;
1545 }
1546
1547 bzero(sc, sizeof(struct tl_softc));
1548
1549 /*
1550 * Map control/status registers.
1551 */
1552 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1553 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1554 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command);
1555 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
1556
1557#ifdef TL_USEIOSPACE
1558 if (!(command & PCIM_CMD_PORTEN)) {
1559 printf("tl%d: failed to enable I/O ports!\n", unit);
1560 free(sc, M_DEVBUF);
1561 goto fail;
1562 }
1563
1564 if (!pci_map_port(config_id, TL_PCI_LOIO,
1565 (u_short *)&(sc->tl_bhandle))) {
1566 if (!pci_map_port(config_id, TL_PCI_LOMEM,
1567 (u_short *)&(sc->tl_bhandle))) {
1568 printf ("tl%d: couldn't map ports\n", unit);
1569 goto fail;
1570 }
1571 }
1572#ifdef __alpha__
1573 sc->tl_btag = ALPHA_BUS_SPACE_IO;
1574#endif
1575#ifdef __i386__
1576 sc->tl_btag = I386_BUS_SPACE_IO;
1577#endif
1578#else
1579 if (!(command & PCIM_CMD_MEMEN)) {
1580 printf("tl%d: failed to enable memory mapping!\n", unit);
1581 goto fail;
1582 }
1583
1584 if (!pci_map_mem(config_id, TL_PCI_LOMEM, &vbase, &pbase)) {
1585 if (!pci_map_mem(config_id, TL_PCI_LOIO, &vbase, &pbase)) {
1586 printf ("tl%d: couldn't map memory\n", unit);
1587 goto fail;
1588 }
1589 }
1590
1591#ifdef __alpha__
1592 sc->tl_btag = ALPHA_BUS_SPACE_MEM;
1593#endif
1594#ifdef __i386__
1595 sc->tl_btag = I386_BUS_SPACE_MEM;
1596#endif
1597 sc->tl_bhandle = vbase;
1598#endif
1599
1600#ifdef notdef
1601 /*
1602 * The ThunderLAN manual suggests jacking the PCI latency
1603 * timer all the way up to its maximum value. I'm not sure
1604 * if this is really necessary, but what the manual wants,
1605 * the manual gets.
1606 */
1607 command = pci_conf_read(config_id, TL_PCI_LATENCY_TIMER);
1608 command |= 0x0000FF00;
1609 pci_conf_write(config_id, TL_PCI_LATENCY_TIMER, command);
1610#endif
1611
1612 /* Allocate interrupt */
1613 if (!pci_map_int(config_id, tl_intr, sc, &net_imask)) {
1614 printf("tl%d: couldn't map interrupt\n", unit);
1615 goto fail;
1616 }
1617
1618 /*
1619 * Now allocate memory for the TX and RX lists. Note that
1620 * we actually allocate 8 bytes more than we really need:
1621 * this is because we need to adjust the final address to
1622 * be aligned on a quadword (64-bit) boundary in order to
1623 * make the chip happy. If the list structures aren't properly
1624 * aligned, DMA fails and the chip generates an adapter check
1625 * interrupt and has to be reset. If you set up the softc struct
1626 * just right you can sort of obtain proper alignment 'by chance.'
1627 * But I don't want to depend on this, so instead the alignment
1628 * is forced here.
1629 */
1630 sc->tl_ldata_ptr = malloc(sizeof(struct tl_list_data) + 8,
1631 M_DEVBUF, M_NOWAIT);
1632
1633 if (sc->tl_ldata_ptr == NULL) {
1634 free(sc, M_DEVBUF);
1635 printf("tl%d: no memory for list buffers!\n", unit);
1636 goto fail;
1637 }
1638
1639 /*
1640 * Convoluted but satisfies my ANSI sensibilities. GCC lets
1641 * you do casts on the LHS of an assignment, but ANSI doesn't
1642 * allow that.
1643 */
1644 sc->tl_ldata = (struct tl_list_data *)sc->tl_ldata_ptr;
1645 round = (unsigned int)sc->tl_ldata_ptr & 0xF;
1646 roundptr = sc->tl_ldata_ptr;
1647 for (i = 0; i < 8; i++) {
1648 if (round % 8) {
1649 round++;
1650 roundptr++;
1651 } else
1652 break;
1653 }
1654 sc->tl_ldata = (struct tl_list_data *)roundptr;
1655
1656 bzero(sc->tl_ldata, sizeof(struct tl_list_data));
1657
1658 sc->tl_unit = unit;
1659 sc->tl_dinfo = t;
1660 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID)
1661 sc->tl_eeaddr = TL_EEPROM_EADDR;
1662 if (t->tl_vid == OLICOM_VENDORID)
1663 sc->tl_eeaddr = TL_EEPROM_EADDR_OC;
1664
1665 /* Reset the adapter. */
1666 tl_softreset(sc, 1);
1667 tl_hardreset(sc);
1668 tl_softreset(sc, 1);
1669
1670 /*
1671 * Get station address from the EEPROM.
1672 */
1673 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1674 sc->tl_eeaddr, ETHER_ADDR_LEN)) {
1675 printf("tl%d: failed to read station address\n", unit);
1676 goto fail;
1677 }
1678
1679 /*
1680 * XXX Olicom, in its desire to be different from the
1681 * rest of the world, has done strange things with the
1682 * encoding of the station address in the EEPROM. First
1683 * of all, they store the address at offset 0xF8 rather
1684 * than at 0x83 like the ThunderLAN manual suggests.
1685 * Second, they store the address in three 16-bit words in
1686 * network byte order, as opposed to storing it sequentially
1687 * like all the other ThunderLAN cards. In order to get
1688 * the station address in a form that matches what the Olicom
1689 * diagnostic utility specifies, we have to byte-swap each
1690 * word. To make things even more confusing, neither 00:00:28
1691 * nor 00:00:24 appear in the IEEE OUI database.
1692 */
1693 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) {
1694 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1695 u_int16_t *p;
1696 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i];
1697 *p = ntohs(*p);
1698 }
1699 }
1700
1701 /*
1702 * A ThunderLAN chip was detected. Inform the world.
1703 */
1704 printf("tl%d: Ethernet address: %6D\n", unit,
1705 sc->arpcom.ac_enaddr, ":");
1706
1707 ifp = &sc->arpcom.ac_if;
1708 ifp->if_softc = sc;
1709 ifp->if_unit = sc->tl_unit;
1710 ifp->if_name = "tl";
1711 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1712 ifp->if_ioctl = tl_ioctl;
1713 ifp->if_output = ether_output;
1714 ifp->if_start = tl_start;
1715 ifp->if_watchdog = tl_watchdog;
1716 ifp->if_init = tl_init;
1717 ifp->if_mtu = ETHERMTU;
1718 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1719 callout_handle_init(&sc->tl_stat_ch);
1720
1721 /* Reset the adapter again. */
1722 tl_softreset(sc, 1);
1723 tl_hardreset(sc);
1724 tl_softreset(sc, 1);
1725
1726 /*
1727 * Now attach the ThunderLAN's PHYs. There will always
1728 * be at least one PHY; if the PHY address is 0x1F, then
1729 * it's the internal one.
1730 */
1731
1732 for (i = TL_PHYADDR_MIN; i < TL_PHYADDR_MAX + 1; i++) {
1733 sc->tl_phy_addr = i;
1734 if (bootverbose)
1735 printf("tl%d: looking for phy at addr %x\n", unit, i);
1736 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
1737 DELAY(500);
1738 while(tl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
1739 sc->tl_phy_sts = tl_phy_readreg(sc, PHY_BMSR);
1740 if (bootverbose)
1741 printf("tl%d: status: %x\n", unit, sc->tl_phy_sts);
1742 if (!sc->tl_phy_sts)
1743 continue;
1744 if (tl_attach_phy(sc)) {
1745 printf("tl%d: failed to attach a phy %d\n", unit, i);
1746 goto fail;
1747 }
1748 phys++;
1749 if (phys && i != TL_PHYADDR_MAX)
1750 break;
1751 }
1752
1753 /*
1754 * If no MII-based PHYs were detected, then this is a
1755 * TNETE110 device with a bit rate PHY. There's no autoneg
1756 * support, so just default to 10baseT mode.
1757 */
1758 if (!phys) {
1759 struct ifmedia *ifm;
1760 sc->tl_bitrate = 1;
1761 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
1762 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1763 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1764 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1765 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1766 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T);
1767 /* Reset again, this time setting bitrate mode. */
1768 tl_softreset(sc, 1);
1769 ifm = &sc->ifmedia;
1770 ifm->ifm_media = ifm->ifm_cur->ifm_media;
1771 tl_ifmedia_upd(ifp);
1772 }
1773
1774 tl_intvec_adchk((void *)sc, 0);
1775 tl_stop(sc);
1776
1777 /*
1778 * Attempt to clear any stray interrupts
1779 * that may be lurking.
1780 */
1781 tl_intr((void *)sc);
1782
1783 /*
1784 * Call MI attach routines.
1785 */
1786 if_attach(ifp);
1787 ether_ifattach(ifp);
1788
1789#if NBPFILTER > 0
1790 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
1791#endif
1792
1793 at_shutdown(tl_shutdown, sc, SHUTDOWN_POST_SYNC);
1794
1795fail:
1796 splx(s);
1797 return;
1798}
1799
1800/*
1801 * Initialize the transmit lists.
1802 */
1803static int tl_list_tx_init(sc)
1804 struct tl_softc *sc;
1805{
1806 struct tl_chain_data *cd;
1807 struct tl_list_data *ld;
1808 int i;
1809
1810 cd = &sc->tl_cdata;
1811 ld = sc->tl_ldata;
1812 for (i = 0; i < TL_TX_LIST_CNT; i++) {
1813 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i];
1814 if (i == (TL_TX_LIST_CNT - 1))
1815 cd->tl_tx_chain[i].tl_next = NULL;
1816 else
1817 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1];
1818 }
1819
1820 cd->tl_tx_free = &cd->tl_tx_chain[0];
1821 cd->tl_tx_tail = cd->tl_tx_head = NULL;
1822 sc->tl_txeoc = 1;
1823
1824 return(0);
1825}
1826
1827/*
1828 * Initialize the RX lists and allocate mbufs for them.
1829 */
1830static int tl_list_rx_init(sc)
1831 struct tl_softc *sc;
1832{
1833 struct tl_chain_data *cd;
1834 struct tl_list_data *ld;
1835 int i;
1836
1837 cd = &sc->tl_cdata;
1838 ld = sc->tl_ldata;
1839
1840 for (i = 0; i < TL_RX_LIST_CNT; i++) {
1841 cd->tl_rx_chain[i].tl_ptr =
1842 (struct tl_list_onefrag *)&ld->tl_rx_list[i];
1843 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)
1844 return(ENOBUFS);
1845 if (i == (TL_RX_LIST_CNT - 1)) {
1846 cd->tl_rx_chain[i].tl_next = NULL;
1847 ld->tl_rx_list[i].tlist_fptr = 0;
1848 } else {
1849 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1];
1850 ld->tl_rx_list[i].tlist_fptr =
1851 vtophys(&ld->tl_rx_list[i + 1]);
1852 }
1853 }
1854
1855 cd->tl_rx_head = &cd->tl_rx_chain[0];
1856 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1857
1858 return(0);
1859}
1860
1861static int tl_newbuf(sc, c)
1862 struct tl_softc *sc;
1863 struct tl_chain_onefrag *c;
1864{
1865 struct mbuf *m_new = NULL;
1866
1867 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1868 if (m_new == NULL) {
1869 printf("tl%d: no memory for rx list -- packet dropped!",
1870 sc->tl_unit);
1871 return(ENOBUFS);
1872 }
1873
1874 MCLGET(m_new, M_DONTWAIT);
1875 if (!(m_new->m_flags & M_EXT)) {
1876 printf("tl%d: no memory for rx list -- packet dropped!",
1877 sc->tl_unit);
1878 m_freem(m_new);
1879 return(ENOBUFS);
1880 }
1881
1882#ifdef __alpha__
1883 m_new->m_data += 2;
1884#endif
1885
1886 c->tl_mbuf = m_new;
1887 c->tl_next = NULL;
1888 c->tl_ptr->tlist_frsize = MCLBYTES;
1889 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1890 c->tl_ptr->tlist_fptr = 0;
1891 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t));
1892 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1893
1894 return(0);
1895}
1896/*
1897 * Interrupt handler for RX 'end of frame' condition (EOF). This
1898 * tells us that a full ethernet frame has been captured and we need
1899 * to handle it.
1900 *
1901 * Reception is done using 'lists' which consist of a header and a
1902 * series of 10 data count/data address pairs that point to buffers.
1903 * Initially you're supposed to create a list, populate it with pointers
1904 * to buffers, then load the physical address of the list into the
1905 * ch_parm register. The adapter is then supposed to DMA the received
1906 * frame into the buffers for you.
1907 *
1908 * To make things as fast as possible, we have the chip DMA directly
1909 * into mbufs. This saves us from having to do a buffer copy: we can
1910 * just hand the mbufs directly to ether_input(). Once the frame has
1911 * been sent on its way, the 'list' structure is assigned a new buffer
1912 * and moved to the end of the RX chain. As long we we stay ahead of
1913 * the chip, it will always think it has an endless receive channel.
1914 *
1915 * If we happen to fall behind and the chip manages to fill up all of
1916 * the buffers, it will generate an end of channel interrupt and wait
1917 * for us to empty the chain and restart the receiver.
1918 */
1919static int tl_intvec_rxeof(xsc, type)
1920 void *xsc;
1921 u_int32_t type;
1922{
1923 struct tl_softc *sc;
1924 int r = 0, total_len = 0;
1925 struct ether_header *eh;
1926 struct mbuf *m;
1927 struct ifnet *ifp;
1928 struct tl_chain_onefrag *cur_rx;
1929
1930 sc = xsc;
1931 ifp = &sc->arpcom.ac_if;
1932
1933 while(sc->tl_cdata.tl_rx_head->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP){
1934 r++;
1935 cur_rx = sc->tl_cdata.tl_rx_head;
1936 sc->tl_cdata.tl_rx_head = cur_rx->tl_next;
1937 m = cur_rx->tl_mbuf;
1938 total_len = cur_rx->tl_ptr->tlist_frsize;
1939
1940 if (tl_newbuf(sc, cur_rx) == ENOBUFS) {
1941 ifp->if_ierrors++;
1942 cur_rx->tl_ptr->tlist_frsize = MCLBYTES;
1943 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1944 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1945 continue;
1946 }
1947
1948 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr =
1949 vtophys(cur_rx->tl_ptr);
1950 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx;
1951 sc->tl_cdata.tl_rx_tail = cur_rx;
1952
1953 eh = mtod(m, struct ether_header *);
1954 m->m_pkthdr.rcvif = ifp;
1955
1956 /*
1957 * Note: when the ThunderLAN chip is in 'capture all
1958 * frames' mode, it will receive its own transmissions.
1959 * We drop don't need to process our own transmissions,
1960 * so we drop them here and continue.
1961 */
1962 /*if (ifp->if_flags & IFF_PROMISC && */
1963 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr,
1964 ETHER_ADDR_LEN)) {
1965 m_freem(m);
1966 continue;
1967 }
1968
1969#if NBPFILTER > 0
1970 /*
1971 * Handle BPF listeners. Let the BPF user see the packet, but
1972 * don't pass it up to the ether_input() layer unless it's
1973 * a broadcast packet, multicast packet, matches our ethernet
1974 * address or the interface is in promiscuous mode. If we don't
1975 * want the packet, just forget it. We leave the mbuf in place
1976 * since it can be used again later.
1977 */
1978 if (ifp->if_bpf) {
1979 m->m_pkthdr.len = m->m_len = total_len;
1980 bpf_mtap(ifp, m);
1981 if (ifp->if_flags & IFF_PROMISC &&
1982 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1983 ETHER_ADDR_LEN) &&
1984 (eh->ether_dhost[0] & 1) == 0)) {
1985 m_freem(m);
1986 continue;
1987 }
1988 }
1989#endif
1990 /* Remove header from mbuf and pass it on. */
1991 m->m_pkthdr.len = m->m_len =
1992 total_len - sizeof(struct ether_header);
1993 m->m_data += sizeof(struct ether_header);
1994 ether_input(ifp, eh, m);
1995 }
1996
1997 return(r);
1998}
1999
2000/*
2001 * The RX-EOC condition hits when the ch_parm address hasn't been
2002 * initialized or the adapter reached a list with a forward pointer
2003 * of 0 (which indicates the end of the chain). In our case, this means
2004 * the card has hit the end of the receive buffer chain and we need to
2005 * empty out the buffers and shift the pointer back to the beginning again.
2006 */
2007static int tl_intvec_rxeoc(xsc, type)
2008 void *xsc;
2009 u_int32_t type;
2010{
2011 struct tl_softc *sc;
2012 int r;
2013
2014 sc = xsc;
2015
2016 /* Flush out the receive queue and ack RXEOF interrupts. */
2017 r = tl_intvec_rxeof(xsc, type);
2018 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000)));
2019 r = 1;
2020 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr));
2021 r |= (TL_CMD_GO|TL_CMD_RT);
2022 return(r);
2023}
2024
2025static int tl_intvec_txeof(xsc, type)
2026 void *xsc;
2027 u_int32_t type;
2028{
2029 struct tl_softc *sc;
2030 int r = 0;
2031 struct tl_chain *cur_tx;
2032
2033 sc = xsc;
2034
2035 /*
2036 * Go through our tx list and free mbufs for those
2037 * frames that have been sent.
2038 */
2039 while (sc->tl_cdata.tl_tx_head != NULL) {
2040 cur_tx = sc->tl_cdata.tl_tx_head;
2041 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
2042 break;
2043 sc->tl_cdata.tl_tx_head = cur_tx->tl_next;
2044
2045 r++;
2046 m_freem(cur_tx->tl_mbuf);
2047 cur_tx->tl_mbuf = NULL;
2048
2049 cur_tx->tl_next = sc->tl_cdata.tl_tx_free;
2050 sc->tl_cdata.tl_tx_free = cur_tx;
2051 if (!cur_tx->tl_ptr->tlist_fptr)
2052 break;
2053 }
2054
2055 return(r);
2056}
2057
2058/*
2059 * The transmit end of channel interrupt. The adapter triggers this
2060 * interrupt to tell us it hit the end of the current transmit list.
2061 *
2062 * A note about this: it's possible for a condition to arise where
2063 * tl_start() may try to send frames between TXEOF and TXEOC interrupts.
2064 * You have to avoid this since the chip expects things to go in a
2065 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC.
2066 * When the TXEOF handler is called, it will free all of the transmitted
2067 * frames and reset the tx_head pointer to NULL. However, a TXEOC
2068 * interrupt should be received and acknowledged before any more frames
2069 * are queued for transmission. If tl_statrt() is called after TXEOF
2070 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives,
2071 * it could attempt to issue a transmit command prematurely.
2072 *
2073 * To guard against this, tl_start() will only issue transmit commands
2074 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler
2075 * can set this flag once tl_start() has cleared it.
2076 */
2077static int tl_intvec_txeoc(xsc, type)
2078 void *xsc;
2079 u_int32_t type;
2080{
2081 struct tl_softc *sc;
2082 struct ifnet *ifp;
2083 u_int32_t cmd;
2084
2085 sc = xsc;
2086 ifp = &sc->arpcom.ac_if;
2087
2088 /* Clear the timeout timer. */
2089 ifp->if_timer = 0;
2090
2091 if (sc->tl_cdata.tl_tx_head == NULL) {
2092 ifp->if_flags &= ~IFF_OACTIVE;
2093 sc->tl_cdata.tl_tx_tail = NULL;
2094 sc->tl_txeoc = 1;
2095 /*
2096 * If we just drained the TX queue and
2097 * there's an autoneg request waiting, set
2098 * it in motion. This will block the transmitter
2099 * until the autoneg session completes which will
2100 * no doubt piss off any processes waiting to
2101 * transmit, but that's the way the ball bounces.
2102 */
2103 if (sc->tl_want_auto)
2104 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1);
2105 } else {
2106 sc->tl_txeoc = 0;
2107 /* First we have to ack the EOC interrupt. */
2108 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type);
2109 /* Then load the address of the next TX list. */
2110 CSR_WRITE_4(sc, TL_CH_PARM,
2111 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr));
2112 /* Restart TX channel. */
2113 cmd = CSR_READ_4(sc, TL_HOSTCMD);
2114 cmd &= ~TL_CMD_RT;
2115 cmd |= TL_CMD_GO|TL_CMD_INTSON;
2116 CMD_PUT(sc, cmd);
2117 return(0);
2118 }
2119
2120 return(1);
2121}
2122
2123static int tl_intvec_adchk(xsc, type)
2124 void *xsc;
2125 u_int32_t type;
2126{
2127 struct tl_softc *sc;
2128 u_int16_t bmcr, ctl;
2129
2130 sc = xsc;
2131
2132 if (type)
2133 printf("tl%d: adapter check: %x\n", sc->tl_unit,
2134 (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
2135
2136 /*
2137 * Before resetting the adapter, try reading the PHY
2138 * settings so we can put them back later. This is
2139 * necessary to keep the chip operating at the same
2140 * speed and duplex settings after the reset completes.
2141 */
2142 if (!sc->tl_bitrate) {
2143 bmcr = tl_phy_readreg(sc, PHY_BMCR);
2144 ctl = tl_phy_readreg(sc, TL_PHY_CTL);
2145 tl_softreset(sc, 1);
2146 tl_phy_writereg(sc, PHY_BMCR, bmcr);
2147 tl_phy_writereg(sc, TL_PHY_CTL, ctl);
2148 if (bmcr & PHY_BMCR_DUPLEX) {
2149 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
2150 } else {
2151 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
2152 }
2153 }
2154 tl_stop(sc);
2155 tl_init(sc);
2156 CMD_SET(sc, TL_CMD_INTSON);
2157
2158 return(0);
2159}
2160
2161static int tl_intvec_netsts(xsc, type)
2162 void *xsc;
2163 u_int32_t type;
2164{
2165 struct tl_softc *sc;
2166 u_int16_t netsts;
2167
2168 sc = xsc;
2169
2170 netsts = tl_dio_read16(sc, TL_NETSTS);
2171 tl_dio_write16(sc, TL_NETSTS, netsts);
2172
2173 printf("tl%d: network status: %x\n", sc->tl_unit, netsts);
2174
2175 return(1);
2176}
2177
2178static void tl_intr(xsc)
2179 void *xsc;
2180{
2181 struct tl_softc *sc;
2182 struct ifnet *ifp;
2183 int r = 0;
2184 u_int32_t type = 0;
2185 u_int16_t ints = 0;
2186 u_int8_t ivec = 0;
2187
2188 sc = xsc;
2189
2190 /* Disable interrupts */
2191 ints = CSR_READ_2(sc, TL_HOST_INT);
2192 CSR_WRITE_2(sc, TL_HOST_INT, ints);
2193 type = (ints << 16) & 0xFFFF0000;
2194 ivec = (ints & TL_VEC_MASK) >> 5;
2195 ints = (ints & TL_INT_MASK) >> 2;
2196
2197 ifp = &sc->arpcom.ac_if;
2198
2199 switch(ints) {
2200 case (TL_INTR_INVALID):
2201#ifdef DIAGNOSTIC
2202 printf("tl%d: got an invalid interrupt!\n", sc->tl_unit);
2203#endif
2204 /* Re-enable interrupts but don't ack this one. */
2205 CMD_PUT(sc, type);
2206 r = 0;
2207 break;
2208 case (TL_INTR_TXEOF):
2209 r = tl_intvec_txeof((void *)sc, type);
2210 break;
2211 case (TL_INTR_TXEOC):
2212 r = tl_intvec_txeoc((void *)sc, type);
2213 break;
2214 case (TL_INTR_STATOFLOW):
2215 tl_stats_update(sc);
2216 r = 1;
2217 break;
2218 case (TL_INTR_RXEOF):
2219 r = tl_intvec_rxeof((void *)sc, type);
2220 break;
2221 case (TL_INTR_DUMMY):
2222 printf("tl%d: got a dummy interrupt\n", sc->tl_unit);
2223 r = 1;
2224 break;
2225 case (TL_INTR_ADCHK):
2226 if (ivec)
2227 r = tl_intvec_adchk((void *)sc, type);
2228 else
2229 r = tl_intvec_netsts((void *)sc, type);
2230 break;
2231 case (TL_INTR_RXEOC):
2232 r = tl_intvec_rxeoc((void *)sc, type);
2233 break;
2234 default:
2235 printf("tl%d: bogus interrupt type\n", ifp->if_unit);
2236 break;
2237 }
2238
2239 /* Re-enable interrupts */
2240 if (r) {
2241 CMD_PUT(sc, TL_CMD_ACK | r | type);
2242 }
2243
2244 if (ifp->if_snd.ifq_head != NULL)
2245 tl_start(ifp);
2246
2247 return;
2248}
2249
2250static void tl_stats_update(xsc)
2251 void *xsc;
2252{
2253 struct tl_softc *sc;
2254 struct ifnet *ifp;
2255 struct tl_stats tl_stats;
2256 u_int32_t *p;
2257
2258 bzero((char *)&tl_stats, sizeof(struct tl_stats));
2259
2260 sc = xsc;
2261 ifp = &sc->arpcom.ac_if;
2262
2263 p = (u_int32_t *)&tl_stats;
2264
2265 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);
2266 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
2267 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
2268 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
2269 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
2270 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
2271
2272 ifp->if_opackets += tl_tx_goodframes(tl_stats);
2273 ifp->if_collisions += tl_stats.tl_tx_single_collision +
2274 tl_stats.tl_tx_multi_collision;
2275 ifp->if_ipackets += tl_rx_goodframes(tl_stats);
2276 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors +
2277 tl_rx_overrun(tl_stats);
2278 ifp->if_oerrors += tl_tx_underrun(tl_stats);
2279
2280 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz);
2281
2282 return;
2283}
2284
2285/*
2286 * Encapsulate an mbuf chain in a list by coupling the mbuf data
2287 * pointers to the fragment pointers.
2288 */
2289static int tl_encap(sc, c, m_head)
2290 struct tl_softc *sc;
2291 struct tl_chain *c;
2292 struct mbuf *m_head;
2293{
2294 int frag = 0;
2295 struct tl_frag *f = NULL;
2296 int total_len;
2297 struct mbuf *m;
2298
2299 /*
2300 * Start packing the mbufs in this chain into
2301 * the fragment pointers. Stop when we run out
2302 * of fragments or hit the end of the mbuf chain.
2303 */
2304 m = m_head;
2305 total_len = 0;
2306
2307 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
2308 if (m->m_len != 0) {
2309 if (frag == TL_MAXFRAGS)
2310 break;
2311 total_len+= m->m_len;
2312 c->tl_ptr->tl_frag[frag].tlist_dadr =
2313 vtophys(mtod(m, vm_offset_t));
2314 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len;
2315 frag++;
2316 }
2317 }
2318
2319 /*
2320 * Handle special cases.
2321 * Special case #1: we used up all 10 fragments, but
2322 * we have more mbufs left in the chain. Copy the
2323 * data into an mbuf cluster. Note that we don't
2324 * bother clearing the values in the other fragment
2325 * pointers/counters; it wouldn't gain us anything,
2326 * and would waste cycles.
2327 */
2328 if (m != NULL) {
2329 struct mbuf *m_new = NULL;
2330
2331 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
2332 if (m_new == NULL) {
2333 printf("tl%d: no memory for tx list", sc->tl_unit);
2334 return(1);
2335 }
2336 if (m_head->m_pkthdr.len > MHLEN) {
2337 MCLGET(m_new, M_DONTWAIT);
2338 if (!(m_new->m_flags & M_EXT)) {
2339 m_freem(m_new);
2340 printf("tl%d: no memory for tx list",
2341 sc->tl_unit);
2342 return(1);
2343 }
2344 }
2345 m_copydata(m_head, 0, m_head->m_pkthdr.len,
2346 mtod(m_new, caddr_t));
2347 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
2348 m_freem(m_head);
2349 m_head = m_new;
2350 f = &c->tl_ptr->tl_frag[0];
2351 f->tlist_dadr = vtophys(mtod(m_new, caddr_t));
2352 f->tlist_dcnt = total_len = m_new->m_len;
2353 frag = 1;
2354 }
2355
2356 /*
2357 * Special case #2: the frame is smaller than the minimum
2358 * frame size. We have to pad it to make the chip happy.
2359 */
2360 if (total_len < TL_MIN_FRAMELEN) {
2361 if (frag == TL_MAXFRAGS)
2362 printf("tl%d: all frags filled but "
2363 "frame still to small!\n", sc->tl_unit);
2364 f = &c->tl_ptr->tl_frag[frag];
2365 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len;
2366 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad);
2367 total_len += f->tlist_dcnt;
2368 frag++;
2369 }
2370
2371 c->tl_mbuf = m_head;
2372 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG;
2373 c->tl_ptr->tlist_frsize = total_len;
2374 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
2375 c->tl_ptr->tlist_fptr = 0;
2376
2377 return(0);
2378}
2379
2380/*
2381 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2382 * to the mbuf data regions directly in the transmit lists. We also save a
2383 * copy of the pointers since the transmit list fragment pointers are
2384 * physical addresses.
2385 */
2386static void tl_start(ifp)
2387 struct ifnet *ifp;
2388{
2389 struct tl_softc *sc;
2390 struct mbuf *m_head = NULL;
2391 u_int32_t cmd;
2392 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2393
2394 sc = ifp->if_softc;
2395
2396 if (sc->tl_autoneg) {
2397 sc->tl_tx_pend = 1;
2398 return;
2399 }
2400
2401 /*
2402 * Check for an available queue slot. If there are none,
2403 * punt.
2404 */
2405 if (sc->tl_cdata.tl_tx_free == NULL) {
2406 ifp->if_flags |= IFF_OACTIVE;
2407 return;
2408 }
2409
2410 start_tx = sc->tl_cdata.tl_tx_free;
2411
2412 while(sc->tl_cdata.tl_tx_free != NULL) {
2413 IF_DEQUEUE(&ifp->if_snd, m_head);
2414 if (m_head == NULL)
2415 break;
2416
2417 /* Pick a chain member off the free list. */
2418 cur_tx = sc->tl_cdata.tl_tx_free;
2419 sc->tl_cdata.tl_tx_free = cur_tx->tl_next;
2420
2421 cur_tx->tl_next = NULL;
2422
2423 /* Pack the data into the list. */
2424 tl_encap(sc, cur_tx, m_head);
2425
2426 /* Chain it together */
2427 if (prev != NULL) {
2428 prev->tl_next = cur_tx;
2429 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr);
2430 }
2431 prev = cur_tx;
2432
2433 /*
2434 * If there's a BPF listener, bounce a copy of this frame
2435 * to him.
2436 */
2437#if NBPFILTER > 0
2438 if (ifp->if_bpf)
2439 bpf_mtap(ifp, cur_tx->tl_mbuf);
2440#endif
2441 }
2442
2443 /*
2444 * If there are no packets queued, bail.
2445 */
2446 if (cur_tx == NULL)
2447 return;
2448
2449 /*
2450 * That's all we can stands, we can't stands no more.
2451 * If there are no other transfers pending, then issue the
2452 * TX GO command to the adapter to start things moving.
2453 * Otherwise, just leave the data in the queue and let
2454 * the EOF/EOC interrupt handler send.
2455 */
2456 if (sc->tl_cdata.tl_tx_head == NULL) {
2457 sc->tl_cdata.tl_tx_head = start_tx;
2458 sc->tl_cdata.tl_tx_tail = cur_tx;
2459
2460 if (sc->tl_txeoc) {
2461 sc->tl_txeoc = 0;
2462 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr));
2463 cmd = CSR_READ_4(sc, TL_HOSTCMD);
2464 cmd &= ~TL_CMD_RT;
2465 cmd |= TL_CMD_GO|TL_CMD_INTSON;
2466 CMD_PUT(sc, cmd);
2467 }
2468 } else {
2469 sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
2470 sc->tl_cdata.tl_tx_tail = cur_tx;
2471 }
2472
2473 /*
2474 * Set a timeout in case the chip goes out to lunch.
2475 */
2476 ifp->if_timer = 5;
2477
2478 return;
2479}
2480
2481static void tl_init(xsc)
2482 void *xsc;
2483{
2484 struct tl_softc *sc = xsc;
2485 struct ifnet *ifp = &sc->arpcom.ac_if;
2486 int s;
2487 u_int16_t phy_sts;
2488
2489 if (sc->tl_autoneg)
2490 return;
2491
2492 s = splimp();
2493
2494 ifp = &sc->arpcom.ac_if;
2495
2496 /*
2497 * Cancel pending I/O.
2498 */
2499 tl_stop(sc);
2500
2501 /*
2502 * Set 'capture all frames' bit for promiscuous mode.
2503 */
2504 if (ifp->if_flags & IFF_PROMISC)
2505 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2506 else
2507 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2508
2509 /*
2510 * Set capture broadcast bit to capture broadcast frames.
2511 */
2512 if (ifp->if_flags & IFF_BROADCAST)
2513 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2514 else
2515 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2516
2517 /* Init our MAC address */
2518 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0);
2519
2520 /* Init multicast filter, if needed. */
2521 tl_setmulti(sc);
2522
2523 /* Init circular RX list. */
2524 if (tl_list_rx_init(sc) == ENOBUFS) {
2525 printf("tl%d: initialization failed: no "
2526 "memory for rx buffers\n", sc->tl_unit);
2527 tl_stop(sc);
2528 return;
2529 }
2530
2531 /* Init TX pointers. */
2532 tl_list_tx_init(sc);
2533
2534 /*
2535 * Enable PHY interrupts.
2536 */
2537 phy_sts = tl_phy_readreg(sc, TL_PHY_CTL);
2538 phy_sts |= PHY_CTL_INTEN;
2539 tl_phy_writereg(sc, TL_PHY_CTL, phy_sts);
2540
2541 /* Enable MII interrupts. */
2542 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
2543
2544 /* Enable PCI interrupts. */
2545 CMD_SET(sc, TL_CMD_INTSON);
2546
2547 /* Load the address of the rx list */
2548 CMD_SET(sc, TL_CMD_RT);
2549 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0]));
2550
2551 /*
2552 * XXX This is a kludge to handle adapters with the Micro Linear
2553 * ML6692 100BaseTX PHY, which only supports 100Mbps modes and
2554 * relies on the controller's internal 10Mbps PHY to provide
2555 * 10Mbps modes. The ML6692 always shows up with a vendor/device ID
2556 * of 0 (it doesn't actually have vendor/device ID registers)
2557 * so we use that property to detect it. In theory there ought to
2558 * be a better way to 'spot the looney' but I can't find one.
2559 */
2560 if (!sc->tl_phy_vid) {
2561 u_int8_t addr = 0;
2562 u_int16_t bmcr;
2563
2564 bmcr = tl_phy_readreg(sc, PHY_BMCR);
2565 addr = sc->tl_phy_addr;
2566 sc->tl_phy_addr = TL_PHYADDR_MAX;
2567 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
2568 if (bmcr & PHY_BMCR_SPEEDSEL)
2569 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_ISOLATE);
2570 else
2571 tl_phy_writereg(sc, PHY_BMCR, bmcr);
2572 sc->tl_phy_addr = addr;
2573 }
2574
2575 /* Send the RX go command */
2576 CMD_SET(sc, TL_CMD_GO|TL_CMD_RT);
2577
2578 ifp->if_flags |= IFF_RUNNING;
2579 ifp->if_flags &= ~IFF_OACTIVE;
2580
2581 (void)splx(s);
2582
2583 /* Start the stats update counter */
2584 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz);
2585
2586 return;
2587}
2588
2589/*
2590 * Set media options.
2591 */
2592static int tl_ifmedia_upd(ifp)
2593 struct ifnet *ifp;
2594{
2595 struct tl_softc *sc;
2596 struct ifmedia *ifm;
2597
2598 sc = ifp->if_softc;
2599 ifm = &sc->ifmedia;
2600
2601 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2602 return(EINVAL);
2603
2604 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
2605 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1);
2606 else
2607 tl_setmode(sc, ifm->ifm_media);
2608
2609 return(0);
2610}
2611
2612/*
2613 * Report current media status.
2614 */
2615static void tl_ifmedia_sts(ifp, ifmr)
2616 struct ifnet *ifp;
2617 struct ifmediareq *ifmr;
2618{
2619 u_int16_t phy_ctl;
2620 u_int16_t phy_sts;
2621 struct tl_softc *sc;
2622
2623 sc = ifp->if_softc;
2624
2625 ifmr->ifm_active = IFM_ETHER;
2626
2627 if (sc->tl_bitrate) {
2628 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1)
2629 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2630 else
2631 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2632 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3)
2633 ifmr->ifm_active |= IFM_HDX;
2634 else
2635 ifmr->ifm_active |= IFM_FDX;
2636 return;
2637 }
2638
2639 phy_ctl = tl_phy_readreg(sc, PHY_BMCR);
2640 phy_sts = tl_phy_readreg(sc, TL_PHY_CTL);
2641
2642 if (phy_sts & PHY_CTL_AUISEL)
2643 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2644
2645 if (phy_ctl & PHY_BMCR_LOOPBK)
2646 ifmr->ifm_active = IFM_ETHER|IFM_LOOP;
2647
2648 if (phy_ctl & PHY_BMCR_SPEEDSEL)
2649 ifmr->ifm_active = IFM_ETHER|IFM_100_TX;
2650 else
2651 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2652
2653 if (phy_ctl & PHY_BMCR_DUPLEX) {
2654 ifmr->ifm_active |= IFM_FDX;
2655 ifmr->ifm_active &= ~IFM_HDX;
2656 } else {
2657 ifmr->ifm_active &= ~IFM_FDX;
2658 ifmr->ifm_active |= IFM_HDX;
2659 }
2660
2661 return;
2662}
2663
2664static int tl_ioctl(ifp, command, data)
2665 struct ifnet *ifp;
2666 u_long command;
2667 caddr_t data;
2668{
2669 struct tl_softc *sc = ifp->if_softc;
2670 struct ifreq *ifr = (struct ifreq *) data;
2671 int s, error = 0;
2672
2673 s = splimp();
2674
2675 switch(command) {
2676 case SIOCSIFADDR:
2677 case SIOCGIFADDR:
2678 case SIOCSIFMTU:
2679 error = ether_ioctl(ifp, command, data);
2680 break;
2681 case SIOCSIFFLAGS:
2682 if (ifp->if_flags & IFF_UP) {
2683 tl_init(sc);
2684 } else {
2685 if (ifp->if_flags & IFF_RUNNING) {
2686 tl_stop(sc);
2687 }
2688 }
2689 error = 0;
2690 break;
2691 case SIOCADDMULTI:
2692 case SIOCDELMULTI:
2693 tl_setmulti(sc);
2694 error = 0;
2695 break;
2696 case SIOCSIFMEDIA:
2697 case SIOCGIFMEDIA:
2698 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2699 break;
2700 default:
2701 error = EINVAL;
2702 break;
2703 }
2704
2705 (void)splx(s);
2706
2707 return(error);
2708}
2709
2710static void tl_watchdog(ifp)
2711 struct ifnet *ifp;
2712{
2713 struct tl_softc *sc;
2714 u_int16_t bmsr;
2715
2716 sc = ifp->if_softc;
2717
2718 if (sc->tl_autoneg) {
2719 tl_autoneg(sc, TL_FLAG_DELAYTIMEO, 1);
2720 return;
2721 }
2722
2723 /* Check that we're still connected. */
2724 tl_phy_readreg(sc, PHY_BMSR);
2725 bmsr = tl_phy_readreg(sc, PHY_BMSR);
2726 if (!(bmsr & PHY_BMSR_LINKSTAT)) {
2727 printf("tl%d: no carrier\n", sc->tl_unit);
2728 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1);
2729 } else
2730 printf("tl%d: device timeout\n", sc->tl_unit);
2731
2732 ifp->if_oerrors++;
2733
2734 tl_init(sc);
2735
2736 return;
2737}
2738
2739/*
2740 * Stop the adapter and free any mbufs allocated to the
2741 * RX and TX lists.
2742 */
2743static void tl_stop(sc)
2744 struct tl_softc *sc;
2745{
2746 register int i;
2747 struct ifnet *ifp;
2748
2749 ifp = &sc->arpcom.ac_if;
2750
2751 /* Stop the stats updater. */
2752 untimeout(tl_stats_update, sc, sc->tl_stat_ch);
2753
2754 /* Stop the transmitter */
2755 CMD_CLR(sc, TL_CMD_RT);
2756 CMD_SET(sc, TL_CMD_STOP);
2757 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2758
2759 /* Stop the receiver */
2760 CMD_SET(sc, TL_CMD_RT);
2761 CMD_SET(sc, TL_CMD_STOP);
2762 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2763
2764 /*
2765 * Disable host interrupts.
2766 */
2767 CMD_SET(sc, TL_CMD_INTSOFF);
2768
2769 /*
2770 * Disable MII interrupts.
2771 */
2772 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
2773
2774 /*
2775 * Clear list pointer.
2776 */
2777 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2778
2779 /*
2780 * Free the RX lists.
2781 */
2782 for (i = 0; i < TL_RX_LIST_CNT; i++) {
2783 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) {
2784 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf);
2785 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL;
2786 }
2787 }
2788 bzero((char *)&sc->tl_ldata->tl_rx_list,
2789 sizeof(sc->tl_ldata->tl_rx_list));
2790
2791 /*
2792 * Free the TX list buffers.
2793 */
2794 for (i = 0; i < TL_TX_LIST_CNT; i++) {
2795 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) {
2796 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
2797 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
2798 }
2799 }
2800 bzero((char *)&sc->tl_ldata->tl_tx_list,
2801 sizeof(sc->tl_ldata->tl_tx_list));
2802
2803 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2804
2805 return;
2806}
2807
2808/*
2809 * Stop all chip I/O so that the kernel's probe routines don't
2810 * get confused by errant DMAs when rebooting.
2811 */
2812static void tl_shutdown(howto, xsc)
2813 int howto;
2814 void *xsc;
2815{
2816 struct tl_softc *sc;
2817
2818 sc = xsc;
2819
2820 tl_stop(sc);
2821
2822 return;
2823}
2824
2825
2826static struct pci_device tl_device = {
2827 "tl",
2828 tl_probe,
2829 tl_attach,
2830 &tl_count,
2831 NULL
2832};
2833#ifdef COMPAT_PCI_DRIVER
2834COMPAT_PCI_DRIVER(tl, tl_device);
2835#else
2836DATA_SET(pcidevice_set, tl_device);
2837#endif /* COMPAT_PCI_DRIVER */