| if_tireg.h (50477) | if_tireg.h (51536) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/dev/ti/if_tireg.h 50477 1999-08-28 01:08:13Z peter $ | 32 * $FreeBSD: head/sys/dev/ti/if_tireg.h 51536 1999-09-22 06:43:16Z wpaul $ |
| 33 */ 34 35/* 36 * Tigon register offsets. These are memory mapped registers 37 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38 * Each register must be accessed using 32 bit operations. 39 * 40 * All reegisters are accessed through a 16K shared memory block. --- 82 unchanged lines hidden (view full) --- 123#define TI_REV_TIGON_I 0x40000000 124#define TI_REV_TIGON_II 0x60000000 125 126/* 127 * Firmware revision that we want. 128 */ 129#define TI_FIRMWARE_MAJOR 0xc 130#define TI_FIRMWARE_MINOR 0x3 | 33 */ 34 35/* 36 * Tigon register offsets. These are memory mapped registers 37 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38 * Each register must be accessed using 32 bit operations. 39 * 40 * All reegisters are accessed through a 16K shared memory block. --- 82 unchanged lines hidden (view full) --- 123#define TI_REV_TIGON_I 0x40000000 124#define TI_REV_TIGON_II 0x60000000 125 126/* 127 * Firmware revision that we want. 128 */ 129#define TI_FIRMWARE_MAJOR 0xc 130#define TI_FIRMWARE_MINOR 0x3 |
| 131#define TI_FIRMWARE_FIX 0xc | 131#define TI_FIRMWARE_FIX 0xf |
| 132 133/* 134 * Miscelaneous Local Control register. 135 */ 136#define TI_MLC_EE_WRITE_ENB 0x00000010 137#define TI_MLC_SRAM_BANK_256K 0x00000200 138#define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */ 139#define TI_MLC_LOCALADDR_21 0x00004000 --- 1038 unchanged lines hidden --- | 132 133/* 134 * Miscelaneous Local Control register. 135 */ 136#define TI_MLC_EE_WRITE_ENB 0x00000010 137#define TI_MLC_SRAM_BANK_256K 0x00000200 138#define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */ 139#define TI_MLC_LOCALADDR_21 0x00004000 --- 1038 unchanged lines hidden --- |