| if_tireg.h (48597) | if_tireg.h (49011) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $Id: if_tireg.h,v 1.46 1999/07/05 19:20:31 wpaul Exp $ | 32 * $Id: if_tireg.h,v 1.46 1999/07/05 19:20:31 wpaul Exp wpaul $ |
| 33 */ 34 35/* 36 * Tigon register offsets. These are memory mapped registers 37 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38 * Each register must be accessed using 32 bit operations. 39 * 40 * All reegisters are accessed through a 16K shared memory block. --- 82 unchanged lines hidden (view full) --- 123#define TI_REV_TIGON_I 0x40000000 124#define TI_REV_TIGON_II 0x60000000 125 126/* 127 * Firmware revision that we want. 128 */ 129#define TI_FIRMWARE_MAJOR 0xc 130#define TI_FIRMWARE_MINOR 0x3 | 33 */ 34 35/* 36 * Tigon register offsets. These are memory mapped registers 37 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38 * Each register must be accessed using 32 bit operations. 39 * 40 * All reegisters are accessed through a 16K shared memory block. --- 82 unchanged lines hidden (view full) --- 123#define TI_REV_TIGON_I 0x40000000 124#define TI_REV_TIGON_II 0x60000000 125 126/* 127 * Firmware revision that we want. 128 */ 129#define TI_FIRMWARE_MAJOR 0xc 130#define TI_FIRMWARE_MINOR 0x3 |
| 131#define TI_FIRMWARE_FIX 0xa | 131#define TI_FIRMWARE_FIX 0xc |
| 132 133/* 134 * Miscelaneous Local Control register. 135 */ 136#define TI_MLC_EE_WRITE_ENB 0x00000010 137#define TI_MLC_SRAM_BANK_256K 0x00000200 138#define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */ 139#define TI_MLC_LOCALADDR_21 0x00004000 --- 969 unchanged lines hidden (view full) --- 1109struct ti_jpool_entry { 1110 int slot; 1111 SLIST_ENTRY(ti_jpool_entry) jpool_entries; 1112}; 1113 1114struct ti_softc { 1115 struct arpcom arpcom; /* interface info */ 1116 bus_space_handle_t ti_bhandle; | 132 133/* 134 * Miscelaneous Local Control register. 135 */ 136#define TI_MLC_EE_WRITE_ENB 0x00000010 137#define TI_MLC_SRAM_BANK_256K 0x00000200 138#define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */ 139#define TI_MLC_LOCALADDR_21 0x00004000 --- 969 unchanged lines hidden (view full) --- 1109struct ti_jpool_entry { 1110 int slot; 1111 SLIST_ENTRY(ti_jpool_entry) jpool_entries; 1112}; 1113 1114struct ti_softc { 1115 struct arpcom arpcom; /* interface info */ 1116 bus_space_handle_t ti_bhandle; |
| 1117#ifdef __alpha__ 1118 vm_offset_t ti_vhandle; /* alpha dense space vaddr */ 1119#endif | |
| 1120 bus_space_tag_t ti_btag; | 1117 bus_space_tag_t ti_btag; |
| 1118 void *ti_intrhand; 1119 struct resource *ti_irq; 1120 struct resource *ti_res; |
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| 1121 struct ifmedia ifmedia; /* media info */ 1122 u_int8_t ti_unit; /* interface number */ 1123 u_int8_t ti_hwrev; /* Tigon rev (1 or 2) */ 1124 u_int8_t ti_linkstat; /* Link state */ | 1121 struct ifmedia ifmedia; /* media info */ 1122 u_int8_t ti_unit; /* interface number */ 1123 u_int8_t ti_hwrev; /* Tigon rev (1 or 2) */ 1124 u_int8_t ti_linkstat; /* Link state */ |
| 1125 caddr_t ti_rdata_ptr; /* Raw ring data */ | |
| 1126 struct ti_ring_data *ti_rdata; /* rings */ 1127 struct ti_chain_data ti_cdata; /* mbufs */ 1128#define ti_ev_prodidx ti_rdata->ti_ev_prodidx_r 1129#define ti_return_prodidx ti_rdata->ti_return_prodidx_r 1130#define ti_tx_considx ti_rdata->ti_tx_considx_r 1131 u_int16_t ti_tx_saved_considx; 1132 u_int16_t ti_rx_saved_considx; 1133 u_int16_t ti_ev_saved_considx; --- 52 unchanged lines hidden --- | 1125 struct ti_ring_data *ti_rdata; /* rings */ 1126 struct ti_chain_data ti_cdata; /* mbufs */ 1127#define ti_ev_prodidx ti_rdata->ti_ev_prodidx_r 1128#define ti_return_prodidx ti_rdata->ti_return_prodidx_r 1129#define ti_tx_considx ti_rdata->ti_tx_considx_r 1130 u_int16_t ti_tx_saved_considx; 1131 u_int16_t ti_rx_saved_considx; 1132 u_int16_t ti_ev_saved_considx; --- 52 unchanged lines hidden --- |