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maestro3.c (201758) maestro3.c (230401)
1/*-
2 * Copyright (c) 2001 Scott Long <scottl@freebsd.org>
3 * Copyright (c) 2001 Darrell Anderson <anderson@cs.duke.edu>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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57#endif
58
59#include <dev/sound/pcm/sound.h>
60#include <dev/sound/pcm/ac97.h>
61
62#include <dev/pci/pcireg.h>
63#include <dev/pci/pcivar.h>
64
1/*-
2 * Copyright (c) 2001 Scott Long <scottl@freebsd.org>
3 * Copyright (c) 2001 Darrell Anderson <anderson@cs.duke.edu>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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57#endif
58
59#include <dev/sound/pcm/sound.h>
60#include <dev/sound/pcm/ac97.h>
61
62#include <dev/pci/pcireg.h>
63#include <dev/pci/pcivar.h>
64
65#include <gnu/dev/sound/pci/maestro3_reg.h>
66#include <gnu/dev/sound/pci/maestro3_dsp.h>
65#define M3_MODEL 1
67
66
68SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/maestro3.c 201758 2010-01-07 21:01:37Z mbr $");
67#include <dev/sound/pci/allegro_reg.h>
68#include <dev/sound/pci/allegro_code.h>
69
69
70SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/maestro3.c 230401 2012-01-20 22:37:10Z pfg $");
71
70/* -------------------------------------------------------------------- */
71
72enum {CHANGE=0, CALL=1, INTR=2, BORING=3, NONE=-1};
73#ifndef M3_DEBUG_LEVEL
74#define M3_DEBUG_LEVEL NONE
75#endif
76#define M3_DEBUG(level, _msg) {if ((level) <= M3_DEBUG_LEVEL) {printf _msg;}}
77

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91};
92
93#define M3_BUFSIZE_MIN 4096
94#define M3_BUFSIZE_MAX 65536
95#define M3_BUFSIZE_DEFAULT 4096
96#define M3_PCHANS 4 /* create /dev/dsp0.[0-N] to use more than one */
97#define M3_RCHANS 1
98#define M3_MAXADDR ((1 << 27) - 1)
72/* -------------------------------------------------------------------- */
73
74enum {CHANGE=0, CALL=1, INTR=2, BORING=3, NONE=-1};
75#ifndef M3_DEBUG_LEVEL
76#define M3_DEBUG_LEVEL NONE
77#endif
78#define M3_DEBUG(level, _msg) {if ((level) <= M3_DEBUG_LEVEL) {printf _msg;}}
79

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93};
94
95#define M3_BUFSIZE_MIN 4096
96#define M3_BUFSIZE_MAX 65536
97#define M3_BUFSIZE_DEFAULT 4096
98#define M3_PCHANS 4 /* create /dev/dsp0.[0-N] to use more than one */
99#define M3_RCHANS 1
100#define M3_MAXADDR ((1 << 27) - 1)
101#define M3_DEFAULT_VOL 0x6800
99
100struct sc_info;
101
102struct sc_pchinfo {
103 u_int32_t spd;
104 u_int32_t fmt;
105 struct snd_dbuf *buffer;
106 struct pcm_channel *channel;

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371m3_pchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
372{
373 struct sc_info *sc = devinfo;
374 struct sc_pchinfo *ch;
375 u_int32_t bus_addr, i;
376 int idx, data_bytes, dac_data;
377 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf;
378
102
103struct sc_info;
104
105struct sc_pchinfo {
106 u_int32_t spd;
107 u_int32_t fmt;
108 struct snd_dbuf *buffer;
109 struct pcm_channel *channel;

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374m3_pchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
375{
376 struct sc_info *sc = devinfo;
377 struct sc_pchinfo *ch;
378 u_int32_t bus_addr, i;
379 int idx, data_bytes, dac_data;
380 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf;
381
382 struct data_word {
383 u_int16_t addr, val;
384 } pv[] = {
385 {CDATA_LEFT_VOLUME, M3_DEFAULT_VOL},
386 {CDATA_RIGHT_VOLUME, M3_DEFAULT_VOL},
387 {SRC3_DIRECTION_OFFSET, 0} ,
388 {SRC3_DIRECTION_OFFSET + 3, 0x0000},
389 {SRC3_DIRECTION_OFFSET + 4, 0},
390 {SRC3_DIRECTION_OFFSET + 5, 0},
391 {SRC3_DIRECTION_OFFSET + 6, 0},
392 {SRC3_DIRECTION_OFFSET + 7, 0},
393 {SRC3_DIRECTION_OFFSET + 8, 0},
394 {SRC3_DIRECTION_OFFSET + 9, 0},
395 {SRC3_DIRECTION_OFFSET + 10, 0x8000},
396 {SRC3_DIRECTION_OFFSET + 11, 0xFF00},
397 {SRC3_DIRECTION_OFFSET + 13, 0},
398 {SRC3_DIRECTION_OFFSET + 14, 0},
399 {SRC3_DIRECTION_OFFSET + 15, 0},
400 {SRC3_DIRECTION_OFFSET + 16, 8},
401 {SRC3_DIRECTION_OFFSET + 17, 50*2},
402 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1},
403 {SRC3_DIRECTION_OFFSET + 20, 0},
404 {SRC3_DIRECTION_OFFSET + 21, 0}
405 };
406
379 M3_LOCK(sc);
380 idx = sc->pch_cnt; /* dac instance number, no active reuse! */
381 M3_DEBUG(CHANGE, ("m3_pchan_init(dac=%d)\n", idx));
382
383 if (dir != PCMDIR_PLAY) {
384 M3_UNLOCK(sc);
385 device_printf(sc->dev, "m3_pchan_init not PCMDIR_PLAY\n");
386 return (NULL);

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724{
725 struct sc_info *sc = devinfo;
726 struct sc_rchinfo *ch;
727 u_int32_t bus_addr, i;
728
729 int idx, data_bytes, adc_data;
730 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf;
731
407 M3_LOCK(sc);
408 idx = sc->pch_cnt; /* dac instance number, no active reuse! */
409 M3_DEBUG(CHANGE, ("m3_pchan_init(dac=%d)\n", idx));
410
411 if (dir != PCMDIR_PLAY) {
412 M3_UNLOCK(sc);
413 device_printf(sc->dev, "m3_pchan_init not PCMDIR_PLAY\n");
414 return (NULL);

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752{
753 struct sc_info *sc = devinfo;
754 struct sc_rchinfo *ch;
755 u_int32_t bus_addr, i;
756
757 int idx, data_bytes, adc_data;
758 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf;
759
760 struct data_word {
761 u_int16_t addr, val;
762 } rv[] = {
763 {CDATA_LEFT_VOLUME, M3_DEFAULT_VOL},
764 {CDATA_RIGHT_VOLUME, M3_DEFAULT_VOL},
765 {SRC3_DIRECTION_OFFSET, 1},
766 {SRC3_DIRECTION_OFFSET + 3, 0x0000},
767 {SRC3_DIRECTION_OFFSET + 4, 0},
768 {SRC3_DIRECTION_OFFSET + 5, 0},
769 {SRC3_DIRECTION_OFFSET + 6, 0},
770 {SRC3_DIRECTION_OFFSET + 7, 0},
771 {SRC3_DIRECTION_OFFSET + 8, 0},
772 {SRC3_DIRECTION_OFFSET + 9, 0},
773 {SRC3_DIRECTION_OFFSET + 10, 0x8000},
774 {SRC3_DIRECTION_OFFSET + 11, 0xFF00},
775 {SRC3_DIRECTION_OFFSET + 13, 0},
776 {SRC3_DIRECTION_OFFSET + 14, 0},
777 {SRC3_DIRECTION_OFFSET + 15, 0},
778 {SRC3_DIRECTION_OFFSET + 16, 50},
779 {SRC3_DIRECTION_OFFSET + 17, 8},
780 {SRC3_DIRECTION_OFFSET + 18, 0},
781 {SRC3_DIRECTION_OFFSET + 19, 0},
782 {SRC3_DIRECTION_OFFSET + 20, 0},
783 {SRC3_DIRECTION_OFFSET + 21, 0},
784 {SRC3_DIRECTION_OFFSET + 22, 0xff}
785 };
786
732 M3_LOCK(sc);
733 idx = sc->rch_cnt; /* adc instance number, no active reuse! */
734 M3_DEBUG(CHANGE, ("m3_rchan_init(adc=%d)\n", idx));
735
736 if (dir != PCMDIR_REC) {
737 M3_UNLOCK(sc);
738 device_printf(sc->dev, "m3_pchan_init not PCMDIR_REC\n");
739 return (NULL);

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1184 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA;
1185 for(i = 0 ; i < size / 2 ; i++) {
1186 m3_wr_assp_data(sc, KDATA_BASE_ADDR2 + i, 0);
1187 }
1188 /* init dma pointer */
1189 m3_wr_assp_data(sc, KDATA_CURRENT_DMA,
1190 KDATA_DMA_XFER0);
1191 /* write kernel into code memory */
787 M3_LOCK(sc);
788 idx = sc->rch_cnt; /* adc instance number, no active reuse! */
789 M3_DEBUG(CHANGE, ("m3_rchan_init(adc=%d)\n", idx));
790
791 if (dir != PCMDIR_REC) {
792 M3_UNLOCK(sc);
793 device_printf(sc->dev, "m3_pchan_init not PCMDIR_REC\n");
794 return (NULL);

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1239 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA;
1240 for(i = 0 ; i < size / 2 ; i++) {
1241 m3_wr_assp_data(sc, KDATA_BASE_ADDR2 + i, 0);
1242 }
1243 /* init dma pointer */
1244 m3_wr_assp_data(sc, KDATA_CURRENT_DMA,
1245 KDATA_DMA_XFER0);
1246 /* write kernel into code memory */
1192 size = sizeof(assp_kernel_image);
1247 size = sizeof(gaw_kernel_vect_code);
1193 for(i = 0 ; i < size / 2; i++) {
1194 m3_wr_assp_code(sc, REV_B_CODE_MEMORY_BEGIN + i,
1248 for(i = 0 ; i < size / 2; i++) {
1249 m3_wr_assp_code(sc, REV_B_CODE_MEMORY_BEGIN + i,
1195 assp_kernel_image[i]);
1250 gaw_kernel_vect_code[i]);
1196 }
1197 /*
1198 * We only have this one client and we know that 0x400 is free in
1199 * our kernel's mem map, so lets just drop it there. It seems that
1200 * the minisrc doesn't need vectors, so we won't bother with them..
1201 */
1251 }
1252 /*
1253 * We only have this one client and we know that 0x400 is free in
1254 * our kernel's mem map, so lets just drop it there. It seems that
1255 * the minisrc doesn't need vectors, so we won't bother with them..
1256 */
1202 size = sizeof(assp_minisrc_image);
1257 size = sizeof(gaw_minisrc_code_0400);
1203 for(i = 0 ; i < size / 2; i++) {
1258 for(i = 0 ; i < size / 2; i++) {
1204 m3_wr_assp_code(sc, 0x400 + i, assp_minisrc_image[i]);
1259 m3_wr_assp_code(sc, 0x400 + i, gaw_minisrc_code_0400[i]);
1205 }
1206 /* write the coefficients for the low pass filter? */
1260 }
1261 /* write the coefficients for the low pass filter? */
1207 size = sizeof(minisrc_lpf_image);
1262 size = sizeof(minisrc_lpf);
1208 for(i = 0; i < size / 2 ; i++) {
1209 m3_wr_assp_code(sc,0x400 + MINISRC_COEF_LOC + i,
1263 for(i = 0; i < size / 2 ; i++) {
1264 m3_wr_assp_code(sc,0x400 + MINISRC_COEF_LOC + i,
1210 minisrc_lpf_image[i]);
1265 minisrc_lpf[i]);
1211 }
1212 m3_wr_assp_code(sc, 0x400 + MINISRC_COEF_LOC + size, 0x8000);
1213 /* the minisrc is the only thing on our task list */
1214 m3_wr_assp_data(sc, KDATA_TASK0, 0x400);
1215 /* init the mixer number */
1216 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 0);
1217 /* extreme kernel master volume */
1266 }
1267 m3_wr_assp_code(sc, 0x400 + MINISRC_COEF_LOC + size, 0x8000);
1268 /* the minisrc is the only thing on our task list */
1269 m3_wr_assp_data(sc, KDATA_TASK0, 0x400);
1270 /* init the mixer number */
1271 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 0);
1272 /* extreme kernel master volume */
1218 m3_wr_assp_data(sc, KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
1219 m3_wr_assp_data(sc, KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
1273 m3_wr_assp_data(sc, KDATA_DAC_LEFT_VOLUME, M3_DEFAULT_VOL);
1274 m3_wr_assp_data(sc, KDATA_DAC_RIGHT_VOLUME, M3_DEFAULT_VOL);
1220
1221 m3_amp_enable(sc);
1222
1223 /* [m3_assp_client_init] (only one client at index 0) */
1224 for (i=0x1100 ; i<0x1c00 ; i++) {
1225 m3_wr_assp_data(sc, i, 0); /* zero entire dac/adc area */
1226 }
1227

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1276 m3_amp_enable(sc);
1277
1278 /* [m3_assp_client_init] (only one client at index 0) */
1279 for (i=0x1100 ; i<0x1c00 ; i++) {
1280 m3_wr_assp_data(sc, i, 0); /* zero entire dac/adc area */
1281 }
1282

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