1/*
2 * This supports the ENSONIQ AudioPCI board based on the ES1370.
3 *
4 * Copyright (c) 1998 Joachim Kuebart <joki@kuebart.stuttgart.netsurf.de>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice immediately at the beginning of the file, without modification,
12 * this list of conditions, and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Absolutely no warranty of function or purpose is made by the author
17 * Joachim Kuebart.
18 * 4. Modifications may be freely made to this file if the above conditions
19 * are met.
20 *
| 1/*
2 * This supports the ENSONIQ AudioPCI board based on the ES1370.
3 *
4 * Copyright (c) 1998 Joachim Kuebart <joki@kuebart.stuttgart.netsurf.de>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice immediately at the beginning of the file, without modification,
12 * this list of conditions, and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Absolutely no warranty of function or purpose is made by the author
17 * Joachim Kuebart.
18 * 4. Modifications may be freely made to this file if the above conditions
19 * are met.
20 *
|
22 */
23
24#ifndef _ES1370_REG_H
25#define _ES1370_REG_H
26
27#define ES1370_REG_CONTROL 0x00
28#define ES1370_REG_STATUS 0x04
29#define ES1370_REG_UART_DATA 0x08
30#define ES1370_REG_UART_STATUS 0x09
31#define ES1370_REG_UART_CONTROL 0x09
32#define ES1370_REG_UART_TEST 0x0a
33#define ES1370_REG_MEMPAGE 0x0c
34#define ES1370_REG_CODEC 0x10
35#define CODEC_INDEX_SHIFT 8
36#define ES1370_REG_SERIAL_CONTROL 0x20
37#define ES1370_REG_DAC1_SCOUNT 0x24
38#define ES1370_REG_DAC2_SCOUNT 0x28
39#define ES1370_REG_ADC_SCOUNT 0x2c
40
41#define ES1370_REG_DAC1_FRAMEADR 0xc30
42#define ES1370_REG_DAC1_FRAMECNT 0xc34
43#define ES1370_REG_DAC2_FRAMEADR 0xc38
44#define ES1370_REG_DAC2_FRAMECNT 0xc3c
45#define ES1370_REG_ADC_FRAMEADR 0xd30
46#define ES1370_REG_ADC_FRAMECNT 0xd34
47
48#define DAC2_SRTODIV(x) (((1411200 + (x) / 2) / (x) - 2) & 0x1fff)
49#define DAC2_DIVTOSR(x) (1411200 / ((x) + 2))
50
51#define CTRL_ADC_STOP 0x80000000 /* 1 = ADC stopped */
52#define CTRL_XCTL1 0x40000000 /* SERR pin if enabled */
53#define CTRL_OPEN 0x20000000 /* no function, can be read and
54 * written */
55#define CTRL_PCLKDIV 0x1fff0000 /* ADC/DAC2 clock divider */
56#define CTRL_SH_PCLKDIV 16
57#define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1
58 * = I2S */
59#define CTRL_M_SBB 0x00004000 /* DAC2 clock: 0 = PCLKDIV, 1 = MPEG */
60#define CTRL_WTSRSEL 0x00003000 /* DAC1 clock freq: 0=5512, 1=11025,
61 * 2=22050, 3=44100 */
62#define CTRL_SH_WTSRSEL 12
63#define CTRL_DAC_SYNC 0x00000800 /* 1 = DAC2 runs off DAC1 clock */
64#define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
65#define CTRL_M_CB 0x00000200 /* recording source: 0 = ADC, 1 =
66 * MPEG */
67#define CTRL_XCTL0 0x00000100 /* 0 = Line in, 1 = Line out */
68#define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
69#define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
70#define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
71#define CTRL_ADC_EN 0x00000010 /* enable ADC */
72#define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
73#define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port (presumably
74 * at address 0x200) */
75#define CTRL_CDC_EN 0x00000002 /* enable serial (CODEC) interface */
76#define CTRL_SERR_DIS 0x00000001 /* 1 = disable PCI SERR signal */
77
78#define SCTRL_P2ENDINC 0x00380000 /* */
79#define SCTRL_SH_P2ENDINC 19
80#define SCTRL_P2STINC 0x00070000 /* */
81#define SCTRL_SH_P2STINC 16
82#define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
83#define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
84#define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
85#define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
86#define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
87#define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
88#define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
89#define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
90#define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for
91 * DAC1 */
92#define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample
93 * when disabled */
94#define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
95#define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
96#define SCTRL_R1FMT 0x00000030 /* format mask */
97#define SCTRL_SH_R1FMT 4
98#define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
99#define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
100#define SCTRL_P2FMT 0x0000000c /* format mask */
101#define SCTRL_SH_P2FMT 2
102#define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
103#define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
104#define SCTRL_P1FMT 0x00000003 /* format mask */
105#define SCTRL_SH_P1FMT 0
106
107#define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
108#define STAT_CSTAT 0x00000400 /* 1 = codec busy or codec write in
109 * progress */
110#define STAT_CBUSY 0x00000200 /* 1 = codec busy */
111#define STAT_CWRIP 0x00000100 /* 1 = codec write in progress */
112#define STAT_VC 0x00000060 /* CCB int source, 0=DAC1, 1=DAC2,
113 * 2=ADC, 3=undef */
114#define STAT_SH_VC 5
115#define STAT_MCCB 0x00000010 /* CCB int pending */
116#define STAT_UART 0x00000008 /* UART int pending */
117#define STAT_DAC1 0x00000004 /* DAC1 int pending */
118#define STAT_DAC2 0x00000002 /* DAC2 int pending */
119#define STAT_ADC 0x00000001 /* ADC int pending */
120
121#define CODEC_OMIX1 0x10
122#define CODEC_OMIX2 0x11
123#define CODEC_LIMIX1 0x12
124#define CODEC_RIMIX1 0x13
125#define CODEC_LIMIX2 0x14
126#define CODEC_RIMIX2 0x15
127#define CODEC_RES_PD 0x16
128#define CODEC_CSEL 0x17
129#define CODEC_ADSEL 0x18
130#define CODEC_MGAIN 0x19
131
132/* ES1371 specific */
133
134#define CODEC_ID_SESHIFT 10
135#define CODEC_ID_SEMASK 0x1f
136
137#define CODEC_PIRD 0x00800000 /* 0 = write AC97 register */
138#define CODEC_PIADD_MASK 0x007f0000
139#define CODEC_PIADD_SHIFT 16
140#define CODEC_PIDAT_MASK 0x0000ffff
141#define CODEC_PIDAT_SHIFT 0
142
143#define CODEC_PORD 0x00800000 /* 0 = write AC97 register */
144#define CODEC_POADD_MASK 0x007f0000
145#define CODEC_POADD_SHIFT 16
146#define CODEC_PODAT_MASK 0x0000ffff
147#define CODEC_PODAT_SHIFT 0
148
149#define CODEC_RDY 0x80000000 /* AC97 read data valid */
150#define CODEC_WIP 0x40000000 /* AC97 write in progress */
151
152#define ES1370_REG_CONTROL 0x00
153#define ES1370_REG_SERIAL_CONTROL 0x20
154#define ES1371_REG_CODEC 0x14
155#define ES1371_REG_LEGACY 0x18 /* W/R: Legacy control/status register */
156#define ES1371_REG_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
157
158#define ES1371_SYNC_RES (1<<14) /* Warm AC97 reset */
159#define ES1371_DIS_R1 (1<<19) /* record channel accumulator update disable */
160#define ES1371_DIS_P2 (1<<20) /* playback channel 2 accumulator update disable */
161#define ES1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
162#define ES1371_DIS_SRC (1<<22) /* sample rate converter disable */
163#define ES1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
164#define ES1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
165#define ES1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25) /* address of the sample rate converter */
166#define ES1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0) /* current value of the sample rate converter */
167#define ES1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff) /* current value of the sample rate converter */
168
169/*
170 * Sample rate converter addresses
171 */
172
173#define ES_SMPREG_DAC1 0x70
174#define ES_SMPREG_DAC2 0x74
175#define ES_SMPREG_ADC 0x78
176#define ES_SMPREG_TRUNC_N 0x00
177#define ES_SMPREG_INT_REGS 0x01
178#define ES_SMPREG_VFREQ_FRAC 0x03
179#define ES_SMPREG_VOL_ADC 0x6c
180#define ES_SMPREG_VOL_DAC1 0x7c
181#define ES_SMPREG_VOL_DAC2 0x7e
| 22 */
23
24#ifndef _ES1370_REG_H
25#define _ES1370_REG_H
26
27#define ES1370_REG_CONTROL 0x00
28#define ES1370_REG_STATUS 0x04
29#define ES1370_REG_UART_DATA 0x08
30#define ES1370_REG_UART_STATUS 0x09
31#define ES1370_REG_UART_CONTROL 0x09
32#define ES1370_REG_UART_TEST 0x0a
33#define ES1370_REG_MEMPAGE 0x0c
34#define ES1370_REG_CODEC 0x10
35#define CODEC_INDEX_SHIFT 8
36#define ES1370_REG_SERIAL_CONTROL 0x20
37#define ES1370_REG_DAC1_SCOUNT 0x24
38#define ES1370_REG_DAC2_SCOUNT 0x28
39#define ES1370_REG_ADC_SCOUNT 0x2c
40
41#define ES1370_REG_DAC1_FRAMEADR 0xc30
42#define ES1370_REG_DAC1_FRAMECNT 0xc34
43#define ES1370_REG_DAC2_FRAMEADR 0xc38
44#define ES1370_REG_DAC2_FRAMECNT 0xc3c
45#define ES1370_REG_ADC_FRAMEADR 0xd30
46#define ES1370_REG_ADC_FRAMECNT 0xd34
47
48#define DAC2_SRTODIV(x) (((1411200 + (x) / 2) / (x) - 2) & 0x1fff)
49#define DAC2_DIVTOSR(x) (1411200 / ((x) + 2))
50
51#define CTRL_ADC_STOP 0x80000000 /* 1 = ADC stopped */
52#define CTRL_XCTL1 0x40000000 /* SERR pin if enabled */
53#define CTRL_OPEN 0x20000000 /* no function, can be read and
54 * written */
55#define CTRL_PCLKDIV 0x1fff0000 /* ADC/DAC2 clock divider */
56#define CTRL_SH_PCLKDIV 16
57#define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1
58 * = I2S */
59#define CTRL_M_SBB 0x00004000 /* DAC2 clock: 0 = PCLKDIV, 1 = MPEG */
60#define CTRL_WTSRSEL 0x00003000 /* DAC1 clock freq: 0=5512, 1=11025,
61 * 2=22050, 3=44100 */
62#define CTRL_SH_WTSRSEL 12
63#define CTRL_DAC_SYNC 0x00000800 /* 1 = DAC2 runs off DAC1 clock */
64#define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
65#define CTRL_M_CB 0x00000200 /* recording source: 0 = ADC, 1 =
66 * MPEG */
67#define CTRL_XCTL0 0x00000100 /* 0 = Line in, 1 = Line out */
68#define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
69#define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
70#define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
71#define CTRL_ADC_EN 0x00000010 /* enable ADC */
72#define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
73#define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port (presumably
74 * at address 0x200) */
75#define CTRL_CDC_EN 0x00000002 /* enable serial (CODEC) interface */
76#define CTRL_SERR_DIS 0x00000001 /* 1 = disable PCI SERR signal */
77
78#define SCTRL_P2ENDINC 0x00380000 /* */
79#define SCTRL_SH_P2ENDINC 19
80#define SCTRL_P2STINC 0x00070000 /* */
81#define SCTRL_SH_P2STINC 16
82#define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
83#define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
84#define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
85#define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
86#define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
87#define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
88#define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
89#define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
90#define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for
91 * DAC1 */
92#define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample
93 * when disabled */
94#define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
95#define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
96#define SCTRL_R1FMT 0x00000030 /* format mask */
97#define SCTRL_SH_R1FMT 4
98#define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
99#define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
100#define SCTRL_P2FMT 0x0000000c /* format mask */
101#define SCTRL_SH_P2FMT 2
102#define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
103#define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
104#define SCTRL_P1FMT 0x00000003 /* format mask */
105#define SCTRL_SH_P1FMT 0
106
107#define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
108#define STAT_CSTAT 0x00000400 /* 1 = codec busy or codec write in
109 * progress */
110#define STAT_CBUSY 0x00000200 /* 1 = codec busy */
111#define STAT_CWRIP 0x00000100 /* 1 = codec write in progress */
112#define STAT_VC 0x00000060 /* CCB int source, 0=DAC1, 1=DAC2,
113 * 2=ADC, 3=undef */
114#define STAT_SH_VC 5
115#define STAT_MCCB 0x00000010 /* CCB int pending */
116#define STAT_UART 0x00000008 /* UART int pending */
117#define STAT_DAC1 0x00000004 /* DAC1 int pending */
118#define STAT_DAC2 0x00000002 /* DAC2 int pending */
119#define STAT_ADC 0x00000001 /* ADC int pending */
120
121#define CODEC_OMIX1 0x10
122#define CODEC_OMIX2 0x11
123#define CODEC_LIMIX1 0x12
124#define CODEC_RIMIX1 0x13
125#define CODEC_LIMIX2 0x14
126#define CODEC_RIMIX2 0x15
127#define CODEC_RES_PD 0x16
128#define CODEC_CSEL 0x17
129#define CODEC_ADSEL 0x18
130#define CODEC_MGAIN 0x19
131
132/* ES1371 specific */
133
134#define CODEC_ID_SESHIFT 10
135#define CODEC_ID_SEMASK 0x1f
136
137#define CODEC_PIRD 0x00800000 /* 0 = write AC97 register */
138#define CODEC_PIADD_MASK 0x007f0000
139#define CODEC_PIADD_SHIFT 16
140#define CODEC_PIDAT_MASK 0x0000ffff
141#define CODEC_PIDAT_SHIFT 0
142
143#define CODEC_PORD 0x00800000 /* 0 = write AC97 register */
144#define CODEC_POADD_MASK 0x007f0000
145#define CODEC_POADD_SHIFT 16
146#define CODEC_PODAT_MASK 0x0000ffff
147#define CODEC_PODAT_SHIFT 0
148
149#define CODEC_RDY 0x80000000 /* AC97 read data valid */
150#define CODEC_WIP 0x40000000 /* AC97 write in progress */
151
152#define ES1370_REG_CONTROL 0x00
153#define ES1370_REG_SERIAL_CONTROL 0x20
154#define ES1371_REG_CODEC 0x14
155#define ES1371_REG_LEGACY 0x18 /* W/R: Legacy control/status register */
156#define ES1371_REG_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
157
158#define ES1371_SYNC_RES (1<<14) /* Warm AC97 reset */
159#define ES1371_DIS_R1 (1<<19) /* record channel accumulator update disable */
160#define ES1371_DIS_P2 (1<<20) /* playback channel 2 accumulator update disable */
161#define ES1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
162#define ES1371_DIS_SRC (1<<22) /* sample rate converter disable */
163#define ES1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
164#define ES1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
165#define ES1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25) /* address of the sample rate converter */
166#define ES1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0) /* current value of the sample rate converter */
167#define ES1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff) /* current value of the sample rate converter */
168
169/*
170 * Sample rate converter addresses
171 */
172
173#define ES_SMPREG_DAC1 0x70
174#define ES_SMPREG_DAC2 0x74
175#define ES_SMPREG_ADC 0x78
176#define ES_SMPREG_TRUNC_N 0x00
177#define ES_SMPREG_INT_REGS 0x01
178#define ES_SMPREG_VFREQ_FRAC 0x03
179#define ES_SMPREG_VOL_ADC 0x6c
180#define ES_SMPREG_VOL_DAC1 0x7c
181#define ES_SMPREG_VOL_DAC2 0x7e
|