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es137x.c (52046) es137x.c (53413)
1/*
1/*
2 * Support the ENSONIQ AudioPCI board based on the ES1370 and Codec
3 * AK4531.
2 * Support the ENSONIQ AudioPCI board and Creative Labs SoundBlaster PCI
3 * boards based on the ES1370, ES1371 and ES1373 chips.
4 *
4 *
5 * Copyright (c) 1999 Russell Cattelan <cattelan@thebarn.com>
5 * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk>
6 * Copyright (c) 1998 by Joachim Kuebart. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright

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32 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
33 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
38 * OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
6 * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk>
7 * Copyright (c) 1998 by Joachim Kuebart. All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * 1. Redistributions of source code must retain the above copyright

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33 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
34 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
39 * OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
40 * $FreeBSD: head/sys/dev/sound/pci/es137x.c 52046 1999-10-09 03:50:27Z imp $
41 * $FreeBSD: head/sys/dev/sound/pci/es137x.c 53413 1999-11-19 07:29:10Z roger $
41 */
42
42 */
43
44/*
45 * Part of this code was heavily inspired by the linux driver from
46 * Thomas Sailer (sailer@ife.ee.ethz.ch)
47 * Just about everything has been touched and reworked in some way but
48 * the all the underlying sequences/timing/register values are from
49 * Thomas' code.
50 *
51*/
52
43#include "pci.h"
44#include "pcm.h"
45
46#include <dev/pcm/sound.h>
53#include "pci.h"
54#include "pcm.h"
55
56#include <dev/pcm/sound.h>
47#include <dev/pcm/pci/es1370.h>
57#include <dev/pcm/ac97.h>
58#include <dev/pcm/pci/es137x.h>
48
49#include <pci/pcireg.h>
50#include <pci/pcivar.h>
51
59
60#include <pci/pcireg.h>
61#include <pci/pcivar.h>
62
63#include <sys/sysctl.h>
64
52#if NPCI != 0
53
65#if NPCI != 0
66
67static int debug = 0;
68SYSCTL_INT(_debug, OID_AUTO, es_debug, CTLFLAG_RW, &debug, 0, "");
69
54#define MEM_MAP_REG 0x14
55
56/* PCI IDs of supported chips */
57#define ES1370_PCI_ID 0x50001274
70#define MEM_MAP_REG 0x14
71
72/* PCI IDs of supported chips */
73#define ES1370_PCI_ID 0x50001274
74#define ES1371_PCI_ID 0x13711274
58
59/* device private data */
60struct es_info;
61
75
76/* device private data */
77struct es_info;
78
62struct es_chinfo {
79typedef struct es_chinfo {
63 struct es_info *parent;
64 pcm_channel *channel;
65 snd_dbuf *buffer;
66 int dir;
67 u_int32_t fmt;
80 struct es_info *parent;
81 pcm_channel *channel;
82 snd_dbuf *buffer;
83 int dir;
84 u_int32_t fmt;
68};
85} es_chinfo_t;
69
86
70struct es_info {
87typedef struct es_info {
71 bus_space_tag_t st;
72 bus_space_handle_t sh;
73 bus_dma_tag_t parent_dmat;
74
75 /* Contents of board's registers */
76 u_long ctrl;
77 u_long sctrl;
78 struct es_chinfo pch, rch;
88 bus_space_tag_t st;
89 bus_space_handle_t sh;
90 bus_dma_tag_t parent_dmat;
91
92 /* Contents of board's registers */
93 u_long ctrl;
94 u_long sctrl;
95 struct es_chinfo pch, rch;
79};
96} es_info_t;
80
81/* -------------------------------------------------------------------- */
97
98/* -------------------------------------------------------------------- */
82
83/* prototypes */
99/* prototypes */
100
101static u_int es1371_wait_src_ready(es_info_t *);
102static void es1371_src_write(es_info_t *, u_short, unsigned short);
103static u_int es1371_adc_rate (es_info_t *, u_int, int);
104static u_int es1371_dac1_rate(es_info_t *, u_int, int);
105static u_int es1371_dac2_rate(es_info_t *, u_int, int);
106static void es1371_wrcodec(void *, int, u_int32_t);
107static u_int32_t es1371_rdcodec(void *, u_int32_t);
108static int es1371_init(es_info_t *es);
109static int eschan1371_setspeed(void *data, u_int32_t speed);
110
84static int es_init(struct es_info *);
85static void es_intr(void *);
86static int write_codec(struct es_info *, u_char, u_char);
87
88/* channel interface */
89static void *eschan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir);
111static int es_init(struct es_info *);
112static void es_intr(void *);
113static int write_codec(struct es_info *, u_char, u_char);
114
115/* channel interface */
116static void *eschan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir);
90static int eschan_setdir(void *data, int dir);
91static int eschan_setformat(void *data, u_int32_t format);
92static int eschan_setspeed(void *data, u_int32_t speed);
93static int eschan_setblocksize(void *data, u_int32_t blocksize);
94static int eschan_trigger(void *data, int go);
95static int eschan_getptr(void *data);
117static int eschan_setdir(void *data, int dir);
118static int eschan_setformat(void *data, u_int32_t format);
119static int eschan_setspeed(void *data, u_int32_t speed);
120static int eschan_setblocksize(void *data, u_int32_t blocksize);
121static int eschan_trigger(void *data, int go);
122static int eschan_getptr(void *data);
96static pcmchan_caps *eschan_getcaps(void *data);
97
98static pcmchan_caps es_playcaps = {
99 4000, 48000,
100 AFMT_STEREO | AFMT_U8 | AFMT_S16_LE,
101 AFMT_STEREO | AFMT_S16_LE
102};
103

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386
387 bus_space_write_4(es->st, es->sh, ES1370_REG_SERIAL_CONTROL, sctrl);
388 bus_space_write_4(es->st, es->sh, ES1370_REG_SERIAL_CONTROL, es->sctrl);
389
390 if (intsrc & STAT_DAC2) chn_intr(es->pch.channel);
391 if (intsrc & STAT_ADC) chn_intr(es->rch.channel);
392}
393
123static pcmchan_caps *eschan_getcaps(void *data);
124
125static pcmchan_caps es_playcaps = {
126 4000, 48000,
127 AFMT_STEREO | AFMT_U8 | AFMT_S16_LE,
128 AFMT_STEREO | AFMT_S16_LE
129};
130

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413
414 bus_space_write_4(es->st, es->sh, ES1370_REG_SERIAL_CONTROL, sctrl);
415 bus_space_write_4(es->st, es->sh, ES1370_REG_SERIAL_CONTROL, es->sctrl);
416
417 if (intsrc & STAT_DAC2) chn_intr(es->pch.channel);
418 if (intsrc & STAT_ADC) chn_intr(es->rch.channel);
419}
420
421
422/* ES1371 specific code */
423
424#define CODEC_ID_SESHIFT 10
425#define CODEC_ID_SEMASK 0x1f
426
427#define CODEC_PIRD 0x00800000 /* 0 = write AC97 register */
428#define CODEC_PIADD_MASK 0x007f0000
429#define CODEC_PIADD_SHIFT 16
430#define CODEC_PIDAT_MASK 0x0000ffff
431#define CODEC_PIDAT_SHIFT 0
432
433#define CODEC_PORD 0x00800000 /* 0 = write AC97 register */
434#define CODEC_POADD_MASK 0x007f0000
435#define CODEC_POADD_SHIFT 16
436#define CODEC_PODAT_MASK 0x0000ffff
437#define CODEC_PODAT_SHIFT 0
438
439#define CODEC_RDY 0x80000000 /* AC97 read data valid */
440#define CODEC_WIP 0x40000000 /* AC97 write in progress */
441
442#define ES1370_REG_CONTROL 0x00
443#define ES1370_REG_SERIAL_CONTROL 0x20
444#define ES1371_REG_CODEC 0x14
445#define ES1371_REG_LEGACY 0x18 /* W/R: Legacy control/status register */
446#define ES1371_REG_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
447
448#define ES1371_SYNC_RES (1<<14) /* Warm AC97 reset */
449#define ES1371_DIS_R1 (1<<19) /* record channel accumulator update disable */
450#define ES1371_DIS_P2 (1<<20) /* playback channel 2 accumulator update disable */
451#define ES1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
452#define ES1371_DIS_SRC (1<<22) /* sample rate converter disable */
453#define ES1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
454#define ES1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
455#define ES1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25) /* address of the sample rate converter */
456#define ES1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0) /* current value of the sample rate converter */
457#define ES1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff) /* current value of the sample rate converter */
458
459/*
460 * Sample rate converter addresses
461 */
462
463#define ES_SMPREG_DAC1 0x70
464#define ES_SMPREG_DAC2 0x74
465#define ES_SMPREG_ADC 0x78
466#define ES_SMPREG_TRUNC_N 0x00
467#define ES_SMPREG_INT_REGS 0x01
468#define ES_SMPREG_VFREQ_FRAC 0x03
469#define ES_SMPREG_VOL_ADC 0x6c
470#define ES_SMPREG_VOL_DAC1 0x7c
471#define ES_SMPREG_VOL_DAC2 0x7e
472
473
474int
475es1371_init(struct es_info *es)
476{
477 int idx;
478
479 if(debug > 0) printf("es_init\n");
480
481 es->ctrl = 0;
482 es->sctrl = 0;
483 /* initialize the chips */
484 bus_space_write_4(es->st, es->sh, ES1370_REG_CONTROL, es->ctrl);
485 bus_space_write_4(es->st, es->sh, ES1370_REG_SERIAL_CONTROL, es->sctrl);
486 bus_space_write_4(es->st, es->sh, ES1371_REG_LEGACY, 0);
487 /* AC'97 warm reset to start the bitclk */
488 bus_space_write_4(es->st, es->sh, ES1371_REG_LEGACY, es->ctrl | ES1371_SYNC_RES);
489 DELAY(2000);
490 bus_space_write_4(es->st, es->sh, ES1370_REG_SERIAL_CONTROL,es->ctrl);
491 /* Init the sample rate converter */
492 bus_space_write_4(es->st, es->sh, ES1371_REG_SMPRATE, ES1371_DIS_SRC);
493 for (idx = 0; idx < 0x80; idx++)
494 es1371_src_write(es, idx, 0);
495 es1371_src_write(es, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
496 es1371_src_write(es, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
497 es1371_src_write(es, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
498 es1371_src_write(es, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
499 es1371_src_write(es, ES_SMPREG_VOL_ADC, 1 << 12);
500 es1371_src_write(es, ES_SMPREG_VOL_ADC + 1, 1 << 12);
501 es1371_src_write(es, ES_SMPREG_VOL_DAC1, 1 << 12);
502 es1371_src_write(es, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
503 es1371_src_write(es, ES_SMPREG_VOL_DAC2, 1 << 12);
504 es1371_src_write(es, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
505 es1371_adc_rate (es, 22050, 1);
506 es1371_dac1_rate(es, 22050, 1);
507 es1371_dac2_rate(es, 22050, 1);
508 /* WARNING:
509 * enabling the sample rate converter without properly programming
510 * its parameters causes the chip to lock up (the SRC busy bit will
511 * be stuck high, and I've found no way to rectify this other than
512 * power cycle)
513 */
514 bus_space_write_4(es->st, es->sh, ES1371_REG_SMPRATE, 0);
515
516 return (0);
517}
518
519void
520es1371_wrcodec(void *s, int addr, u_int32_t data)
521{
522 /* unsigned long flags; */
523 int sl;
524 unsigned t, x;
525 struct es_info *es = (struct es_info*)s;
526
527 if(debug > 0) printf("wrcodec addr 0x%x data 0x%x\n",addr,data);
528
529 for (t = 0; t < 0x1000; t++)
530 if(!(bus_space_read_4(es->st, es->sh,(ES1371_REG_CODEC & CODEC_WIP))))
531 break;
532 sl = spltty();
533 /* save the current state for later */
534 x = bus_space_read_4(es->st, es->sh, ES1371_REG_SMPRATE);
535 /* enable SRC state data in SRC mux */
536 bus_space_write_4(es->st, es->sh, ES1371_REG_SMPRATE,
537 (es1371_wait_src_ready(s) &
538 (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1)));
539 /* wait for a SAFE time to write addr/data and then do it, dammit */
540 for (t = 0; t < 0x1000; t++)
541 if (( bus_space_read_4(es->st, es->sh, ES1371_REG_SMPRATE) & 0x00070000) == 0x00010000)
542 break;
543
544 if(debug > 2) printf("one b_s_w: 0x%x 0x%x 0x%x\n",es->sh,ES1371_REG_CODEC,
545 ((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) |
546 ((data << CODEC_PODAT_SHIFT) & CODEC_PODAT_MASK));
547
548 bus_space_write_4(es->st, es->sh,ES1371_REG_CODEC,
549 ((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) |
550 ((data << CODEC_PODAT_SHIFT) & CODEC_PODAT_MASK));
551 /* restore SRC reg */
552 es1371_wait_src_ready(s);
553 if(debug > 2) printf("two b_s_w: 0x%x 0x%x 0x%x\n",es->sh,ES1371_REG_SMPRATE,x);
554 bus_space_write_4(es->st, es->sh,ES1371_REG_SMPRATE,x);
555 splx(sl);
556}
557
558u_int32_t
559es1371_rdcodec(void *s, u_int32_t addr)
560{
561 /* unsigned long flags; */
562 int sl;
563 unsigned t, x;
564
565 struct es_info *es = (struct es_info *)s;
566
567 if(debug > 0) printf("rdcodec addr 0x%x ... ",addr);
568
569 for (t = 0; t < 0x1000; t++)
570 if (!(x = bus_space_read_4(es->st,es->sh,ES1371_REG_CODEC) & CODEC_WIP))
571 break;
572 if(debug >0) printf("loop 1 t 0x%x x 0x%x ",t,x);
573
574 sl = spltty();
575
576 /* save the current state for later */
577 x = bus_space_read_4(es->st, es->sh, ES1371_REG_SMPRATE);
578 /* enable SRC state data in SRC mux */
579 bus_space_write_4(es->st, es->sh, ES1371_REG_SMPRATE,
580 (es1371_wait_src_ready(s) &
581 (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1)));
582 /* wait for a SAFE time to write addr/data and then do it, dammit */
583 for (t = 0; t < 0x5000; t++)
584 if (( x = bus_space_read_4(es->st, es->sh, ES1371_REG_SMPRATE) & 0x00070000) == 0x00010000)
585 break;
586 if(debug >0) printf("loop 2 t 0x%x x 0x%x ",t,x);
587 bus_space_write_4(es->st, es->sh,ES1371_REG_CODEC,
588 ((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | CODEC_PORD);
589
590 /* restore SRC reg */
591 es1371_wait_src_ready(s);
592 bus_space_write_4(es->st,es->sh,ES1371_REG_SMPRATE,x);
593
594 splx(sl);
595
596 /* now wait for the stinkin' data (RDY) */
597 for (t = 0; t < 0x1000; t++)
598 if ((x = bus_space_read_4(es->st,es->sh,ES1371_REG_CODEC)) & CODEC_RDY)
599 break;
600 if(debug > 0) printf("loop 3 t 0x%x 0x%x ret 0x%x\n",t,x,((x & CODEC_PIDAT_MASK) >> CODEC_PIDAT_SHIFT));
601 return ((x & CODEC_PIDAT_MASK) >> CODEC_PIDAT_SHIFT);
602}
603
604
605
606
607static u_int
608es1371_src_read(es_info_t *es, u_short reg){
609
610 unsigned int r;
611
612 r = es1371_wait_src_ready(es) &
613 (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1);
614 r |= ES1371_SRC_RAM_ADDRO(reg);
615 bus_space_write_4(es->st, es->sh,ES1371_REG_SMPRATE,r);
616 return ES1371_SRC_RAM_DATAI(es1371_wait_src_ready(es));
617}
618
619static void
620es1371_src_write(es_info_t *es, u_short reg, u_short data){
621 u_int r;
622
623 r = es1371_wait_src_ready(es) &
624 (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1);
625 r |= ES1371_SRC_RAM_ADDRO(reg) | ES1371_SRC_RAM_DATAO(data);
626 /* printf("es1371_src_write 0x%x 0x%x\n",ES1371_REG_SMPRATE,r | ES1371_SRC_RAM_WE); */
627 bus_space_write_4(es->st, es->sh,ES1371_REG_SMPRATE,r | ES1371_SRC_RAM_WE);
628}
629
630static u_int
631es1371_adc_rate(es_info_t *es, u_int rate, int set){
632 u_int n, truncm, freq, result;
633
634 if (rate > 48000)
635 rate = 48000;
636 if (rate < 4000)
637 rate = 4000;
638 n = rate / 3000;
639 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
640 n--;
641 truncm = (21 * n - 1) | 1;
642 freq = ((48000UL << 15) / rate) * n;
643 result = (48000UL << 15) / (freq / n);
644 if (set) {
645 if (rate >= 24000) {
646 if (truncm > 239)
647 truncm = 239;
648 es1371_src_write(es, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
649 (((239 - truncm) >> 1) << 9) | (n << 4));
650 } else {
651 if (truncm > 119)
652 truncm = 119;
653 es1371_src_write(es, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
654 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
655 }
656 es1371_src_write(es, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
657 (es1371_src_read(es, ES_SMPREG_ADC + ES_SMPREG_INT_REGS) &
658 0x00ff) | ((freq >> 5) & 0xfc00));
659 es1371_src_write(es, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
660 es1371_src_write(es, ES_SMPREG_VOL_ADC, n << 8);
661 es1371_src_write(es, ES_SMPREG_VOL_ADC + 1, n << 8);
662 }
663 return result;
664}
665
666static u_int
667es1371_dac1_rate(es_info_t *es, u_int rate, int set){
668 u_int freq, r, result;
669
670 if (rate > 48000)
671 rate = 48000;
672 if (rate < 4000)
673 rate = 4000;
674 freq = (rate << 15) / 3000;
675 result = (freq * 3000) >> 15;
676 if (set) {
677 r = (es1371_wait_src_ready(es) & (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1));
678 bus_space_write_4(es->st, es->sh,ES1371_REG_SMPRATE,r);
679 es1371_src_write(es, ES_SMPREG_DAC1 +
680 ES_SMPREG_INT_REGS,
681 (es1371_src_read(es,
682 ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS) & 0x00ff) | ((freq >> 5) & 0xfc00));
683 es1371_src_write(es, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
684 r = (es1371_wait_src_ready(es) & (ES1371_DIS_SRC | ES1371_DIS_P2 | ES1371_DIS_R1));
685 bus_space_write_4(es->st, es->sh,ES1371_REG_SMPRATE,r);
686 }
687 return result;
688}
689
690static u_int
691es1371_dac2_rate(es_info_t *es, u_int rate, int set){
692 u_int freq, r, result;
693
694 if (rate > 48000)
695 rate = 48000;
696 if (rate < 4000)
697 rate = 4000;
698 freq = (rate << 15) / 3000;
699 result = (freq * 3000) >> 15;
700 if (set) {
701 r = (es1371_wait_src_ready(es) & (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_P2 | ES1371_DIS_R1));
702 bus_space_write_4(es->st, es->sh,ES1371_REG_SMPRATE,r);
703 /* if(debug > 0) printf("dac2_rate 0x%x\n",bus_space_read_4(es->st, es->sh,ES1371_REG_SMPRATE)); */
704 es1371_src_write(es, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
705 (es1371_src_read(es, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS) &
706 0x00ff) | ((freq >> 5) & 0xfc00));
707 es1371_src_write(es, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
708 r = (es1371_wait_src_ready(es) & (ES1371_DIS_SRC | ES1371_DIS_P1 | ES1371_DIS_R1));
709 bus_space_write_4(es->st, es->sh,ES1371_REG_SMPRATE,r);
710 /* if(debug > 0) printf("dac2_rate 0x%x\n",bus_space_read_4(es->st, es->sh,ES1371_REG_SMPRATE)); */
711 }
712 return result;
713}
714
715
716static u_int
717es1371_wait_src_ready(es_info_t *es){
718 u_int t, r;
719
720 for (t = 0; t < 500; t++) {
721 if (!((r = bus_space_read_4(es->st, es->sh,ES1371_REG_SMPRATE)) & ES1371_SRC_RAM_BUSY)){
722 return r;
723 }
724 DELAY(1000);
725 }
726 printf("es1371: wait source ready timeout 0x%x [0x%x]\n", ES1371_REG_SMPRATE, r);
727 return 0;
728}
729
730
731int
732eschan1371_setspeed(void *data, u_int32_t speed)
733{
734 struct es_chinfo *ch = data;
735 struct es_info *es = ch->parent;
736
737 /* rec/play speeds locked together - should indicate in flags */
738 es1371_dac2_rate(es, speed, 1); /* play */
739 es1371_adc_rate (es, speed, 1); /* record */
740
741 return speed; /* XXX calc real speed */
742}
743
744
745
394/* -------------------------------------------------------------------- */
395
396/*
397 * Probe and attach the card
398 */
399
400static int
401es_init(struct es_info *es)

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418}
419
420static int
421es_pci_probe(device_t dev)
422{
423 if (pci_get_devid(dev) == ES1370_PCI_ID) {
424 device_set_desc(dev, "AudioPCI ES1370");
425 return 0;
746/* -------------------------------------------------------------------- */
747
748/*
749 * Probe and attach the card
750 */
751
752static int
753es_init(struct es_info *es)

--- 16 unchanged lines hidden (view full) ---

770}
771
772static int
773es_pci_probe(device_t dev)
774{
775 if (pci_get_devid(dev) == ES1370_PCI_ID) {
776 device_set_desc(dev, "AudioPCI ES1370");
777 return 0;
778 } else if (pci_get_devid(dev) == ES1371_PCI_ID) {
779 device_set_desc(dev, "AudioPCI ES1371");
780 return 0;
426 }
427 return ENXIO;
428}
429
430static int
431es_pci_attach(device_t dev)
432{
433 snddev_info *d;
434 u_int32_t data;
435 struct es_info *es = 0;
436 int type = 0;
437 int regid;
438 struct resource *reg = 0;
439 int mapped;
440 int irqid;
441 struct resource *irq = 0;
442 void *ih = 0;
443 char status[SND_STATUSLEN];
781 }
782 return ENXIO;
783}
784
785static int
786es_pci_attach(device_t dev)
787{
788 snddev_info *d;
789 u_int32_t data;
790 struct es_info *es = 0;
791 int type = 0;
792 int regid;
793 struct resource *reg = 0;
794 int mapped;
795 int irqid;
796 struct resource *irq = 0;
797 void *ih = 0;
798 char status[SND_STATUSLEN];
799 struct ac97_info *codec;
444
445 d = device_get_softc(dev);
446 if ((es = malloc(sizeof *es, M_DEVBUF, M_NOWAIT)) == NULL) {
447 device_printf(dev, "cannot allocate softc\n");
448 return ENXIO;
449 }
450 bzero(es, sizeof *es);
451

--- 20 unchanged lines hidden (view full) ---

472 es->sh = rman_get_bushandle(reg);
473 mapped++;
474 }
475 }
476 if (mapped == 0) {
477 device_printf(dev, "unable to map register space\n");
478 goto bad;
479 }
800
801 d = device_get_softc(dev);
802 if ((es = malloc(sizeof *es, M_DEVBUF, M_NOWAIT)) == NULL) {
803 device_printf(dev, "cannot allocate softc\n");
804 return ENXIO;
805 }
806 bzero(es, sizeof *es);
807

--- 20 unchanged lines hidden (view full) ---

828 es->sh = rman_get_bushandle(reg);
829 mapped++;
830 }
831 }
832 if (mapped == 0) {
833 device_printf(dev, "unable to map register space\n");
834 goto bad;
835 }
480
481 if (es_init(es) == -1) {
836
837 if (pci_get_devid(dev) == ES1371_PCI_ID) {
838 if(-1 == es1371_init(es)){
482 device_printf(dev, "unable to initialize the card\n");
839 device_printf(dev, "unable to initialize the card\n");
840 goto bad;
841 }
842 codec = ac97_create(es,(ac97_read *)es1371_rdcodec,(ac97_write *)es1371_wrcodec);
843 if (codec == NULL) goto bad;
844 /* our init routine does everything for us */
845 /* set to NULL; flag mixer_init not to run the ac97_init */
846 /* ac97_mixer.init = NULL; */
847 mixer_init(d, &ac97_mixer, codec);
848 /* change the routine for setting speed */
849 es_chantemplate.setspeed = eschan1371_setspeed;
850 } else if (pci_get_devid(dev) == ES1370_PCI_ID) {
851 if (-1 == es_init(es)){
852 device_printf(dev, "unable to initialize the card\n");
483 goto bad;
853 goto bad;
854 }
855 mixer_init(d, &es_mixer, es);
484 }
856 }
485 mixer_init(d, &es_mixer, es);
857
486
487 irqid = 0;
488 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &irqid,
489 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
490 if (!irq
491 || bus_setup_intr(dev, irq, INTR_TYPE_TTY, es_intr, es, &ih)) {
492 device_printf(dev, "unable to map interrupt\n");
493 goto bad;

--- 41 unchanged lines hidden (view full) ---

535 es_methods,
536 sizeof(snddev_info),
537};
538
539static devclass_t pcm_devclass;
540
541DRIVER_MODULE(es, pci, es_driver, pcm_devclass, 0, 0);
542
858
859 irqid = 0;
860 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &irqid,
861 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
862 if (!irq
863 || bus_setup_intr(dev, irq, INTR_TYPE_TTY, es_intr, es, &ih)) {
864 device_printf(dev, "unable to map interrupt\n");
865 goto bad;

--- 41 unchanged lines hidden (view full) ---

907 es_methods,
908 sizeof(snddev_info),
909};
910
911static devclass_t pcm_devclass;
912
913DRIVER_MODULE(es, pci, es_driver, pcm_devclass, 0, 0);
914
915
543#endif /* NPCI != 0 */
916#endif /* NPCI != 0 */