1/*
2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
24 * SUCH DAMAGE.
25 *
| 1/*
2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
24 * SUCH DAMAGE.
25 *
|
26 * $FreeBSD: head/sys/dev/sound/pci/cs4281.c 73770 2001-03-05 17:30:43Z cg $
| 26 * $FreeBSD: head/sys/dev/sound/pci/cs4281.c 74763 2001-03-24 23:10:29Z cg $
|
27 *
28 * The order of pokes in the initiation sequence is based on Linux
29 * driver by Thomas Sailer, gw boynton (wesb@crystal.cirrus.com), tom
30 * woller (twoller@crystal.cirrus.com). Shingo Watanabe (nabe@nabechan.org)
31 * contributed towards power management.
32 */
33
34#include <dev/sound/pcm/sound.h>
35#include <dev/sound/pcm/ac97.h>
36
37#include <pci/pcireg.h>
38#include <pci/pcivar.h>
39
40#include <dev/sound/pci/cs4281.h>
41
42#define CS4281_BUFFER_SIZE 16384
43
44/* Max fifo size for full duplex is 64 */
45#define CS4281_FIFO_SIZE 15
46
47/* DMA Engine Indices */
48#define CS4281_DMA_PLAY 0
49#define CS4281_DMA_REC 1
50
51/* Misc */
52
53#define MIN(x,y) (x) < (y) ? (x) : (y)
54#define MAX(x,y) (x) > (y) ? (x) : (y)
55
56#define inline __inline
57
58#ifndef DEB
59#define DEB(x) /* x */
60#endif /* DEB */
61
62/* ------------------------------------------------------------------------- */
63/* Structures */
64
65struct sc_info;
66
67/* channel registers */
68struct sc_chinfo {
69 struct sc_info *parent;
70
| 27 *
28 * The order of pokes in the initiation sequence is based on Linux
29 * driver by Thomas Sailer, gw boynton (wesb@crystal.cirrus.com), tom
30 * woller (twoller@crystal.cirrus.com). Shingo Watanabe (nabe@nabechan.org)
31 * contributed towards power management.
32 */
33
34#include <dev/sound/pcm/sound.h>
35#include <dev/sound/pcm/ac97.h>
36
37#include <pci/pcireg.h>
38#include <pci/pcivar.h>
39
40#include <dev/sound/pci/cs4281.h>
41
42#define CS4281_BUFFER_SIZE 16384
43
44/* Max fifo size for full duplex is 64 */
45#define CS4281_FIFO_SIZE 15
46
47/* DMA Engine Indices */
48#define CS4281_DMA_PLAY 0
49#define CS4281_DMA_REC 1
50
51/* Misc */
52
53#define MIN(x,y) (x) < (y) ? (x) : (y)
54#define MAX(x,y) (x) > (y) ? (x) : (y)
55
56#define inline __inline
57
58#ifndef DEB
59#define DEB(x) /* x */
60#endif /* DEB */
61
62/* ------------------------------------------------------------------------- */
63/* Structures */
64
65struct sc_info;
66
67/* channel registers */
68struct sc_chinfo {
69 struct sc_info *parent;
70
|
71 snd_dbuf *buffer;
72 pcm_channel *channel;
| 71 struct snd_dbuf *buffer;
72 struct pcm_channel *channel;
|
73
74 u_int32_t spd, fmt, bps, blksz;
75
76 int dma_setup, dma_active, dma_chan;
77};
78
79/* device private data */
80struct sc_info {
81 device_t dev;
82 u_int32_t type;
83
84 bus_space_tag_t st;
85 bus_space_handle_t sh;
86 bus_dma_tag_t parent_dmat;
87
88 struct resource *reg, *irq, *mem;
89 int regtype, regid, irqid, memid;
90 void *ih;
91
92 int power;
93 struct sc_chinfo pch;
94 struct sc_chinfo rch;
95};
96
97/* -------------------------------------------------------------------- */
98/* prototypes */
99
100/* ADC/DAC control */
101static u_int32_t adcdac_go(struct sc_chinfo *ch, u_int32_t go);
102static void adcdac_prog(struct sc_chinfo *ch);
103
104/* power management and interrupt control */
105static void cs4281_intr(void *);
106static int cs4281_power(struct sc_info *, int);
107static int cs4281_init(struct sc_info *);
108
109/* talk to the card */
110static u_int32_t cs4281_rd(struct sc_info *, int);
111static void cs4281_wr(struct sc_info *, int, u_int32_t);
112
113/* misc */
114static u_int8_t cs4281_rate_to_rv(u_int32_t);
115static u_int32_t cs4281_format_to_dmr(u_int32_t);
116static u_int32_t cs4281_format_to_bps(u_int32_t);
117
118/* -------------------------------------------------------------------- */
119/* formats (do not add formats without editing cs_fmt_tab) */
120
121static u_int32_t cs4281_fmts[] = {
122 AFMT_U8,
123 AFMT_U8 | AFMT_STEREO,
124 AFMT_S8,
125 AFMT_S8 | AFMT_STEREO,
126 AFMT_S16_LE,
127 AFMT_S16_LE | AFMT_STEREO,
128 AFMT_U16_LE,
129 AFMT_U16_LE | AFMT_STEREO,
130 AFMT_S16_BE,
131 AFMT_S16_BE | AFMT_STEREO,
132 AFMT_U16_BE,
133 AFMT_U16_BE | AFMT_STEREO,
134 0
135};
136
| 73
74 u_int32_t spd, fmt, bps, blksz;
75
76 int dma_setup, dma_active, dma_chan;
77};
78
79/* device private data */
80struct sc_info {
81 device_t dev;
82 u_int32_t type;
83
84 bus_space_tag_t st;
85 bus_space_handle_t sh;
86 bus_dma_tag_t parent_dmat;
87
88 struct resource *reg, *irq, *mem;
89 int regtype, regid, irqid, memid;
90 void *ih;
91
92 int power;
93 struct sc_chinfo pch;
94 struct sc_chinfo rch;
95};
96
97/* -------------------------------------------------------------------- */
98/* prototypes */
99
100/* ADC/DAC control */
101static u_int32_t adcdac_go(struct sc_chinfo *ch, u_int32_t go);
102static void adcdac_prog(struct sc_chinfo *ch);
103
104/* power management and interrupt control */
105static void cs4281_intr(void *);
106static int cs4281_power(struct sc_info *, int);
107static int cs4281_init(struct sc_info *);
108
109/* talk to the card */
110static u_int32_t cs4281_rd(struct sc_info *, int);
111static void cs4281_wr(struct sc_info *, int, u_int32_t);
112
113/* misc */
114static u_int8_t cs4281_rate_to_rv(u_int32_t);
115static u_int32_t cs4281_format_to_dmr(u_int32_t);
116static u_int32_t cs4281_format_to_bps(u_int32_t);
117
118/* -------------------------------------------------------------------- */
119/* formats (do not add formats without editing cs_fmt_tab) */
120
121static u_int32_t cs4281_fmts[] = {
122 AFMT_U8,
123 AFMT_U8 | AFMT_STEREO,
124 AFMT_S8,
125 AFMT_S8 | AFMT_STEREO,
126 AFMT_S16_LE,
127 AFMT_S16_LE | AFMT_STEREO,
128 AFMT_U16_LE,
129 AFMT_U16_LE | AFMT_STEREO,
130 AFMT_S16_BE,
131 AFMT_S16_BE | AFMT_STEREO,
132 AFMT_U16_BE,
133 AFMT_U16_BE | AFMT_STEREO,
134 0
135};
136
|
137static pcmchan_caps cs4281_caps = {6024, 48000, cs4281_fmts, 0};
| 137static struct pcmchan_caps cs4281_caps = {6024, 48000, cs4281_fmts, 0};
|
138
139/* -------------------------------------------------------------------- */
140/* Hardware */
141
142static inline u_int32_t
143cs4281_rd(struct sc_info *sc, int regno)
144{
145 return bus_space_read_4(sc->st, sc->sh, regno);
146}
147
148static inline void
149cs4281_wr(struct sc_info *sc, int regno, u_int32_t data)
150{
151 bus_space_write_4(sc->st, sc->sh, regno, data);
152 DELAY(100);
153}
154
155static inline void
156cs4281_clr4(struct sc_info *sc, int regno, u_int32_t mask)
157{
158 u_int32_t r;
159 r = cs4281_rd(sc, regno);
160 cs4281_wr(sc, regno, r & ~mask);
161}
162
163static inline void
164cs4281_set4(struct sc_info *sc, int regno, u_int32_t mask)
165{
166 u_int32_t v;
167 v = cs4281_rd(sc, regno);
168 cs4281_wr(sc, regno, v | mask);
169}
170
171static int
172cs4281_waitset(struct sc_info *sc, int regno, u_int32_t mask, int tries)
173{
174 u_int32_t v;
175
176 while(tries > 0) {
177 DELAY(100);
178 v = cs4281_rd(sc, regno);
179 if ((v & mask) == mask) break;
180 tries --;
181 }
182 return tries;
183}
184
185static int
186cs4281_waitclr(struct sc_info *sc, int regno, u_int32_t mask, int tries)
187{
188 u_int32_t v;
189
190 while(tries > 0) {
191 DELAY(100);
192 v = ~ cs4281_rd(sc, regno);
193 if (v & mask) break;
194 tries --;
195 }
196 return tries;
197}
198
199/* ------------------------------------------------------------------------- */
200/* Register value mapping functions */
201
202static u_int32_t cs4281_rates[] = {48000, 44100, 22050, 16000, 11025, 8000};
203#define CS4281_NUM_RATES sizeof(cs4281_rates)/sizeof(cs4281_rates[0])
204
205static u_int8_t
206cs4281_rate_to_rv(u_int32_t rate)
207{
208 u_int32_t v;
209
210 for (v = 0; v < CS4281_NUM_RATES; v++) {
211 if (rate == cs4281_rates[v]) return v;
212 }
213
214 v = 1536000 / rate;
215 if (v > 255 || v < 32) v = 5; /* default to 8k */
216 return v;
217}
218
219static u_int32_t
220cs4281_rv_to_rate(u_int8_t rv)
221{
222 u_int32_t r;
223
224 if (rv < CS4281_NUM_RATES) return cs4281_rates[rv];
225 r = 1536000 / rv;
226 return r;
227}
228
229static inline u_int32_t
230cs4281_format_to_dmr(u_int32_t format)
231{
232 u_int32_t dmr = 0;
233 if (AFMT_8BIT & format) dmr |= CS4281PCI_DMR_SIZE8;
234 if (!(AFMT_STEREO & format)) dmr |= CS4281PCI_DMR_MONO;
235 if (AFMT_BIGENDIAN & format) dmr |= CS4281PCI_DMR_BEND;
236 if (!(AFMT_SIGNED & format)) dmr |= CS4281PCI_DMR_USIGN;
237 return dmr;
238}
239
240static inline u_int32_t
241cs4281_format_to_bps(u_int32_t format)
242{
243 return ((AFMT_8BIT & format) ? 1 : 2) * ((AFMT_STEREO & format) ? 2 : 1);
244}
245
246/* -------------------------------------------------------------------- */
247/* ac97 codec */
248
249static u_int32_t
250cs4281_rdcd(kobj_t obj, void *devinfo, int regno)
251{
252 struct sc_info *sc = (struct sc_info *)devinfo;
253 int codecno;
254
255 codecno = regno >> 8;
256 regno &= 0xff;
257
258 /* Remove old state */
259 cs4281_rd(sc, CS4281PCI_ACSDA);
260
261 /* Fill in AC97 register value request form */
262 cs4281_wr(sc, CS4281PCI_ACCAD, regno);
263 cs4281_wr(sc, CS4281PCI_ACCDA, 0);
264 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN |
265 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV |
266 CS4281PCI_ACCTL_CRW);
267
268 /* Wait for read to complete */
269 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) {
270 device_printf(sc->dev, "cs4281_rdcd: DCV did not go\n");
271 return 0xffffffff;
272 }
273
274 /* Wait for valid status */
275 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_VSTS, 250) == 0) {
276 device_printf(sc->dev,"cs4281_rdcd: VSTS did not come\n");
277 return 0xffffffff;
278 }
279
280 return cs4281_rd(sc, CS4281PCI_ACSDA);
281}
282
283static void
284cs4281_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
285{
286 struct sc_info *sc = (struct sc_info *)devinfo;
287 int codecno;
288
289 codecno = regno >> 8;
290 regno &= 0xff;
291
292 cs4281_wr(sc, CS4281PCI_ACCAD, regno);
293 cs4281_wr(sc, CS4281PCI_ACCDA, data);
294 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN |
295 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV);
296
297 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) {
298 device_printf(sc->dev,"cs4281_wrcd: DCV did not go\n");
299 }
300}
301
302static kobj_method_t cs4281_ac97_methods[] = {
303 KOBJMETHOD(ac97_read, cs4281_rdcd),
304 KOBJMETHOD(ac97_write, cs4281_wrcd),
305 { 0, 0 }
306};
307AC97_DECLARE(cs4281_ac97);
308
309/* ------------------------------------------------------------------------- */
310/* shared rec/play channel interface */
311
312static void *
| 138
139/* -------------------------------------------------------------------- */
140/* Hardware */
141
142static inline u_int32_t
143cs4281_rd(struct sc_info *sc, int regno)
144{
145 return bus_space_read_4(sc->st, sc->sh, regno);
146}
147
148static inline void
149cs4281_wr(struct sc_info *sc, int regno, u_int32_t data)
150{
151 bus_space_write_4(sc->st, sc->sh, regno, data);
152 DELAY(100);
153}
154
155static inline void
156cs4281_clr4(struct sc_info *sc, int regno, u_int32_t mask)
157{
158 u_int32_t r;
159 r = cs4281_rd(sc, regno);
160 cs4281_wr(sc, regno, r & ~mask);
161}
162
163static inline void
164cs4281_set4(struct sc_info *sc, int regno, u_int32_t mask)
165{
166 u_int32_t v;
167 v = cs4281_rd(sc, regno);
168 cs4281_wr(sc, regno, v | mask);
169}
170
171static int
172cs4281_waitset(struct sc_info *sc, int regno, u_int32_t mask, int tries)
173{
174 u_int32_t v;
175
176 while(tries > 0) {
177 DELAY(100);
178 v = cs4281_rd(sc, regno);
179 if ((v & mask) == mask) break;
180 tries --;
181 }
182 return tries;
183}
184
185static int
186cs4281_waitclr(struct sc_info *sc, int regno, u_int32_t mask, int tries)
187{
188 u_int32_t v;
189
190 while(tries > 0) {
191 DELAY(100);
192 v = ~ cs4281_rd(sc, regno);
193 if (v & mask) break;
194 tries --;
195 }
196 return tries;
197}
198
199/* ------------------------------------------------------------------------- */
200/* Register value mapping functions */
201
202static u_int32_t cs4281_rates[] = {48000, 44100, 22050, 16000, 11025, 8000};
203#define CS4281_NUM_RATES sizeof(cs4281_rates)/sizeof(cs4281_rates[0])
204
205static u_int8_t
206cs4281_rate_to_rv(u_int32_t rate)
207{
208 u_int32_t v;
209
210 for (v = 0; v < CS4281_NUM_RATES; v++) {
211 if (rate == cs4281_rates[v]) return v;
212 }
213
214 v = 1536000 / rate;
215 if (v > 255 || v < 32) v = 5; /* default to 8k */
216 return v;
217}
218
219static u_int32_t
220cs4281_rv_to_rate(u_int8_t rv)
221{
222 u_int32_t r;
223
224 if (rv < CS4281_NUM_RATES) return cs4281_rates[rv];
225 r = 1536000 / rv;
226 return r;
227}
228
229static inline u_int32_t
230cs4281_format_to_dmr(u_int32_t format)
231{
232 u_int32_t dmr = 0;
233 if (AFMT_8BIT & format) dmr |= CS4281PCI_DMR_SIZE8;
234 if (!(AFMT_STEREO & format)) dmr |= CS4281PCI_DMR_MONO;
235 if (AFMT_BIGENDIAN & format) dmr |= CS4281PCI_DMR_BEND;
236 if (!(AFMT_SIGNED & format)) dmr |= CS4281PCI_DMR_USIGN;
237 return dmr;
238}
239
240static inline u_int32_t
241cs4281_format_to_bps(u_int32_t format)
242{
243 return ((AFMT_8BIT & format) ? 1 : 2) * ((AFMT_STEREO & format) ? 2 : 1);
244}
245
246/* -------------------------------------------------------------------- */
247/* ac97 codec */
248
249static u_int32_t
250cs4281_rdcd(kobj_t obj, void *devinfo, int regno)
251{
252 struct sc_info *sc = (struct sc_info *)devinfo;
253 int codecno;
254
255 codecno = regno >> 8;
256 regno &= 0xff;
257
258 /* Remove old state */
259 cs4281_rd(sc, CS4281PCI_ACSDA);
260
261 /* Fill in AC97 register value request form */
262 cs4281_wr(sc, CS4281PCI_ACCAD, regno);
263 cs4281_wr(sc, CS4281PCI_ACCDA, 0);
264 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN |
265 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV |
266 CS4281PCI_ACCTL_CRW);
267
268 /* Wait for read to complete */
269 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) {
270 device_printf(sc->dev, "cs4281_rdcd: DCV did not go\n");
271 return 0xffffffff;
272 }
273
274 /* Wait for valid status */
275 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_VSTS, 250) == 0) {
276 device_printf(sc->dev,"cs4281_rdcd: VSTS did not come\n");
277 return 0xffffffff;
278 }
279
280 return cs4281_rd(sc, CS4281PCI_ACSDA);
281}
282
283static void
284cs4281_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
285{
286 struct sc_info *sc = (struct sc_info *)devinfo;
287 int codecno;
288
289 codecno = regno >> 8;
290 regno &= 0xff;
291
292 cs4281_wr(sc, CS4281PCI_ACCAD, regno);
293 cs4281_wr(sc, CS4281PCI_ACCDA, data);
294 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN |
295 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV);
296
297 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) {
298 device_printf(sc->dev,"cs4281_wrcd: DCV did not go\n");
299 }
300}
301
302static kobj_method_t cs4281_ac97_methods[] = {
303 KOBJMETHOD(ac97_read, cs4281_rdcd),
304 KOBJMETHOD(ac97_write, cs4281_wrcd),
305 { 0, 0 }
306};
307AC97_DECLARE(cs4281_ac97);
308
309/* ------------------------------------------------------------------------- */
310/* shared rec/play channel interface */
311
312static void *
|
313cs4281chan_init(kobj_t obj, void *devinfo, snd_dbuf *b, pcm_channel *c, int dir)
| 313cs4281chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
|
314{
315 struct sc_info *sc = devinfo;
316 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
317
318 ch->buffer = b;
319 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, CS4281_BUFFER_SIZE) != 0) {
320 return NULL;
321 }
322 ch->parent = sc;
323 ch->channel = c;
324
325 ch->fmt = AFMT_U8;
326 ch->spd = DSP_DEFAULT_SPEED;
327 ch->bps = 1;
328 ch->blksz = sndbuf_getsize(ch->buffer);
329
330 ch->dma_chan = (dir == PCMDIR_PLAY) ? CS4281_DMA_PLAY : CS4281_DMA_REC;
331 ch->dma_setup = 0;
332
333 adcdac_go(ch, 0);
334 adcdac_prog(ch);
335
336 return ch;
337}
338
339static int
340cs4281chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
341{
342 struct sc_chinfo *ch = data;
343 u_int32_t go;
344
345 go = adcdac_go(ch, 0);
346
347 /* 2 interrupts are possible and used in buffer (half-empty,empty),
348 * hence factor of 2. */
349 ch->blksz = MIN(blocksize, CS4281_BUFFER_SIZE / 2);
350 sndbuf_resize(ch->buffer, 2, ch->blksz);
351 ch->dma_setup = 0;
352 adcdac_prog(ch);
353 adcdac_go(ch, go);
354
355 DEB(printf("cs4281chan_setblocksize: bufsz %d Setting %d\n", blocksize, ch->blksz));
356
357 return sndbuf_getsize(ch->buffer);
358}
359
360static int
361cs4281chan_setspeed(kobj_t obj, void *data, u_int32_t speed)
362{
363 struct sc_chinfo *ch = data;
364 struct sc_info *sc = ch->parent;
365 u_int32_t go, v, r;
366
367 go = adcdac_go(ch, 0); /* pause */
368 r = (ch->dma_chan == CS4281_DMA_PLAY) ? CS4281PCI_DACSR : CS4281PCI_ADCSR;
369 v = cs4281_rate_to_rv(speed);
370 cs4281_wr(sc, r, v);
371 adcdac_go(ch, go); /* unpause */
372
373 ch->spd = cs4281_rv_to_rate(v);
374 return ch->spd;
375}
376
377static int
378cs4281chan_setformat(kobj_t obj, void *data, u_int32_t format)
379{
380 struct sc_chinfo *ch = data;
381 struct sc_info *sc = ch->parent;
382 u_int32_t v, go;
383
384 go = adcdac_go(ch, 0); /* pause */
385
386 if (ch->dma_chan == CS4281_DMA_PLAY)
387 v = CS4281PCI_DMR_TR_PLAY;
388 else
389 v = CS4281PCI_DMR_TR_REC;
390 v |= CS4281PCI_DMR_DMA | CS4281PCI_DMR_AUTO;
391 v |= cs4281_format_to_dmr(format);
392 cs4281_wr(sc, CS4281PCI_DMR(ch->dma_chan), v);
393
394 adcdac_go(ch, go); /* unpause */
395
396 ch->fmt = format;
397 ch->bps = cs4281_format_to_bps(format);
398 ch->dma_setup = 0;
399
400 return 0;
401}
402
403static int
404cs4281chan_getptr(kobj_t obj, void *data)
405{
406 struct sc_chinfo *ch = data;
407 struct sc_info *sc = ch->parent;
408 u_int32_t dba, dca, ptr;
409 int sz;
410
411 sz = sndbuf_getsize(ch->buffer);
412 dba = cs4281_rd(sc, CS4281PCI_DBA(ch->dma_chan));
413 dca = cs4281_rd(sc, CS4281PCI_DCA(ch->dma_chan));
414 ptr = (dca - dba + sz) % sz;
415
416 return ptr;
417}
418
419static int
420cs4281chan_trigger(kobj_t obj, void *data, int go)
421{
422 struct sc_chinfo *ch = data;
423
424 switch(go) {
425 case PCMTRIG_START:
426 adcdac_prog(ch);
427 adcdac_go(ch, 1);
428 break;
429 case PCMTRIG_ABORT:
430 adcdac_go(ch, 0);
431 break;
432 default:
433 break;
434 }
435
436 /* return 0 if ok */
437 return 0;
438}
439
| 314{
315 struct sc_info *sc = devinfo;
316 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
317
318 ch->buffer = b;
319 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, CS4281_BUFFER_SIZE) != 0) {
320 return NULL;
321 }
322 ch->parent = sc;
323 ch->channel = c;
324
325 ch->fmt = AFMT_U8;
326 ch->spd = DSP_DEFAULT_SPEED;
327 ch->bps = 1;
328 ch->blksz = sndbuf_getsize(ch->buffer);
329
330 ch->dma_chan = (dir == PCMDIR_PLAY) ? CS4281_DMA_PLAY : CS4281_DMA_REC;
331 ch->dma_setup = 0;
332
333 adcdac_go(ch, 0);
334 adcdac_prog(ch);
335
336 return ch;
337}
338
339static int
340cs4281chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
341{
342 struct sc_chinfo *ch = data;
343 u_int32_t go;
344
345 go = adcdac_go(ch, 0);
346
347 /* 2 interrupts are possible and used in buffer (half-empty,empty),
348 * hence factor of 2. */
349 ch->blksz = MIN(blocksize, CS4281_BUFFER_SIZE / 2);
350 sndbuf_resize(ch->buffer, 2, ch->blksz);
351 ch->dma_setup = 0;
352 adcdac_prog(ch);
353 adcdac_go(ch, go);
354
355 DEB(printf("cs4281chan_setblocksize: bufsz %d Setting %d\n", blocksize, ch->blksz));
356
357 return sndbuf_getsize(ch->buffer);
358}
359
360static int
361cs4281chan_setspeed(kobj_t obj, void *data, u_int32_t speed)
362{
363 struct sc_chinfo *ch = data;
364 struct sc_info *sc = ch->parent;
365 u_int32_t go, v, r;
366
367 go = adcdac_go(ch, 0); /* pause */
368 r = (ch->dma_chan == CS4281_DMA_PLAY) ? CS4281PCI_DACSR : CS4281PCI_ADCSR;
369 v = cs4281_rate_to_rv(speed);
370 cs4281_wr(sc, r, v);
371 adcdac_go(ch, go); /* unpause */
372
373 ch->spd = cs4281_rv_to_rate(v);
374 return ch->spd;
375}
376
377static int
378cs4281chan_setformat(kobj_t obj, void *data, u_int32_t format)
379{
380 struct sc_chinfo *ch = data;
381 struct sc_info *sc = ch->parent;
382 u_int32_t v, go;
383
384 go = adcdac_go(ch, 0); /* pause */
385
386 if (ch->dma_chan == CS4281_DMA_PLAY)
387 v = CS4281PCI_DMR_TR_PLAY;
388 else
389 v = CS4281PCI_DMR_TR_REC;
390 v |= CS4281PCI_DMR_DMA | CS4281PCI_DMR_AUTO;
391 v |= cs4281_format_to_dmr(format);
392 cs4281_wr(sc, CS4281PCI_DMR(ch->dma_chan), v);
393
394 adcdac_go(ch, go); /* unpause */
395
396 ch->fmt = format;
397 ch->bps = cs4281_format_to_bps(format);
398 ch->dma_setup = 0;
399
400 return 0;
401}
402
403static int
404cs4281chan_getptr(kobj_t obj, void *data)
405{
406 struct sc_chinfo *ch = data;
407 struct sc_info *sc = ch->parent;
408 u_int32_t dba, dca, ptr;
409 int sz;
410
411 sz = sndbuf_getsize(ch->buffer);
412 dba = cs4281_rd(sc, CS4281PCI_DBA(ch->dma_chan));
413 dca = cs4281_rd(sc, CS4281PCI_DCA(ch->dma_chan));
414 ptr = (dca - dba + sz) % sz;
415
416 return ptr;
417}
418
419static int
420cs4281chan_trigger(kobj_t obj, void *data, int go)
421{
422 struct sc_chinfo *ch = data;
423
424 switch(go) {
425 case PCMTRIG_START:
426 adcdac_prog(ch);
427 adcdac_go(ch, 1);
428 break;
429 case PCMTRIG_ABORT:
430 adcdac_go(ch, 0);
431 break;
432 default:
433 break;
434 }
435
436 /* return 0 if ok */
437 return 0;
438}
439
|
440static pcmchan_caps *
| 440static struct pcmchan_caps *
|
441cs4281chan_getcaps(kobj_t obj, void *data)
442{
443 return &cs4281_caps;
444}
445
446static kobj_method_t cs4281chan_methods[] = {
447 KOBJMETHOD(channel_init, cs4281chan_init),
448 KOBJMETHOD(channel_setformat, cs4281chan_setformat),
449 KOBJMETHOD(channel_setspeed, cs4281chan_setspeed),
450 KOBJMETHOD(channel_setblocksize, cs4281chan_setblocksize),
451 KOBJMETHOD(channel_trigger, cs4281chan_trigger),
452 KOBJMETHOD(channel_getptr, cs4281chan_getptr),
453 KOBJMETHOD(channel_getcaps, cs4281chan_getcaps),
454 { 0, 0 }
455};
456CHANNEL_DECLARE(cs4281chan);
457
458/* -------------------------------------------------------------------- */
459/* ADC/DAC control */
460
461/* adcdac_go enables/disable DMA channel, returns non-zero if DMA was
462 * active before call */
463
464static u_int32_t
465adcdac_go(struct sc_chinfo *ch, u_int32_t go)
466{
467 struct sc_info *sc = ch->parent;
468 u_int32_t going;
469
470 going = !(cs4281_rd(sc, CS4281PCI_DCR(ch->dma_chan)) & CS4281PCI_DCR_MSK);
471
472 if (go)
473 cs4281_clr4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK);
474 else
475 cs4281_set4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK);
476
477 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI);
478
479 return going;
480}
481
482static void
483adcdac_prog(struct sc_chinfo *ch)
484{
485 struct sc_info *sc = ch->parent;
486 u_int32_t go;
487
488 if (!ch->dma_setup) {
489 go = adcdac_go(ch, 0);
490 cs4281_wr(sc, CS4281PCI_DBA(ch->dma_chan),
491 vtophys(sndbuf_getbuf(ch->buffer)));
492 cs4281_wr(sc, CS4281PCI_DBC(ch->dma_chan),
493 sndbuf_getsize(ch->buffer) / ch->bps - 1);
494 ch->dma_setup = 1;
495 adcdac_go(ch, go);
496 }
497}
498
499/* -------------------------------------------------------------------- */
500/* The interrupt handler */
501
502static void
503cs4281_intr(void *p)
504{
505 struct sc_info *sc = (struct sc_info *)p;
506 u_int32_t hisr;
507
508 hisr = cs4281_rd(sc, CS4281PCI_HISR);
509
510 if (hisr == 0) return;
511
512 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_PLAY)) {
513 chn_intr(sc->pch.channel);
514 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_PLAY)); /* Clear interrupt */
515 }
516
517 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_REC)) {
518 chn_intr(sc->rch.channel);
519 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_REC)); /* Clear interrupt */
520 }
521
522 /* Signal End-of-Interrupt */
523 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI);
524}
525
526/* -------------------------------------------------------------------- */
527/* power management related */
528
529static int
530cs4281_power(struct sc_info *sc, int state)
531{
532
533 switch (state) {
534 case 0:
535 /* Permit r/w access to all BA0 registers */
536 cs4281_wr(sc, CS4281PCI_CWPR, CS4281PCI_CWPR_MAGIC);
537 /* Power on */
538 cs4281_clr4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN);
539 break;
540 case 3:
541 /* Power off card and codec */
542 cs4281_set4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN);
543 cs4281_clr4(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN);
544 break;
545 }
546
547 DEB(printf("cs4281_power %d -> %d\n", sc->power, state));
548 sc->power = state;
549
550 return 0;
551}
552
553static int
554cs4281_init(struct sc_info *sc)
555{
556 u_int32_t i, v;
557
558 /* (0) Blast clock register and serial port */
559 cs4281_wr(sc, CS4281PCI_CLKCR1, 0);
560 cs4281_wr(sc, CS4281PCI_SERMC, 0);
561
562 /* (1) Make ESYN 0 to turn sync pulse on AC97 link */
563 cs4281_wr(sc, CS4281PCI_ACCTL, 0);
564 DELAY(50);
565
566 /* (2) Effect Reset */
567 cs4281_wr(sc, CS4281PCI_SPMC, 0);
568 DELAY(100);
569 cs4281_wr(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN);
570 /* Wait 50ms for ABITCLK to become stable */
571 DELAY(50000);
572
573 /* (3) Enable Sound System Clocks */
574 cs4281_wr(sc, CS4281PCI_CLKCR1, CS4281PCI_CLKCR1_DLLP);
575 DELAY(50000); /* Wait for PLL to stabilize */
576 cs4281_wr(sc, CS4281PCI_CLKCR1,
577 CS4281PCI_CLKCR1_DLLP | CS4281PCI_CLKCR1_SWCE);
578
579 /* (4) Power Up - this combination is essential. */
580 cs4281_set4(sc, CS4281PCI_SSPM,
581 CS4281PCI_SSPM_ACLEN | CS4281PCI_SSPM_PSRCEN |
582 CS4281PCI_SSPM_CSRCEN | CS4281PCI_SSPM_MIXEN);
583
584 /* (5) Wait for clock stabilization */
585 if (cs4281_waitset(sc,
586 CS4281PCI_CLKCR1,
587 CS4281PCI_CLKCR1_DLLRDY,
588 250) == 0) {
589 device_printf(sc->dev, "Clock stabilization failed\n");
590 return -1;
591 }
592
593 /* (6) Enable ASYNC generation. */
594 cs4281_wr(sc, CS4281PCI_ACCTL,CS4281PCI_ACCTL_ESYN);
595
596 /* Wait to allow AC97 to start generating clock bit */
597 DELAY(50000);
598
599 /* Set AC97 timing */
600 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);
601
602 /* (7) Wait for AC97 ready signal */
603 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_CRDY, 250) == 0) {
604 device_printf(sc->dev, "codec did not avail\n");
605 return -1;
606 }
607
608 /* (8) Assert valid frame signal to begin sending commands to
609 * AC97 codec */
610 cs4281_wr(sc,
611 CS4281PCI_ACCTL,
612 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_ESYN);
613
614 /* (9) Wait for codec calibration */
615 for(i = 0 ; i < 1000; i++) {
616 DELAY(10000);
617 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
618 if ((v & 0x0f) == 0x0f) {
619 break;
620 }
621 }
622 if (i == 1000) {
623 device_printf(sc->dev, "codec failed to calibrate\n");
624 return -1;
625 }
626
627 /* (10) Set AC97 timing */
628 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);
629
630 /* (11) Wait for valid data to arrive */
631 if (cs4281_waitset(sc,
632 CS4281PCI_ACISV,
633 CS4281PCI_ACISV_ISV(3) | CS4281PCI_ACISV_ISV(4),
634 10000) == 0) {
635 device_printf(sc->dev, "cs4281 never got valid data\n");
636 return -1;
637 }
638
639 /* (12) Start digital data transfer of audio data to codec */
640 cs4281_wr(sc,
641 CS4281PCI_ACOSV,
642 CS4281PCI_ACOSV_SLV(3) | CS4281PCI_ACOSV_SLV(4));
643
644 /* Set Master and headphone to max */
645 cs4281_wrcd(0, sc, AC97_MIX_PHONES, 0);
646 cs4281_wrcd(0, sc, AC97_MIX_MASTER, 0);
647
648 /* Power on the DAC */
649 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfdff;
650 cs4281_wrcd(0, sc, AC97_REG_POWER, v);
651
652 /* Wait until DAC state ready */
653 for(i = 0; i < 320; i++) {
654 DELAY(100);
655 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
656 if (v & 0x02) break;
657 }
658
659 /* Power on the ADC */
660 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfeff;
661 cs4281_wrcd(0, sc, AC97_REG_POWER, v);
662
663 /* Wait until ADC state ready */
664 for(i = 0; i < 320; i++) {
665 DELAY(100);
666 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
667 if (v & 0x01) break;
668 }
669
670 /* FIFO configuration (driver is DMA orientated, implicit FIFO) */
671 /* Play FIFO */
672
673 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_PLAY_SLOT) |
674 CS4281PCI_FCR_LS(CS4281PCI_LPCM_PLAY_SLOT) |
675 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)|
676 CS4281PCI_FCR_OF(0);
677 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v);
678
679 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v | CS4281PCI_FCR_FEN);
680
681 /* Record FIFO */
682 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_REC_SLOT) |
683 CS4281PCI_FCR_LS(CS4281PCI_LPCM_REC_SLOT) |
684 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)|
685 CS4281PCI_FCR_OF(CS4281_FIFO_SIZE + 1);
686 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_PSH);
687 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_FEN);
688
689 /* Match AC97 slots to FIFOs */
690 v = CS4281PCI_SRCSA_PLSS(CS4281PCI_LPCM_PLAY_SLOT) |
691 CS4281PCI_SRCSA_PRSS(CS4281PCI_RPCM_PLAY_SLOT) |
692 CS4281PCI_SRCSA_CLSS(CS4281PCI_LPCM_REC_SLOT) |
693 CS4281PCI_SRCSA_CRSS(CS4281PCI_RPCM_REC_SLOT);
694 cs4281_wr(sc, CS4281PCI_SRCSA, v);
695
696 /* Set Auto-Initialize and set directions */
697 cs4281_wr(sc,
698 CS4281PCI_DMR(CS4281_DMA_PLAY),
699 CS4281PCI_DMR_DMA |
700 CS4281PCI_DMR_AUTO |
701 CS4281PCI_DMR_TR_PLAY);
702 cs4281_wr(sc,
703 CS4281PCI_DMR(CS4281_DMA_REC),
704 CS4281PCI_DMR_DMA |
705 CS4281PCI_DMR_AUTO |
706 CS4281PCI_DMR_TR_REC);
707
708 /* Enable half and empty buffer interrupts keeping DMA paused */
709 cs4281_wr(sc,
710 CS4281PCI_DCR(CS4281_DMA_PLAY),
711 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK);
712 cs4281_wr(sc,
713 CS4281PCI_DCR(CS4281_DMA_REC),
714 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK);
715
716 /* Enable Interrupts */
717 cs4281_clr4(sc,
718 CS4281PCI_HIMR,
719 CS4281PCI_HIMR_DMAI |
720 CS4281PCI_HIMR_DMA(CS4281_DMA_PLAY) |
721 CS4281PCI_HIMR_DMA(CS4281_DMA_REC));
722
723 /* Set playback volume */
724 cs4281_wr(sc, CS4281PCI_PPLVC, 7);
725 cs4281_wr(sc, CS4281PCI_PPRVC, 7);
726
727 return 0;
728}
729
730/* -------------------------------------------------------------------- */
731/* Probe and attach the card */
732
733static int
734cs4281_pci_probe(device_t dev)
735{
736 char *s = NULL;
737
738 switch (pci_get_devid(dev)) {
739 case CS4281_PCI_ID:
740 s = "Crystal Semiconductor CS4281";
741 break;
742 }
743
744 if (s)
745 device_set_desc(dev, s);
746 return s ? 0 : ENXIO;
747}
748
749static int
750cs4281_pci_attach(device_t dev)
751{
752 struct sc_info *sc;
753 struct ac97_info *codec = NULL;
754 u_int32_t data;
755 char status[SND_STATUSLEN];
756
757 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) {
758 device_printf(dev, "cannot allocate softc\n");
759 return ENXIO;
760 }
761
762 bzero(sc, sizeof(*sc));
763 sc->dev = dev;
764 sc->type = pci_get_devid(dev);
765
766 data = pci_read_config(dev, PCIR_COMMAND, 2);
767 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
768 pci_write_config(dev, PCIR_COMMAND, data, 2);
769
770 data = pci_read_config(dev, PCIR_COMMAND, 2);
771
772#if __FreeBSD_version > 500000
773 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
774 /* Reset the power state. */
775 device_printf(dev, "chip is in D%d power mode "
776 "-- setting to D0\n", pci_get_powerstate(dev));
777
778 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
779 }
780#endif
781 sc->regid = PCIR_MAPS;
782 sc->regtype = SYS_RES_MEMORY;
783 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
784 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE);
785 if (!sc->reg) {
786 sc->regtype = SYS_RES_IOPORT;
787 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
788 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE);
789 if (!sc->reg) {
790 device_printf(dev, "unable to allocate register space\n");
791 goto bad;
792 }
793 }
794 sc->st = rman_get_bustag(sc->reg);
795 sc->sh = rman_get_bushandle(sc->reg);
796
797 sc->memid = PCIR_MAPS + 4;
798 sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->memid, 0,
799 ~0, CS4281PCI_BA1_SIZE, RF_ACTIVE);
800 if (sc->mem == NULL) {
801 device_printf(dev, "unable to allocate fifo space\n");
802 goto bad;
803 }
804
805 sc->irqid = 0;
806 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid,
807 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
808 if (!sc->irq) {
809 device_printf(dev, "unable to allocate interrupt\n");
810 goto bad;
811 }
812
| 441cs4281chan_getcaps(kobj_t obj, void *data)
442{
443 return &cs4281_caps;
444}
445
446static kobj_method_t cs4281chan_methods[] = {
447 KOBJMETHOD(channel_init, cs4281chan_init),
448 KOBJMETHOD(channel_setformat, cs4281chan_setformat),
449 KOBJMETHOD(channel_setspeed, cs4281chan_setspeed),
450 KOBJMETHOD(channel_setblocksize, cs4281chan_setblocksize),
451 KOBJMETHOD(channel_trigger, cs4281chan_trigger),
452 KOBJMETHOD(channel_getptr, cs4281chan_getptr),
453 KOBJMETHOD(channel_getcaps, cs4281chan_getcaps),
454 { 0, 0 }
455};
456CHANNEL_DECLARE(cs4281chan);
457
458/* -------------------------------------------------------------------- */
459/* ADC/DAC control */
460
461/* adcdac_go enables/disable DMA channel, returns non-zero if DMA was
462 * active before call */
463
464static u_int32_t
465adcdac_go(struct sc_chinfo *ch, u_int32_t go)
466{
467 struct sc_info *sc = ch->parent;
468 u_int32_t going;
469
470 going = !(cs4281_rd(sc, CS4281PCI_DCR(ch->dma_chan)) & CS4281PCI_DCR_MSK);
471
472 if (go)
473 cs4281_clr4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK);
474 else
475 cs4281_set4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK);
476
477 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI);
478
479 return going;
480}
481
482static void
483adcdac_prog(struct sc_chinfo *ch)
484{
485 struct sc_info *sc = ch->parent;
486 u_int32_t go;
487
488 if (!ch->dma_setup) {
489 go = adcdac_go(ch, 0);
490 cs4281_wr(sc, CS4281PCI_DBA(ch->dma_chan),
491 vtophys(sndbuf_getbuf(ch->buffer)));
492 cs4281_wr(sc, CS4281PCI_DBC(ch->dma_chan),
493 sndbuf_getsize(ch->buffer) / ch->bps - 1);
494 ch->dma_setup = 1;
495 adcdac_go(ch, go);
496 }
497}
498
499/* -------------------------------------------------------------------- */
500/* The interrupt handler */
501
502static void
503cs4281_intr(void *p)
504{
505 struct sc_info *sc = (struct sc_info *)p;
506 u_int32_t hisr;
507
508 hisr = cs4281_rd(sc, CS4281PCI_HISR);
509
510 if (hisr == 0) return;
511
512 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_PLAY)) {
513 chn_intr(sc->pch.channel);
514 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_PLAY)); /* Clear interrupt */
515 }
516
517 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_REC)) {
518 chn_intr(sc->rch.channel);
519 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_REC)); /* Clear interrupt */
520 }
521
522 /* Signal End-of-Interrupt */
523 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI);
524}
525
526/* -------------------------------------------------------------------- */
527/* power management related */
528
529static int
530cs4281_power(struct sc_info *sc, int state)
531{
532
533 switch (state) {
534 case 0:
535 /* Permit r/w access to all BA0 registers */
536 cs4281_wr(sc, CS4281PCI_CWPR, CS4281PCI_CWPR_MAGIC);
537 /* Power on */
538 cs4281_clr4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN);
539 break;
540 case 3:
541 /* Power off card and codec */
542 cs4281_set4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN);
543 cs4281_clr4(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN);
544 break;
545 }
546
547 DEB(printf("cs4281_power %d -> %d\n", sc->power, state));
548 sc->power = state;
549
550 return 0;
551}
552
553static int
554cs4281_init(struct sc_info *sc)
555{
556 u_int32_t i, v;
557
558 /* (0) Blast clock register and serial port */
559 cs4281_wr(sc, CS4281PCI_CLKCR1, 0);
560 cs4281_wr(sc, CS4281PCI_SERMC, 0);
561
562 /* (1) Make ESYN 0 to turn sync pulse on AC97 link */
563 cs4281_wr(sc, CS4281PCI_ACCTL, 0);
564 DELAY(50);
565
566 /* (2) Effect Reset */
567 cs4281_wr(sc, CS4281PCI_SPMC, 0);
568 DELAY(100);
569 cs4281_wr(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN);
570 /* Wait 50ms for ABITCLK to become stable */
571 DELAY(50000);
572
573 /* (3) Enable Sound System Clocks */
574 cs4281_wr(sc, CS4281PCI_CLKCR1, CS4281PCI_CLKCR1_DLLP);
575 DELAY(50000); /* Wait for PLL to stabilize */
576 cs4281_wr(sc, CS4281PCI_CLKCR1,
577 CS4281PCI_CLKCR1_DLLP | CS4281PCI_CLKCR1_SWCE);
578
579 /* (4) Power Up - this combination is essential. */
580 cs4281_set4(sc, CS4281PCI_SSPM,
581 CS4281PCI_SSPM_ACLEN | CS4281PCI_SSPM_PSRCEN |
582 CS4281PCI_SSPM_CSRCEN | CS4281PCI_SSPM_MIXEN);
583
584 /* (5) Wait for clock stabilization */
585 if (cs4281_waitset(sc,
586 CS4281PCI_CLKCR1,
587 CS4281PCI_CLKCR1_DLLRDY,
588 250) == 0) {
589 device_printf(sc->dev, "Clock stabilization failed\n");
590 return -1;
591 }
592
593 /* (6) Enable ASYNC generation. */
594 cs4281_wr(sc, CS4281PCI_ACCTL,CS4281PCI_ACCTL_ESYN);
595
596 /* Wait to allow AC97 to start generating clock bit */
597 DELAY(50000);
598
599 /* Set AC97 timing */
600 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);
601
602 /* (7) Wait for AC97 ready signal */
603 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_CRDY, 250) == 0) {
604 device_printf(sc->dev, "codec did not avail\n");
605 return -1;
606 }
607
608 /* (8) Assert valid frame signal to begin sending commands to
609 * AC97 codec */
610 cs4281_wr(sc,
611 CS4281PCI_ACCTL,
612 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_ESYN);
613
614 /* (9) Wait for codec calibration */
615 for(i = 0 ; i < 1000; i++) {
616 DELAY(10000);
617 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
618 if ((v & 0x0f) == 0x0f) {
619 break;
620 }
621 }
622 if (i == 1000) {
623 device_printf(sc->dev, "codec failed to calibrate\n");
624 return -1;
625 }
626
627 /* (10) Set AC97 timing */
628 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);
629
630 /* (11) Wait for valid data to arrive */
631 if (cs4281_waitset(sc,
632 CS4281PCI_ACISV,
633 CS4281PCI_ACISV_ISV(3) | CS4281PCI_ACISV_ISV(4),
634 10000) == 0) {
635 device_printf(sc->dev, "cs4281 never got valid data\n");
636 return -1;
637 }
638
639 /* (12) Start digital data transfer of audio data to codec */
640 cs4281_wr(sc,
641 CS4281PCI_ACOSV,
642 CS4281PCI_ACOSV_SLV(3) | CS4281PCI_ACOSV_SLV(4));
643
644 /* Set Master and headphone to max */
645 cs4281_wrcd(0, sc, AC97_MIX_PHONES, 0);
646 cs4281_wrcd(0, sc, AC97_MIX_MASTER, 0);
647
648 /* Power on the DAC */
649 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfdff;
650 cs4281_wrcd(0, sc, AC97_REG_POWER, v);
651
652 /* Wait until DAC state ready */
653 for(i = 0; i < 320; i++) {
654 DELAY(100);
655 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
656 if (v & 0x02) break;
657 }
658
659 /* Power on the ADC */
660 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfeff;
661 cs4281_wrcd(0, sc, AC97_REG_POWER, v);
662
663 /* Wait until ADC state ready */
664 for(i = 0; i < 320; i++) {
665 DELAY(100);
666 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
667 if (v & 0x01) break;
668 }
669
670 /* FIFO configuration (driver is DMA orientated, implicit FIFO) */
671 /* Play FIFO */
672
673 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_PLAY_SLOT) |
674 CS4281PCI_FCR_LS(CS4281PCI_LPCM_PLAY_SLOT) |
675 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)|
676 CS4281PCI_FCR_OF(0);
677 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v);
678
679 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v | CS4281PCI_FCR_FEN);
680
681 /* Record FIFO */
682 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_REC_SLOT) |
683 CS4281PCI_FCR_LS(CS4281PCI_LPCM_REC_SLOT) |
684 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)|
685 CS4281PCI_FCR_OF(CS4281_FIFO_SIZE + 1);
686 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_PSH);
687 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_FEN);
688
689 /* Match AC97 slots to FIFOs */
690 v = CS4281PCI_SRCSA_PLSS(CS4281PCI_LPCM_PLAY_SLOT) |
691 CS4281PCI_SRCSA_PRSS(CS4281PCI_RPCM_PLAY_SLOT) |
692 CS4281PCI_SRCSA_CLSS(CS4281PCI_LPCM_REC_SLOT) |
693 CS4281PCI_SRCSA_CRSS(CS4281PCI_RPCM_REC_SLOT);
694 cs4281_wr(sc, CS4281PCI_SRCSA, v);
695
696 /* Set Auto-Initialize and set directions */
697 cs4281_wr(sc,
698 CS4281PCI_DMR(CS4281_DMA_PLAY),
699 CS4281PCI_DMR_DMA |
700 CS4281PCI_DMR_AUTO |
701 CS4281PCI_DMR_TR_PLAY);
702 cs4281_wr(sc,
703 CS4281PCI_DMR(CS4281_DMA_REC),
704 CS4281PCI_DMR_DMA |
705 CS4281PCI_DMR_AUTO |
706 CS4281PCI_DMR_TR_REC);
707
708 /* Enable half and empty buffer interrupts keeping DMA paused */
709 cs4281_wr(sc,
710 CS4281PCI_DCR(CS4281_DMA_PLAY),
711 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK);
712 cs4281_wr(sc,
713 CS4281PCI_DCR(CS4281_DMA_REC),
714 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK);
715
716 /* Enable Interrupts */
717 cs4281_clr4(sc,
718 CS4281PCI_HIMR,
719 CS4281PCI_HIMR_DMAI |
720 CS4281PCI_HIMR_DMA(CS4281_DMA_PLAY) |
721 CS4281PCI_HIMR_DMA(CS4281_DMA_REC));
722
723 /* Set playback volume */
724 cs4281_wr(sc, CS4281PCI_PPLVC, 7);
725 cs4281_wr(sc, CS4281PCI_PPRVC, 7);
726
727 return 0;
728}
729
730/* -------------------------------------------------------------------- */
731/* Probe and attach the card */
732
733static int
734cs4281_pci_probe(device_t dev)
735{
736 char *s = NULL;
737
738 switch (pci_get_devid(dev)) {
739 case CS4281_PCI_ID:
740 s = "Crystal Semiconductor CS4281";
741 break;
742 }
743
744 if (s)
745 device_set_desc(dev, s);
746 return s ? 0 : ENXIO;
747}
748
749static int
750cs4281_pci_attach(device_t dev)
751{
752 struct sc_info *sc;
753 struct ac97_info *codec = NULL;
754 u_int32_t data;
755 char status[SND_STATUSLEN];
756
757 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) {
758 device_printf(dev, "cannot allocate softc\n");
759 return ENXIO;
760 }
761
762 bzero(sc, sizeof(*sc));
763 sc->dev = dev;
764 sc->type = pci_get_devid(dev);
765
766 data = pci_read_config(dev, PCIR_COMMAND, 2);
767 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
768 pci_write_config(dev, PCIR_COMMAND, data, 2);
769
770 data = pci_read_config(dev, PCIR_COMMAND, 2);
771
772#if __FreeBSD_version > 500000
773 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
774 /* Reset the power state. */
775 device_printf(dev, "chip is in D%d power mode "
776 "-- setting to D0\n", pci_get_powerstate(dev));
777
778 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
779 }
780#endif
781 sc->regid = PCIR_MAPS;
782 sc->regtype = SYS_RES_MEMORY;
783 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
784 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE);
785 if (!sc->reg) {
786 sc->regtype = SYS_RES_IOPORT;
787 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
788 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE);
789 if (!sc->reg) {
790 device_printf(dev, "unable to allocate register space\n");
791 goto bad;
792 }
793 }
794 sc->st = rman_get_bustag(sc->reg);
795 sc->sh = rman_get_bushandle(sc->reg);
796
797 sc->memid = PCIR_MAPS + 4;
798 sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->memid, 0,
799 ~0, CS4281PCI_BA1_SIZE, RF_ACTIVE);
800 if (sc->mem == NULL) {
801 device_printf(dev, "unable to allocate fifo space\n");
802 goto bad;
803 }
804
805 sc->irqid = 0;
806 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid,
807 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
808 if (!sc->irq) {
809 device_printf(dev, "unable to allocate interrupt\n");
810 goto bad;
811 }
812
|
813 if (bus_setup_intr(dev, sc->irq, INTR_TYPE_TTY, cs4281_intr, sc, &sc->ih)) {
| 813 if (snd_setup_intr(dev, sc->irq, 0, cs4281_intr, sc, &sc->ih)) {
|
814 device_printf(dev, "unable to setup interrupt\n");
815 goto bad;
816 }
817
818 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
819 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
820 /*highaddr*/BUS_SPACE_MAXADDR,
821 /*filter*/NULL, /*filterarg*/NULL,
822 /*maxsize*/CS4281_BUFFER_SIZE, /*nsegments*/1,
823 /*maxsegz*/0x3ffff,
824 /*flags*/0, &sc->parent_dmat) != 0) {
825 device_printf(dev, "unable to create dma tag\n");
826 goto bad;
827 }
828
829 /* power up */
830 cs4281_power(sc, 0);
831
832 /* init chip */
833 if (cs4281_init(sc) == -1) {
834 device_printf(dev, "unable to initialize the card\n");
835 goto bad;
836 }
837
838 /* create/init mixer */
839 codec = AC97_CREATE(dev, sc, cs4281_ac97);
840 if (codec == NULL)
841 goto bad;
842
843 mixer_init(dev, ac97_getmixerclass(), codec);
844
845 if (pcm_register(dev, sc, 1, 1))
846 goto bad;
847
848 pcm_addchan(dev, PCMDIR_PLAY, &cs4281chan_class, sc);
849 pcm_addchan(dev, PCMDIR_REC, &cs4281chan_class, sc);
850
851 snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld",
852 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory",
853 rman_get_start(sc->reg), rman_get_start(sc->irq));
854 pcm_setstatus(dev, status);
855
856 return 0;
857
858 bad:
859 if (codec)
860 ac97_destroy(codec);
861 if (sc->reg)
862 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
863 if (sc->mem)
864 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
865 if (sc->ih)
866 bus_teardown_intr(dev, sc->irq, sc->ih);
867 if (sc->irq)
868 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
869 if (sc->parent_dmat)
870 bus_dma_tag_destroy(sc->parent_dmat);
871 free(sc, M_DEVBUF);
872
873 return ENXIO;
874}
875
876static int
877cs4281_pci_detach(device_t dev)
878{
879 int r;
880 struct sc_info *sc;
881
882 r = pcm_unregister(dev);
883 if (r)
884 return r;
885
886 sc = pcm_getdevinfo(dev);
887
888 /* power off */
889 cs4281_power(sc, 3);
890
891 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
892 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
893 bus_teardown_intr(dev, sc->irq, sc->ih);
894 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
895 bus_dma_tag_destroy(sc->parent_dmat);
896 free(sc, M_DEVBUF);
897
898 return 0;
899}
900
901static int
902cs4281_pci_suspend(device_t dev)
903{
904 struct sc_info *sc;
905
906 sc = pcm_getdevinfo(dev);
907
908 sc->rch.dma_active = adcdac_go(&sc->rch, 0);
909 sc->pch.dma_active = adcdac_go(&sc->pch, 0);
910
911 cs4281_power(sc, 3);
912
913 return 0;
914}
915
916static int
917cs4281_pci_resume(device_t dev)
918{
919 struct sc_info *sc;
920
921 sc = pcm_getdevinfo(dev);
922
923 /* power up */
924 cs4281_power(sc, 0);
925
926 /* initialize chip */
927 if (cs4281_init(sc) == -1) {
928 device_printf(dev, "unable to reinitialize the card\n");
929 return ENXIO;
930 }
931
932 /* restore mixer state */
933 if (mixer_reinit(dev) == -1) {
934 device_printf(dev, "unable to reinitialize the mixer\n");
935 return ENXIO;
936 }
937
938 /* restore chip state */
939 cs4281chan_setspeed(NULL, &sc->rch, sc->rch.spd);
940 cs4281chan_setblocksize(NULL, &sc->rch, sc->rch.blksz);
941 cs4281chan_setformat(NULL, &sc->rch, sc->rch.fmt);
942 adcdac_go(&sc->rch, sc->rch.dma_active);
943
944 cs4281chan_setspeed(NULL, &sc->pch, sc->pch.spd);
945 cs4281chan_setblocksize(NULL, &sc->pch, sc->pch.blksz);
946 cs4281chan_setformat(NULL, &sc->pch, sc->pch.fmt);
947 adcdac_go(&sc->pch, sc->pch.dma_active);
948
949 return 0;
950}
951
952static device_method_t cs4281_methods[] = {
953 /* Device interface */
954 DEVMETHOD(device_probe, cs4281_pci_probe),
955 DEVMETHOD(device_attach, cs4281_pci_attach),
956 DEVMETHOD(device_detach, cs4281_pci_detach),
957 DEVMETHOD(device_suspend, cs4281_pci_suspend),
958 DEVMETHOD(device_resume, cs4281_pci_resume),
959 { 0, 0 }
960};
961
962static driver_t cs4281_driver = {
963 "pcm",
964 cs4281_methods,
| 814 device_printf(dev, "unable to setup interrupt\n");
815 goto bad;
816 }
817
818 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
819 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
820 /*highaddr*/BUS_SPACE_MAXADDR,
821 /*filter*/NULL, /*filterarg*/NULL,
822 /*maxsize*/CS4281_BUFFER_SIZE, /*nsegments*/1,
823 /*maxsegz*/0x3ffff,
824 /*flags*/0, &sc->parent_dmat) != 0) {
825 device_printf(dev, "unable to create dma tag\n");
826 goto bad;
827 }
828
829 /* power up */
830 cs4281_power(sc, 0);
831
832 /* init chip */
833 if (cs4281_init(sc) == -1) {
834 device_printf(dev, "unable to initialize the card\n");
835 goto bad;
836 }
837
838 /* create/init mixer */
839 codec = AC97_CREATE(dev, sc, cs4281_ac97);
840 if (codec == NULL)
841 goto bad;
842
843 mixer_init(dev, ac97_getmixerclass(), codec);
844
845 if (pcm_register(dev, sc, 1, 1))
846 goto bad;
847
848 pcm_addchan(dev, PCMDIR_PLAY, &cs4281chan_class, sc);
849 pcm_addchan(dev, PCMDIR_REC, &cs4281chan_class, sc);
850
851 snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld",
852 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory",
853 rman_get_start(sc->reg), rman_get_start(sc->irq));
854 pcm_setstatus(dev, status);
855
856 return 0;
857
858 bad:
859 if (codec)
860 ac97_destroy(codec);
861 if (sc->reg)
862 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
863 if (sc->mem)
864 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
865 if (sc->ih)
866 bus_teardown_intr(dev, sc->irq, sc->ih);
867 if (sc->irq)
868 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
869 if (sc->parent_dmat)
870 bus_dma_tag_destroy(sc->parent_dmat);
871 free(sc, M_DEVBUF);
872
873 return ENXIO;
874}
875
876static int
877cs4281_pci_detach(device_t dev)
878{
879 int r;
880 struct sc_info *sc;
881
882 r = pcm_unregister(dev);
883 if (r)
884 return r;
885
886 sc = pcm_getdevinfo(dev);
887
888 /* power off */
889 cs4281_power(sc, 3);
890
891 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
892 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
893 bus_teardown_intr(dev, sc->irq, sc->ih);
894 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
895 bus_dma_tag_destroy(sc->parent_dmat);
896 free(sc, M_DEVBUF);
897
898 return 0;
899}
900
901static int
902cs4281_pci_suspend(device_t dev)
903{
904 struct sc_info *sc;
905
906 sc = pcm_getdevinfo(dev);
907
908 sc->rch.dma_active = adcdac_go(&sc->rch, 0);
909 sc->pch.dma_active = adcdac_go(&sc->pch, 0);
910
911 cs4281_power(sc, 3);
912
913 return 0;
914}
915
916static int
917cs4281_pci_resume(device_t dev)
918{
919 struct sc_info *sc;
920
921 sc = pcm_getdevinfo(dev);
922
923 /* power up */
924 cs4281_power(sc, 0);
925
926 /* initialize chip */
927 if (cs4281_init(sc) == -1) {
928 device_printf(dev, "unable to reinitialize the card\n");
929 return ENXIO;
930 }
931
932 /* restore mixer state */
933 if (mixer_reinit(dev) == -1) {
934 device_printf(dev, "unable to reinitialize the mixer\n");
935 return ENXIO;
936 }
937
938 /* restore chip state */
939 cs4281chan_setspeed(NULL, &sc->rch, sc->rch.spd);
940 cs4281chan_setblocksize(NULL, &sc->rch, sc->rch.blksz);
941 cs4281chan_setformat(NULL, &sc->rch, sc->rch.fmt);
942 adcdac_go(&sc->rch, sc->rch.dma_active);
943
944 cs4281chan_setspeed(NULL, &sc->pch, sc->pch.spd);
945 cs4281chan_setblocksize(NULL, &sc->pch, sc->pch.blksz);
946 cs4281chan_setformat(NULL, &sc->pch, sc->pch.fmt);
947 adcdac_go(&sc->pch, sc->pch.dma_active);
948
949 return 0;
950}
951
952static device_method_t cs4281_methods[] = {
953 /* Device interface */
954 DEVMETHOD(device_probe, cs4281_pci_probe),
955 DEVMETHOD(device_attach, cs4281_pci_attach),
956 DEVMETHOD(device_detach, cs4281_pci_detach),
957 DEVMETHOD(device_suspend, cs4281_pci_suspend),
958 DEVMETHOD(device_resume, cs4281_pci_resume),
959 { 0, 0 }
960};
961
962static driver_t cs4281_driver = {
963 "pcm",
964 cs4281_methods,
|
965 sizeof(snddev_info),
| 965 sizeof(struct snddev_info),
|
966};
967
968static devclass_t pcm_devclass;
969
970DRIVER_MODULE(snd_cs4281, pci, cs4281_driver, pcm_devclass, 0, 0);
971MODULE_DEPEND(snd_cs4281, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
972MODULE_VERSION(snd_cs4281, 1);
| 966};
967
968static devclass_t pcm_devclass;
969
970DRIVER_MODULE(snd_cs4281, pci, cs4281_driver, pcm_devclass, 0, 0);
971MODULE_DEPEND(snd_cs4281, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
972MODULE_VERSION(snd_cs4281, 1);
|