1/*
2 * file: mss.h
3 *
4 * (C) 1997 Luigi Rizzo (luigi@iet.unipi.it)
5 *
6 * This file contains information and macro definitions for
7 * AD1848-compatible devices, used in the MSS/WSS compatible boards.
8 *
9 */
10
11/*
12 *
13
14The codec part of the board is seen as a set of 4 registers mapped
15at the base address for the board (default 0x534). Note that some
16(early) boards implemented 4 additional registers 4 location before
17(usually 0x530) to store configuration information. This is a source
18of confusion in that one never knows what address to specify. The
19(current) convention is to use the old address (0x530) in the kernel
20configuration file and consider MSS registers start four location
21ahead.
22
23 *
24 */
25
26/*
27 * The four visible registers of the MSS :
28 *
29 */
30
31#define MSS_INDEX (0 + 4)
32#define MSS_IDXBUSY 0x80 /* readonly, set when busy */
33#define MSS_MCE 0x40 /* the MCE bit. */
34 /*
35 * the MCE bit must be set whenever the current mode of the
36 * codec is changed; this in particular is true for the
37 * Data Format (I8, I28) and Interface Config(I9) registers.
38 * Only exception are CEN and PEN which can be changed on the fly.
39 * The DAC output is muted when MCE is set.
40 */
41#define MSS_TRD 0x20 /* Transfer request disable */
42 /*
43 * When TRD is set, DMA transfers cease when the INT bit in
44 * the MSS status reg is set. Must be cleared for automode
45 * DMA, set otherwise.
46 */
47#define MSS_IDXMASK 0x1f /* mask for indirect address */
48
49#define MSS_IDATA (1 + 4)
50 /*
51 * data to be transferred to the indirect register addressed
52 * by index addr. During init and sw. powerdown, cannot be
53 * written to, and is always read as 0x80 (consistent with the
54 * busy flag).
55 */
56
57#define MSS_STATUS (2 + 4)
58
59#define IS_CUL 0x80 /* capture upper/lower */
60#define IS_CLR 0x40 /* capture left/right */
61#define IS_CRDY 0x20 /* capture ready for programmed i/o */
62#define IS_SER 0x10 /* sample error (overrun/underrun) */
63#define IS_PUL 0x08 /* playback upper/lower */
64#define IS_PLR 0x04 /* playback left/right */
65#define IS_PRDY 0x02 /* playback ready for programmed i/o */
66#define IS_INT 0x01 /* int status (1 = active) */
67 /*
68 * IS_INT is clreared by any write to the status register.
69 */
70#if 0
71#define io_Polled_IO(d) ((d)->io_base+3+4)
72 /*
73 * this register is used in case of polled i/o
74 */
75#endif
76
77/*
78 * The MSS has a set of 16 (or 32 depending on the model) indirect
79 * registers accessible through the data port by specifying the
80 * appropriate address in the address register.
81 *
82 * The 16 low registers are uniformly handled in AD1848/CS4248 compatible
83 * mode (often called MODE1). For the upper 16 registers there are
84 * some differences among different products, mainly Crystal uses them
85 * differently from OPTi.
86 *
87 */
88
89/*
90 * volume registers
91 */
92
93#define I6_MUTE 0x80
94
95/*
96 * register I9 -- interface configuration.
97 */
98
99#define I9_PEN 0x01 /* playback enable */
100#define I9_CEN 0x02 /* capture enable */
101
102/*
103 * values used in bd_flags
104 */
105#define BD_F_MCE_BIT 0x0001
106#define BD_F_IRQ_OK 0x0002
107#define BD_F_TMR_RUN 0x0004
108#define BD_F_MSS_OFFSET 0x0008 /* offset mss writes by -4 */
109#define BD_F_DUPLEX 0x0010
110
111/* AD1816 register macros */
112
113#define AD1816_ALE 0 /* indirect reg access */
114#define AD1816_INT 1 /* interupt status */
115#define AD1816_LOW 2 /* indirect low byte */
116#define AD1816_HIGH 3 /* indirect high byte */
117
118#if 0
119#define ad1816_pioD(d) ((d)->io_base+4) /* PIO debug */
120#define ad1816_pios(d) ((d)->io_base+5) /* PIO status */
121#define ad1816_piod(d) ((d)->io_base+6) /* PIO data */
122#endif
123
124/* values for playback/capture config:
125 bits: 0 enable/disable
126 1 pio/dma
127 2 stereo/mono
128 3 companded/linearPCM
129 4-5 format : 00 8bit linear (uncomp)
130 00 8bit mulaw (comp)
131 01 16bit le (uncomp)
132 01 8bit alaw (comp)
133 11 16bit be (uncomp)
134*/
135
136#define AD1816_PLAY 8 /* playback config */
137#define AD1816_CAPT 9 /* capture config */
138
139#define AD1816_BUSY 0x80 /* chip is busy */
140#define AD1816_ALEMASK 0x3F /* mask for indirect adr. */
141
142#if 0
143#define AD1816_INTRSI 0x01 /* sb intr */
144#define AD1816_INTRGI 0x02 /* game intr */
145#define AD1816_INTRRI 0x04 /* ring intr */
146#define AD1816_INTRDI 0x08 /* dsp intr */
147#define AD1816_INTRVI 0x10 /* vol intr */
148#define AD1816_INTRTI 0x20 /* timer intr */
149#endif
150
151#define AD1816_INTRCI 0x40 /* capture intr */
152#define AD1816_INTRPI 0x80 /* playback intr */
153/* PIO stuff is not supplied here */
154/* playback / capture config */
155#define AD1816_ENABLE 0x01 /* enable pl/cp */
156#define AD1816_PIO 0x02 /* use pio */
157#define AD1816_STEREO 0x04
158#define AD1816_COMP 0x08 /* data is companded */
159#define AD1816_U8 0x00 /* 8 bit linear pcm */
160#define AD1816_MULAW 0x08 /* 8 bit mulaw */
161#define AD1816_ALAW 0x18 /* 8 bit alaw */
162#define AD1816_S16LE 0x10 /* 16 bit linear little endian */
163#define AD1816_S16BE 0x30 /* 16 bit linear big endian */
164#define AD1816_FORMASK 0x38 /* format mask */
165
166
167
168
169/*
170 * sound/ad1848_mixer.h
171 *
172 * Definitions for the mixer of AD1848 and compatible codecs.
173 *
174 * Copyright by Hannu Savolainen 1994
175 *
176 * Redistribution and use in source and binary forms, with or without
177 * modification, are permitted provided that the following conditions are
178 * met: 1. Redistributions of source code must retain the above copyright
179 * notice, this list of conditions and the following disclaimer. 2.
180 * Redistributions in binary form must reproduce the above copyright notice,
181 * this list of conditions and the following disclaimer in the documentation
182 * and/or other materials provided with the distribution.
183 *
184 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
185 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
186 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
187 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
188 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
189 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
190 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
191 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
192 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
193 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
194 * SUCH DAMAGE.
195 */
196/*
197 * The AD1848 codec has generic input lines called Line, Aux1 and Aux2.
198 * Soundcard manufacturers have connected actual inputs (CD, synth, line,
199 * etc) to these inputs in different order. Therefore it's difficult
200 * to assign mixer channels to to these inputs correctly. The following
201 * contains two alternative mappings. The first one is for GUS MAX and
202 * the second is just a generic one (line1, line2 and line3).
203 * (Actually this is not a mapping but rather some kind of interleaving
204 * solution).
205 */
206
207#define MSS_REC_DEVICES \
208 (SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD|SOUND_MASK_IMIX)
209
210
211/*
212 * Table of mixer registers. There is a default table for the
213 * AD1848/CS423x clones, and one for the OPTI931. As more MSS
214 * clones come out, there ought to be more tables.
215 *
216 * Fields in the table are : polarity, register, offset, bits
217 *
218 * The channel numbering used by individual soundcards is not fixed.
219 * Some cards have assigned different meanings for the AUX1, AUX2
220 * and LINE inputs. Some have different features...
221 *
222 * Following there is a macro ...MIXER_DEVICES which is a bitmap
223 * of all non-zero fields in the table.
224 * MODE1_MIXER_DEVICES is the basic mixer of the 1848 in mode 1
225 * registers I0..I15)
226 *
227 */
228
229mixer_ent mix_devices[32][2] = {
230MIX_NONE(SOUND_MIXER_VOLUME),
231MIX_NONE(SOUND_MIXER_BASS),
232MIX_NONE(SOUND_MIXER_TREBLE),
233MIX_ENT(SOUND_MIXER_SYNTH, 2, 1, 0, 5, 3, 1, 0, 5),
234MIX_ENT(SOUND_MIXER_PCM, 6, 1, 0, 6, 7, 1, 0, 6),
235MIX_ENT(SOUND_MIXER_SPEAKER, 26, 1, 0, 4, 0, 0, 0, 0),
236MIX_ENT(SOUND_MIXER_LINE, 18, 1, 0, 5, 19, 1, 0, 5),
237MIX_ENT(SOUND_MIXER_MIC, 0, 0, 5, 1, 1, 0, 5, 1),
238MIX_ENT(SOUND_MIXER_CD, 4, 1, 0, 5, 5, 1, 0, 5),
239MIX_ENT(SOUND_MIXER_IMIX, 13, 1, 2, 6, 0, 0, 0, 0),
240MIX_NONE(SOUND_MIXER_ALTPCM),
241MIX_NONE(SOUND_MIXER_RECLEV),
242MIX_ENT(SOUND_MIXER_IGAIN, 0, 0, 0, 4, 1, 0, 0, 4),
243MIX_NONE(SOUND_MIXER_OGAIN),
244MIX_NONE(SOUND_MIXER_LINE1),
245MIX_NONE(SOUND_MIXER_LINE2),
246MIX_NONE(SOUND_MIXER_LINE3),
247};
248
249#define MODE2_MIXER_DEVICES \
250 (SOUND_MASK_SYNTH | SOUND_MASK_PCM | SOUND_MASK_SPEAKER | \
251 SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | \
252 SOUND_MASK_IMIX | SOUND_MASK_IGAIN )
253
254#define MODE1_MIXER_DEVICES \
255 (SOUND_MASK_SYNTH | SOUND_MASK_PCM | SOUND_MASK_MIC | \
256 SOUND_MASK_CD | SOUND_MASK_IMIX | SOUND_MASK_IGAIN )
257
258
259/*
260 * entries for the opti931...
261 */
262
263mixer_ent opti931_devices[32][2] = { /* for the opti931 */
264MIX_ENT(SOUND_MIXER_VOLUME, 22, 1, 1, 5, 23, 1, 1, 5),
265MIX_NONE(SOUND_MIXER_BASS),
266MIX_NONE(SOUND_MIXER_TREBLE),
267MIX_ENT(SOUND_MIXER_SYNTH, 4, 1, 1, 4, 5, 1, 1, 4),
268MIX_ENT(SOUND_MIXER_PCM, 6, 1, 0, 5, 7, 1, 0, 5),
269MIX_NONE(SOUND_MIXER_SPEAKER),
270MIX_ENT(SOUND_MIXER_LINE, 18, 1, 1, 4, 19, 1, 1, 4),
271MIX_ENT(SOUND_MIXER_MIC, 0, 0, 5, 1, 1, 0, 5, 1),
272MIX_ENT(SOUND_MIXER_CD, 2, 1, 1, 4, 3, 1, 1, 4),
273MIX_NONE(SOUND_MIXER_IMIX),
274MIX_NONE(SOUND_MIXER_ALTPCM),
275MIX_NONE(SOUND_MIXER_RECLEV),
276MIX_ENT(SOUND_MIXER_IGAIN, 0, 0, 0, 4, 1, 0, 0, 4),
277MIX_NONE(SOUND_MIXER_OGAIN),
278MIX_ENT(SOUND_MIXER_LINE1, 16, 1, 1, 4, 17, 1, 1, 4),
279MIX_NONE(SOUND_MIXER_LINE2),
280MIX_NONE(SOUND_MIXER_LINE3),
281};
282
283#define OPTI931_MIXER_DEVICES \
284 (SOUND_MASK_VOLUME | SOUND_MASK_SYNTH | SOUND_MASK_PCM | \
285 SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | \
286 SOUND_MASK_IGAIN | SOUND_MASK_LINE1 )
287
288#define AD1816_REC_DEVICES \
289 (SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD)
290
291#define AD1816_MIXER_DEVICES \
292 (SOUND_MASK_VOLUME | SOUND_MASK_PCM | SOUND_MASK_SYNTH | \
293 SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | SOUND_MASK_IGAIN)
294
295/*-
296 * Copyright (c) 1999 Doug Rabson
297 * All rights reserved.
298 *
299 * Redistribution and use in source and binary forms, with or without
300 * modification, are permitted provided that the following conditions
301 * are met:
302 * 1. Redistributions of source code must retain the above copyright
303 * notice, this list of conditions and the following disclaimer.
304 * 2. Redistributions in binary form must reproduce the above copyright
305 * notice, this list of conditions and the following disclaimer in the
306 * documentation and/or other materials provided with the distribution.
307 *
308 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
309 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
310 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
311 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
312 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
313 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
314 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
315 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
316 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
317 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
318 * SUCH DAMAGE.
319 *
| 1/*
2 * file: mss.h
3 *
4 * (C) 1997 Luigi Rizzo (luigi@iet.unipi.it)
5 *
6 * This file contains information and macro definitions for
7 * AD1848-compatible devices, used in the MSS/WSS compatible boards.
8 *
9 */
10
11/*
12 *
13
14The codec part of the board is seen as a set of 4 registers mapped
15at the base address for the board (default 0x534). Note that some
16(early) boards implemented 4 additional registers 4 location before
17(usually 0x530) to store configuration information. This is a source
18of confusion in that one never knows what address to specify. The
19(current) convention is to use the old address (0x530) in the kernel
20configuration file and consider MSS registers start four location
21ahead.
22
23 *
24 */
25
26/*
27 * The four visible registers of the MSS :
28 *
29 */
30
31#define MSS_INDEX (0 + 4)
32#define MSS_IDXBUSY 0x80 /* readonly, set when busy */
33#define MSS_MCE 0x40 /* the MCE bit. */
34 /*
35 * the MCE bit must be set whenever the current mode of the
36 * codec is changed; this in particular is true for the
37 * Data Format (I8, I28) and Interface Config(I9) registers.
38 * Only exception are CEN and PEN which can be changed on the fly.
39 * The DAC output is muted when MCE is set.
40 */
41#define MSS_TRD 0x20 /* Transfer request disable */
42 /*
43 * When TRD is set, DMA transfers cease when the INT bit in
44 * the MSS status reg is set. Must be cleared for automode
45 * DMA, set otherwise.
46 */
47#define MSS_IDXMASK 0x1f /* mask for indirect address */
48
49#define MSS_IDATA (1 + 4)
50 /*
51 * data to be transferred to the indirect register addressed
52 * by index addr. During init and sw. powerdown, cannot be
53 * written to, and is always read as 0x80 (consistent with the
54 * busy flag).
55 */
56
57#define MSS_STATUS (2 + 4)
58
59#define IS_CUL 0x80 /* capture upper/lower */
60#define IS_CLR 0x40 /* capture left/right */
61#define IS_CRDY 0x20 /* capture ready for programmed i/o */
62#define IS_SER 0x10 /* sample error (overrun/underrun) */
63#define IS_PUL 0x08 /* playback upper/lower */
64#define IS_PLR 0x04 /* playback left/right */
65#define IS_PRDY 0x02 /* playback ready for programmed i/o */
66#define IS_INT 0x01 /* int status (1 = active) */
67 /*
68 * IS_INT is clreared by any write to the status register.
69 */
70#if 0
71#define io_Polled_IO(d) ((d)->io_base+3+4)
72 /*
73 * this register is used in case of polled i/o
74 */
75#endif
76
77/*
78 * The MSS has a set of 16 (or 32 depending on the model) indirect
79 * registers accessible through the data port by specifying the
80 * appropriate address in the address register.
81 *
82 * The 16 low registers are uniformly handled in AD1848/CS4248 compatible
83 * mode (often called MODE1). For the upper 16 registers there are
84 * some differences among different products, mainly Crystal uses them
85 * differently from OPTi.
86 *
87 */
88
89/*
90 * volume registers
91 */
92
93#define I6_MUTE 0x80
94
95/*
96 * register I9 -- interface configuration.
97 */
98
99#define I9_PEN 0x01 /* playback enable */
100#define I9_CEN 0x02 /* capture enable */
101
102/*
103 * values used in bd_flags
104 */
105#define BD_F_MCE_BIT 0x0001
106#define BD_F_IRQ_OK 0x0002
107#define BD_F_TMR_RUN 0x0004
108#define BD_F_MSS_OFFSET 0x0008 /* offset mss writes by -4 */
109#define BD_F_DUPLEX 0x0010
110
111/* AD1816 register macros */
112
113#define AD1816_ALE 0 /* indirect reg access */
114#define AD1816_INT 1 /* interupt status */
115#define AD1816_LOW 2 /* indirect low byte */
116#define AD1816_HIGH 3 /* indirect high byte */
117
118#if 0
119#define ad1816_pioD(d) ((d)->io_base+4) /* PIO debug */
120#define ad1816_pios(d) ((d)->io_base+5) /* PIO status */
121#define ad1816_piod(d) ((d)->io_base+6) /* PIO data */
122#endif
123
124/* values for playback/capture config:
125 bits: 0 enable/disable
126 1 pio/dma
127 2 stereo/mono
128 3 companded/linearPCM
129 4-5 format : 00 8bit linear (uncomp)
130 00 8bit mulaw (comp)
131 01 16bit le (uncomp)
132 01 8bit alaw (comp)
133 11 16bit be (uncomp)
134*/
135
136#define AD1816_PLAY 8 /* playback config */
137#define AD1816_CAPT 9 /* capture config */
138
139#define AD1816_BUSY 0x80 /* chip is busy */
140#define AD1816_ALEMASK 0x3F /* mask for indirect adr. */
141
142#if 0
143#define AD1816_INTRSI 0x01 /* sb intr */
144#define AD1816_INTRGI 0x02 /* game intr */
145#define AD1816_INTRRI 0x04 /* ring intr */
146#define AD1816_INTRDI 0x08 /* dsp intr */
147#define AD1816_INTRVI 0x10 /* vol intr */
148#define AD1816_INTRTI 0x20 /* timer intr */
149#endif
150
151#define AD1816_INTRCI 0x40 /* capture intr */
152#define AD1816_INTRPI 0x80 /* playback intr */
153/* PIO stuff is not supplied here */
154/* playback / capture config */
155#define AD1816_ENABLE 0x01 /* enable pl/cp */
156#define AD1816_PIO 0x02 /* use pio */
157#define AD1816_STEREO 0x04
158#define AD1816_COMP 0x08 /* data is companded */
159#define AD1816_U8 0x00 /* 8 bit linear pcm */
160#define AD1816_MULAW 0x08 /* 8 bit mulaw */
161#define AD1816_ALAW 0x18 /* 8 bit alaw */
162#define AD1816_S16LE 0x10 /* 16 bit linear little endian */
163#define AD1816_S16BE 0x30 /* 16 bit linear big endian */
164#define AD1816_FORMASK 0x38 /* format mask */
165
166
167
168
169/*
170 * sound/ad1848_mixer.h
171 *
172 * Definitions for the mixer of AD1848 and compatible codecs.
173 *
174 * Copyright by Hannu Savolainen 1994
175 *
176 * Redistribution and use in source and binary forms, with or without
177 * modification, are permitted provided that the following conditions are
178 * met: 1. Redistributions of source code must retain the above copyright
179 * notice, this list of conditions and the following disclaimer. 2.
180 * Redistributions in binary form must reproduce the above copyright notice,
181 * this list of conditions and the following disclaimer in the documentation
182 * and/or other materials provided with the distribution.
183 *
184 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
185 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
186 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
187 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
188 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
189 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
190 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
191 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
192 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
193 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
194 * SUCH DAMAGE.
195 */
196/*
197 * The AD1848 codec has generic input lines called Line, Aux1 and Aux2.
198 * Soundcard manufacturers have connected actual inputs (CD, synth, line,
199 * etc) to these inputs in different order. Therefore it's difficult
200 * to assign mixer channels to to these inputs correctly. The following
201 * contains two alternative mappings. The first one is for GUS MAX and
202 * the second is just a generic one (line1, line2 and line3).
203 * (Actually this is not a mapping but rather some kind of interleaving
204 * solution).
205 */
206
207#define MSS_REC_DEVICES \
208 (SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD|SOUND_MASK_IMIX)
209
210
211/*
212 * Table of mixer registers. There is a default table for the
213 * AD1848/CS423x clones, and one for the OPTI931. As more MSS
214 * clones come out, there ought to be more tables.
215 *
216 * Fields in the table are : polarity, register, offset, bits
217 *
218 * The channel numbering used by individual soundcards is not fixed.
219 * Some cards have assigned different meanings for the AUX1, AUX2
220 * and LINE inputs. Some have different features...
221 *
222 * Following there is a macro ...MIXER_DEVICES which is a bitmap
223 * of all non-zero fields in the table.
224 * MODE1_MIXER_DEVICES is the basic mixer of the 1848 in mode 1
225 * registers I0..I15)
226 *
227 */
228
229mixer_ent mix_devices[32][2] = {
230MIX_NONE(SOUND_MIXER_VOLUME),
231MIX_NONE(SOUND_MIXER_BASS),
232MIX_NONE(SOUND_MIXER_TREBLE),
233MIX_ENT(SOUND_MIXER_SYNTH, 2, 1, 0, 5, 3, 1, 0, 5),
234MIX_ENT(SOUND_MIXER_PCM, 6, 1, 0, 6, 7, 1, 0, 6),
235MIX_ENT(SOUND_MIXER_SPEAKER, 26, 1, 0, 4, 0, 0, 0, 0),
236MIX_ENT(SOUND_MIXER_LINE, 18, 1, 0, 5, 19, 1, 0, 5),
237MIX_ENT(SOUND_MIXER_MIC, 0, 0, 5, 1, 1, 0, 5, 1),
238MIX_ENT(SOUND_MIXER_CD, 4, 1, 0, 5, 5, 1, 0, 5),
239MIX_ENT(SOUND_MIXER_IMIX, 13, 1, 2, 6, 0, 0, 0, 0),
240MIX_NONE(SOUND_MIXER_ALTPCM),
241MIX_NONE(SOUND_MIXER_RECLEV),
242MIX_ENT(SOUND_MIXER_IGAIN, 0, 0, 0, 4, 1, 0, 0, 4),
243MIX_NONE(SOUND_MIXER_OGAIN),
244MIX_NONE(SOUND_MIXER_LINE1),
245MIX_NONE(SOUND_MIXER_LINE2),
246MIX_NONE(SOUND_MIXER_LINE3),
247};
248
249#define MODE2_MIXER_DEVICES \
250 (SOUND_MASK_SYNTH | SOUND_MASK_PCM | SOUND_MASK_SPEAKER | \
251 SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | \
252 SOUND_MASK_IMIX | SOUND_MASK_IGAIN )
253
254#define MODE1_MIXER_DEVICES \
255 (SOUND_MASK_SYNTH | SOUND_MASK_PCM | SOUND_MASK_MIC | \
256 SOUND_MASK_CD | SOUND_MASK_IMIX | SOUND_MASK_IGAIN )
257
258
259/*
260 * entries for the opti931...
261 */
262
263mixer_ent opti931_devices[32][2] = { /* for the opti931 */
264MIX_ENT(SOUND_MIXER_VOLUME, 22, 1, 1, 5, 23, 1, 1, 5),
265MIX_NONE(SOUND_MIXER_BASS),
266MIX_NONE(SOUND_MIXER_TREBLE),
267MIX_ENT(SOUND_MIXER_SYNTH, 4, 1, 1, 4, 5, 1, 1, 4),
268MIX_ENT(SOUND_MIXER_PCM, 6, 1, 0, 5, 7, 1, 0, 5),
269MIX_NONE(SOUND_MIXER_SPEAKER),
270MIX_ENT(SOUND_MIXER_LINE, 18, 1, 1, 4, 19, 1, 1, 4),
271MIX_ENT(SOUND_MIXER_MIC, 0, 0, 5, 1, 1, 0, 5, 1),
272MIX_ENT(SOUND_MIXER_CD, 2, 1, 1, 4, 3, 1, 1, 4),
273MIX_NONE(SOUND_MIXER_IMIX),
274MIX_NONE(SOUND_MIXER_ALTPCM),
275MIX_NONE(SOUND_MIXER_RECLEV),
276MIX_ENT(SOUND_MIXER_IGAIN, 0, 0, 0, 4, 1, 0, 0, 4),
277MIX_NONE(SOUND_MIXER_OGAIN),
278MIX_ENT(SOUND_MIXER_LINE1, 16, 1, 1, 4, 17, 1, 1, 4),
279MIX_NONE(SOUND_MIXER_LINE2),
280MIX_NONE(SOUND_MIXER_LINE3),
281};
282
283#define OPTI931_MIXER_DEVICES \
284 (SOUND_MASK_VOLUME | SOUND_MASK_SYNTH | SOUND_MASK_PCM | \
285 SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | \
286 SOUND_MASK_IGAIN | SOUND_MASK_LINE1 )
287
288#define AD1816_REC_DEVICES \
289 (SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD)
290
291#define AD1816_MIXER_DEVICES \
292 (SOUND_MASK_VOLUME | SOUND_MASK_PCM | SOUND_MASK_SYNTH | \
293 SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | SOUND_MASK_IGAIN)
294
295/*-
296 * Copyright (c) 1999 Doug Rabson
297 * All rights reserved.
298 *
299 * Redistribution and use in source and binary forms, with or without
300 * modification, are permitted provided that the following conditions
301 * are met:
302 * 1. Redistributions of source code must retain the above copyright
303 * notice, this list of conditions and the following disclaimer.
304 * 2. Redistributions in binary form must reproduce the above copyright
305 * notice, this list of conditions and the following disclaimer in the
306 * documentation and/or other materials provided with the distribution.
307 *
308 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
309 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
310 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
311 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
312 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
313 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
314 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
315 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
316 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
317 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
318 * SUCH DAMAGE.
319 *
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