1/*
2 * Copyright (c) 1997, 1998, 1999, 2000
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
|
33 */
34
35/*
36 * SysKonnect PCI vendor ID
37 */
38#define SK_VENDORID 0x1148
39
40/*
41 * SK-NET gigabit ethernet device ID
42 */
43#define SK_DEVICEID_GE 0x4300
44
45/*
46 * GEnesis registers. The GEnesis chip has a 256-byte I/O window
47 * but internally it has a 16K register space. This 16K space is
48 * divided into 128-byte blocks. The first 128 bytes of the I/O
49 * window represent the first block, which is permanently mapped
50 * at the start of the window. The other 127 blocks can be mapped
51 * to the second 128 bytes of the I/O window by setting the desired
52 * block value in the RAP register in block 0. Not all of the 127
53 * blocks are actually used. Most registers are 32 bits wide, but
54 * there are a few 16-bit and 8-bit ones as well.
55 */
56
57
58/* Start of remappable register window. */
59#define SK_WIN_BASE 0x0080
60
61/* Size of a window */
62#define SK_WIN_LEN 0x80
63
64#define SK_WIN_MASK 0x3F80
65#define SK_REG_MASK 0x7F
66
67/* Compute the window of a given register (for the RAP register) */
68#define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN)
69
70/* Compute the relative offset of a register within the window */
71#define SK_REG(reg) ((reg) & SK_REG_MASK)
72
73#define SK_PORT_A 0
74#define SK_PORT_B 1
75
76/*
77 * Compute offset of port-specific register. Since there are two
78 * ports, there are two of some GEnesis modules (e.g. two sets of
79 * DMA queues, two sets of FIFO control registers, etc...). Normally,
80 * the block for port 0 is at offset 0x0 and the block for port 1 is
81 * at offset 0x80 (i.e. the next page over). However for the transmit
82 * BMUs and RAMbuffers, there are two blocks for each port: one for
83 * the sync transmit queue and one for the async queue (which we don't
84 * use). However instead of ordering them like this:
85 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2
86 * SysKonnect has instead ordered them like this:
87 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2
88 * This means that when referencing the TX BMU and RAMbuffer registers,
89 * we have to double the block offset (0x80 * 2) in order to reach the
90 * second queue. This prevents us from using the same formula
91 * (sk_port * 0x80) to compute the offsets for all of the port-specific
92 * blocks: we need an extra offset for the BMU and RAMbuffer registers.
93 * The simplest thing is to provide an extra argument to these macros:
94 * the 'skip' parameter. The 'skip' value is the number of extra pages
95 * for skip when computing the port0/port1 offsets. For most registers,
96 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1.
97 */
98#define SK_IF_READ_4(sc_if, skip, reg) \
99 sk_win_read_4(sc_if->sk_softc, reg + \
100 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
101#define SK_IF_READ_2(sc_if, skip, reg) \
102 sk_win_read_2(sc_if->sk_softc, reg + \
103 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
104#define SK_IF_READ_1(sc_if, skip, reg) \
105 sk_win_read_1(sc_if->sk_softc, reg + \
106 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
107
108#define SK_IF_WRITE_4(sc_if, skip, reg, val) \
109 sk_win_write_4(sc_if->sk_softc, \
110 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
111#define SK_IF_WRITE_2(sc_if, skip, reg, val) \
112 sk_win_write_2(sc_if->sk_softc, \
113 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
114#define SK_IF_WRITE_1(sc_if, skip, reg, val) \
115 sk_win_write_1(sc_if->sk_softc, \
116 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
117
118/* Block 0 registers, permanently mapped at iobase. */
119#define SK_RAP 0x0000
120#define SK_CSR 0x0004
121#define SK_LED 0x0006
122#define SK_ISR 0x0008 /* interrupt source */
123#define SK_IMR 0x000C /* interrupt mask */
124#define SK_IESR 0x0010 /* interrupt hardware error source */
125#define SK_IEMR 0x0014 /* interrupt hardware error mask */
126#define SK_ISSR 0x0018 /* special interrupt source */
127#define SK_XM_IMR0 0x0020
128#define SK_XM_ISR0 0x0028
129#define SK_XM_PHYADDR0 0x0030
130#define SK_XM_PHYDATA0 0x0034
131#define SK_XM_IMR1 0x0040
132#define SK_XM_ISR1 0x0048
133#define SK_XM_PHYADDR1 0x0050
134#define SK_XM_PHYDATA1 0x0054
135#define SK_BMU_RX_CSR0 0x0060
136#define SK_BMU_RX_CSR1 0x0064
137#define SK_BMU_TXS_CSR0 0x0068
138#define SK_BMU_TXA_CSR0 0x006C
139#define SK_BMU_TXS_CSR1 0x0070
140#define SK_BMU_TXA_CSR1 0x0074
141
142/* SK_CSR register */
143#define SK_CSR_SW_RESET 0x0001
144#define SK_CSR_SW_UNRESET 0x0002
145#define SK_CSR_MASTER_RESET 0x0004
146#define SK_CSR_MASTER_UNRESET 0x0008
147#define SK_CSR_MASTER_STOP 0x0010
148#define SK_CSR_MASTER_DONE 0x0020
149#define SK_CSR_SW_IRQ_CLEAR 0x0040
150#define SK_CSR_SW_IRQ_SET 0x0080
151#define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */
152#define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 Mhz, = 33 */
153
154/* SK_LED register */
155#define SK_LED_GREEN_OFF 0x01
156#define SK_LED_GREEN_ON 0x02
157
158/* SK_ISR register */
159#define SK_ISR_TX2_AS_CHECK 0x00000001
160#define SK_ISR_TX2_AS_EOF 0x00000002
161#define SK_ISR_TX2_AS_EOB 0x00000004
162#define SK_ISR_TX2_S_CHECK 0x00000008
163#define SK_ISR_TX2_S_EOF 0x00000010
164#define SK_ISR_TX2_S_EOB 0x00000020
165#define SK_ISR_TX1_AS_CHECK 0x00000040
166#define SK_ISR_TX1_AS_EOF 0x00000080
167#define SK_ISR_TX1_AS_EOB 0x00000100
168#define SK_ISR_TX1_S_CHECK 0x00000200
169#define SK_ISR_TX1_S_EOF 0x00000400
170#define SK_ISR_TX1_S_EOB 0x00000800
171#define SK_ISR_RX2_CHECK 0x00001000
172#define SK_ISR_RX2_EOF 0x00002000
173#define SK_ISR_RX2_EOB 0x00004000
174#define SK_ISR_RX1_CHECK 0x00008000
175#define SK_ISR_RX1_EOF 0x00010000
176#define SK_ISR_RX1_EOB 0x00020000
177#define SK_ISR_LINK2_OFLOW 0x00040000
178#define SK_ISR_MAC2 0x00080000
179#define SK_ISR_LINK1_OFLOW 0x00100000
180#define SK_ISR_MAC1 0x00200000
181#define SK_ISR_TIMER 0x00400000
182#define SK_ISR_EXTERNAL_REG 0x00800000
183#define SK_ISR_SW 0x01000000
184#define SK_ISR_I2C_RDY 0x02000000
185#define SK_ISR_TX2_TIMEO 0x04000000
186#define SK_ISR_TX1_TIMEO 0x08000000
187#define SK_ISR_RX2_TIMEO 0x10000000
188#define SK_ISR_RX1_TIMEO 0x20000000
189#define SK_ISR_RSVD 0x40000000
190#define SK_ISR_HWERR 0x80000000
191
192/* SK_IMR register */
193#define SK_IMR_TX2_AS_CHECK 0x00000001
194#define SK_IMR_TX2_AS_EOF 0x00000002
195#define SK_IMR_TX2_AS_EOB 0x00000004
196#define SK_IMR_TX2_S_CHECK 0x00000008
197#define SK_IMR_TX2_S_EOF 0x00000010
198#define SK_IMR_TX2_S_EOB 0x00000020
199#define SK_IMR_TX1_AS_CHECK 0x00000040
200#define SK_IMR_TX1_AS_EOF 0x00000080
201#define SK_IMR_TX1_AS_EOB 0x00000100
202#define SK_IMR_TX1_S_CHECK 0x00000200
203#define SK_IMR_TX1_S_EOF 0x00000400
204#define SK_IMR_TX1_S_EOB 0x00000800
205#define SK_IMR_RX2_CHECK 0x00001000
206#define SK_IMR_RX2_EOF 0x00002000
207#define SK_IMR_RX2_EOB 0x00004000
208#define SK_IMR_RX1_CHECK 0x00008000
209#define SK_IMR_RX1_EOF 0x00010000
210#define SK_IMR_RX1_EOB 0x00020000
211#define SK_IMR_LINK2_OFLOW 0x00040000
212#define SK_IMR_MAC2 0x00080000
213#define SK_IMR_LINK1_OFLOW 0x00100000
214#define SK_IMR_MAC1 0x00200000
215#define SK_IMR_TIMER 0x00400000
216#define SK_IMR_EXTERNAL_REG 0x00800000
217#define SK_IMR_SW 0x01000000
218#define SK_IMR_I2C_RDY 0x02000000
219#define SK_IMR_TX2_TIMEO 0x04000000
220#define SK_IMR_TX1_TIMEO 0x08000000
221#define SK_IMR_RX2_TIMEO 0x10000000
222#define SK_IMR_RX1_TIMEO 0x20000000
223#define SK_IMR_RSVD 0x40000000
224#define SK_IMR_HWERR 0x80000000
225
226#define SK_INTRS1 \
227 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1)
228
229#define SK_INTRS2 \
230 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2)
231
232/* SK_IESR register */
233#define SK_IESR_PAR_RX2 0x00000001
234#define SK_IESR_PAR_RX1 0x00000002
235#define SK_IESR_PAR_MAC2 0x00000004
236#define SK_IESR_PAR_MAC1 0x00000008
237#define SK_IESR_PAR_WR_RAM 0x00000010
238#define SK_IESR_PAR_RD_RAM 0x00000020
239#define SK_IESR_NO_TSTAMP_MAC2 0x00000040
240#define SK_IESR_NO_TSTAMO_MAC1 0x00000080
241#define SK_IESR_NO_STS_MAC2 0x00000100
242#define SK_IESR_NO_STS_MAC1 0x00000200
243#define SK_IESR_IRQ_STS 0x00000400
244#define SK_IESR_MASTERERR 0x00000800
245
246/* SK_IEMR register */
247#define SK_IEMR_PAR_RX2 0x00000001
248#define SK_IEMR_PAR_RX1 0x00000002
249#define SK_IEMR_PAR_MAC2 0x00000004
250#define SK_IEMR_PAR_MAC1 0x00000008
251#define SK_IEMR_PAR_WR_RAM 0x00000010
252#define SK_IEMR_PAR_RD_RAM 0x00000020
253#define SK_IEMR_NO_TSTAMP_MAC2 0x00000040
254#define SK_IEMR_NO_TSTAMO_MAC1 0x00000080
255#define SK_IEMR_NO_STS_MAC2 0x00000100
256#define SK_IEMR_NO_STS_MAC1 0x00000200
257#define SK_IEMR_IRQ_STS 0x00000400
258#define SK_IEMR_MASTERERR 0x00000800
259
260/* Block 2 */
261#define SK_MAC0_0 0x0100
262#define SK_MAC0_1 0x0104
263#define SK_MAC1_0 0x0108
264#define SK_MAC1_1 0x010C
265#define SK_MAC2_0 0x0110
266#define SK_MAC2_1 0x0114
267#define SK_CONNTYPE 0x0118
268#define SK_PMDTYPE 0x0119
269#define SK_CONFIG 0x011A
270#define SK_CHIPVER 0x011B
271#define SK_EPROM0 0x011C
272#define SK_EPROM1 0x011D
273#define SK_EPROM2 0x011E
274#define SK_EPROM3 0x011F
275#define SK_EP_ADDR 0x0120
276#define SK_EP_DATA 0x0124
277#define SK_EP_LOADCTL 0x0128
278#define SK_EP_LOADTST 0x0129
279#define SK_TIMERINIT 0x0130
280#define SK_TIMER 0x0134
281#define SK_TIMERCTL 0x0138
282#define SK_TIMERTST 0x0139
283#define SK_IMTIMERINIT 0x0140
284#define SK_IMTIMER 0x0144
285#define SK_IMTIMERCTL 0x0148
286#define SK_IMTIMERTST 0x0149
287#define SK_IMMR 0x014C
288#define SK_IHWEMR 0x0150
289#define SK_TESTCTL1 0x0158
290#define SK_TESTCTL2 0x0159
291#define SK_GPIO 0x015C
292#define SK_I2CHWCTL 0x0160
293#define SK_I2CHWDATA 0x0164
294#define SK_I2CHWIRQ 0x0168
295#define SK_I2CSW 0x016C
296#define SK_BLNKINIT 0x0170
297#define SK_BLNKCOUNT 0x0174
298#define SK_BLNKCTL 0x0178
299#define SK_BLNKSTS 0x0179
300#define SK_BLNKTST 0x017A
301
302#define SK_IMCTL_STOP 0x02
303#define SK_IMCTL_START 0x04
304
305#define SK_IMTIMER_TICKS 54
306#define SK_IM_USECS(x) ((x) * SK_IMTIMER_TICKS)
307
308/*
309 * The SK_EPROM0 register contains a byte that describes the
310 * amount of SRAM mounted on the NIC. The value also tells if
311 * the chips are 64K or 128K. This affects the RAMbuffer address
312 * offset that we need to use.
313 */
314#define SK_RAMSIZE_512K_64 0x1
315#define SK_RAMSIZE_1024K_128 0x2
316#define SK_RAMSIZE_1024K_64 0x3
317#define SK_RAMSIZE_2048K_128 0x4
318
319#define SK_RBOFF_0 0x0
320#define SK_RBOFF_80000 0x80000
321
322/*
323 * SK_EEPROM1 contains the PHY type, which may be XMAC for
324 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom
325 * PHY.
326 */
327#define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */
328#define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */
329#define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */
330#define SK_PHYTYPE_NAT 3 /* National DP83891 */
331
332/*
333 * PHY addresses.
334 */
335#define SK_PHYADDR_XMAC 0x0
336#define SK_PHYADDR_BCOM 0x1
337#define SK_PHYADDR_LONE 0x3
338#define SK_PHYADDR_NAT 0x0
339
340#define SK_CONFIG_SINGLEMAC 0x01
341#define SK_CONFIG_DIS_DSL_CLK 0x02
342
343#define SK_PMD_1000BASELX 0x4C
344#define SK_PMD_1000BASESX 0x53
345#define SK_PMD_1000BASECX 0x43
346#define SK_PMD_1000BASETX 0x54
347
348/* GPIO bits */
349#define SK_GPIO_DAT0 0x00000001
350#define SK_GPIO_DAT1 0x00000002
351#define SK_GPIO_DAT2 0x00000004
352#define SK_GPIO_DAT3 0x00000008
353#define SK_GPIO_DAT4 0x00000010
354#define SK_GPIO_DAT5 0x00000020
355#define SK_GPIO_DAT6 0x00000040
356#define SK_GPIO_DAT7 0x00000080
357#define SK_GPIO_DAT8 0x00000100
358#define SK_GPIO_DAT9 0x00000200
359#define SK_GPIO_DIR0 0x00010000
360#define SK_GPIO_DIR1 0x00020000
361#define SK_GPIO_DIR2 0x00040000
362#define SK_GPIO_DIR3 0x00080000
363#define SK_GPIO_DIR4 0x00100000
364#define SK_GPIO_DIR5 0x00200000
365#define SK_GPIO_DIR6 0x00400000
366#define SK_GPIO_DIR7 0x00800000
367#define SK_GPIO_DIR8 0x01000000
368#define SK_GPIO_DIR9 0x02000000
369
370/* Block 3 Ram interface and MAC arbiter registers */
371#define SK_RAMADDR 0x0180
372#define SK_RAMDATA0 0x0184
373#define SK_RAMDATA1 0x0188
374#define SK_TO0 0x0190
375#define SK_TO1 0x0191
376#define SK_TO2 0x0192
377#define SK_TO3 0x0193
378#define SK_TO4 0x0194
379#define SK_TO5 0x0195
380#define SK_TO6 0x0196
381#define SK_TO7 0x0197
382#define SK_TO8 0x0198
383#define SK_TO9 0x0199
384#define SK_TO10 0x019A
385#define SK_TO11 0x019B
386#define SK_RITIMEO_TMR 0x019C
387#define SK_RAMCTL 0x01A0
388#define SK_RITIMER_TST 0x01A2
389
390#define SK_RAMCTL_RESET 0x0001
391#define SK_RAMCTL_UNRESET 0x0002
392#define SK_RAMCTL_CLR_IRQ_WPAR 0x0100
393#define SK_RAMCTL_CLR_IRQ_RPAR 0x0200
394
395/* Mac arbiter registers */
396#define SK_MINIT_RX1 0x01B0
397#define SK_MINIT_RX2 0x01B1
398#define SK_MINIT_TX1 0x01B2
399#define SK_MINIT_TX2 0x01B3
400#define SK_MTIMEO_RX1 0x01B4
401#define SK_MTIMEO_RX2 0x01B5
402#define SK_MTIMEO_TX1 0x01B6
403#define SK_MTIEMO_TX2 0x01B7
404#define SK_MACARB_CTL 0x01B8
405#define SK_MTIMER_TST 0x01BA
406#define SK_RCINIT_RX1 0x01C0
407#define SK_RCINIT_RX2 0x01C1
408#define SK_RCINIT_TX1 0x01C2
409#define SK_RCINIT_TX2 0x01C3
410#define SK_RCTIMEO_RX1 0x01C4
411#define SK_RCTIMEO_RX2 0x01C5
412#define SK_RCTIMEO_TX1 0x01C6
413#define SK_RCTIMEO_TX2 0x01C7
414#define SK_RECOVERY_CTL 0x01C8
415#define SK_RCTIMER_TST 0x01CA
416
417/* Packet arbiter registers */
418#define SK_RXPA1_TINIT 0x01D0
419#define SK_RXPA2_TINIT 0x01D4
420#define SK_TXPA1_TINIT 0x01D8
421#define SK_TXPA2_TINIT 0x01DC
422#define SK_RXPA1_TIMEO 0x01E0
423#define SK_RXPA2_TIMEO 0x01E4
424#define SK_TXPA1_TIMEO 0x01E8
425#define SK_TXPA2_TIMEO 0x01EC
426#define SK_PKTARB_CTL 0x01F0
427#define SK_PKTATB_TST 0x01F2
428
429#define SK_PKTARB_TIMEOUT 0x2000
430
431#define SK_PKTARBCTL_RESET 0x0001
432#define SK_PKTARBCTL_UNRESET 0x0002
433#define SK_PKTARBCTL_RXTO1_OFF 0x0004
434#define SK_PKTARBCTL_RXTO1_ON 0x0008
435#define SK_PKTARBCTL_RXTO2_OFF 0x0010
436#define SK_PKTARBCTL_RXTO2_ON 0x0020
437#define SK_PKTARBCTL_TXTO1_OFF 0x0040
438#define SK_PKTARBCTL_TXTO1_ON 0x0080
439#define SK_PKTARBCTL_TXTO2_OFF 0x0100
440#define SK_PKTARBCTL_TXTO2_ON 0x0200
441#define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400
442#define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800
443#define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000
444#define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000
445
446#define SK_MINIT_XMAC_B2 54
447#define SK_MINIT_XMAC_C1 63
448
449#define SK_MACARBCTL_RESET 0x0001
450#define SK_MACARBCTL_UNRESET 0x0002
451#define SK_MACARBCTL_FASTOE_OFF 0x0004
452#define SK_MACARBCRL_FASTOE_ON 0x0008
453
454#define SK_RCINIT_XMAC_B2 54
455#define SK_RCINIT_XMAC_C1 0
456
457#define SK_RECOVERYCTL_RX1_OFF 0x0001
458#define SK_RECOVERYCTL_RX1_ON 0x0002
459#define SK_RECOVERYCTL_RX2_OFF 0x0004
460#define SK_RECOVERYCTL_RX2_ON 0x0008
461#define SK_RECOVERYCTL_TX1_OFF 0x0010
462#define SK_RECOVERYCTL_TX1_ON 0x0020
463#define SK_RECOVERYCTL_TX2_OFF 0x0040
464#define SK_RECOVERYCTL_TX2_ON 0x0080
465
466#define SK_RECOVERY_XMAC_B2 \
467 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \
468 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON)
469
470#define SK_RECOVERY_XMAC_C1 \
471 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \
472 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF)
473
474/* Block 4 -- TX Arbiter MAC 1 */
475#define SK_TXAR1_TIMERINIT 0x0200
476#define SK_TXAR1_TIMERVAL 0x0204
477#define SK_TXAR1_LIMITINIT 0x0208
478#define SK_TXAR1_LIMITCNT 0x020C
479#define SK_TXAR1_COUNTERCTL 0x0210
480#define SK_TXAR1_COUNTERTST 0x0212
481#define SK_TXAR1_COUNTERSTS 0x0212
482
483/* Block 5 -- TX Arbiter MAC 2 */
484#define SK_TXAR2_TIMERINIT 0x0280
485#define SK_TXAR2_TIMERVAL 0x0284
486#define SK_TXAR2_LIMITINIT 0x0288
487#define SK_TXAR2_LIMITCNT 0x028C
488#define SK_TXAR2_COUNTERCTL 0x0290
489#define SK_TXAR2_COUNTERTST 0x0291
490#define SK_TXAR2_COUNTERSTS 0x0292
491
492#define SK_TXARCTL_OFF 0x01
493#define SK_TXARCTL_ON 0x02
494#define SK_TXARCTL_RATECTL_OFF 0x04
495#define SK_TXARCTL_RATECTL_ON 0x08
496#define SK_TXARCTL_ALLOC_OFF 0x10
497#define SK_TXARCTL_ALLOC_ON 0x20
498#define SK_TXARCTL_FSYNC_OFF 0x40
499#define SK_TXARCTL_FSYNC_ON 0x80
500
501/* Block 6 -- External registers */
502#define SK_EXTREG_BASE 0x300
503#define SK_EXTREG_END 0x37C
504
505/* Block 7 -- PCI config registers */
506#define SK_PCI_BASE 0x0380
507#define SK_PCI_END 0x03FC
508
509/* Compute offset of mirrored PCI register */
510#define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE)
511
512/* Block 8 -- RX queue 1 */
513#define SK_RXQ1_BUFCNT 0x0400
514#define SK_RXQ1_BUFCTL 0x0402
515#define SK_RXQ1_NEXTDESC 0x0404
516#define SK_RXQ1_RXBUF_LO 0x0408
517#define SK_RXQ1_RXBUF_HI 0x040C
518#define SK_RXQ1_RXSTAT 0x0410
519#define SK_RXQ1_TIMESTAMP 0x0414
520#define SK_RXQ1_CSUM1 0x0418
521#define SK_RXQ1_CSUM2 0x041A
522#define SK_RXQ1_CSUM1_START 0x041C
523#define SK_RXQ1_CSUM2_START 0x041E
524#define SK_RXQ1_CURADDR_LO 0x0420
525#define SK_RXQ1_CURADDR_HI 0x0424
526#define SK_RXQ1_CURCNT_LO 0x0428
527#define SK_RXQ1_CURCNT_HI 0x042C
528#define SK_RXQ1_CURBYTES 0x0430
529#define SK_RXQ1_BMU_CSR 0x0434
530#define SK_RXQ1_WATERMARK 0x0438
531#define SK_RXQ1_FLAG 0x043A
532#define SK_RXQ1_TEST1 0x043C
533#define SK_RXQ1_TEST2 0x0440
534#define SK_RXQ1_TEST3 0x0444
535
536/* Block 9 -- RX queue 2 */
537#define SK_RXQ2_BUFCNT 0x0480
538#define SK_RXQ2_BUFCTL 0x0482
539#define SK_RXQ2_NEXTDESC 0x0484
540#define SK_RXQ2_RXBUF_LO 0x0488
541#define SK_RXQ2_RXBUF_HI 0x048C
542#define SK_RXQ2_RXSTAT 0x0490
543#define SK_RXQ2_TIMESTAMP 0x0494
544#define SK_RXQ2_CSUM1 0x0498
545#define SK_RXQ2_CSUM2 0x049A
546#define SK_RXQ2_CSUM1_START 0x049C
547#define SK_RXQ2_CSUM2_START 0x049E
548#define SK_RXQ2_CURADDR_LO 0x04A0
549#define SK_RXQ2_CURADDR_HI 0x04A4
550#define SK_RXQ2_CURCNT_LO 0x04A8
551#define SK_RXQ2_CURCNT_HI 0x04AC
552#define SK_RXQ2_CURBYTES 0x04B0
553#define SK_RXQ2_BMU_CSR 0x04B4
554#define SK_RXQ2_WATERMARK 0x04B8
555#define SK_RXQ2_FLAG 0x04BA
556#define SK_RXQ2_TEST1 0x04BC
557#define SK_RXQ2_TEST2 0x04C0
558#define SK_RXQ2_TEST3 0x04C4
559
560#define SK_RXBMU_CLR_IRQ_ERR 0x00000001
561#define SK_RXBMU_CLR_IRQ_EOF 0x00000002
562#define SK_RXBMU_CLR_IRQ_EOB 0x00000004
563#define SK_RXBMU_CLR_IRQ_PAR 0x00000008
564#define SK_RXBMU_RX_START 0x00000010
565#define SK_RXBMU_RX_STOP 0x00000020
566#define SK_RXBMU_POLL_OFF 0x00000040
567#define SK_RXBMU_POLL_ON 0x00000080
568#define SK_RXBMU_TRANSFER_SM_RESET 0x00000100
569#define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200
570#define SK_RXBMU_DESCWR_SM_RESET 0x00000400
571#define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800
572#define SK_RXBMU_DESCRD_SM_RESET 0x00001000
573#define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000
574#define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000
575#define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000
576#define SK_RXBMU_PFI_SM_RESET 0x00010000
577#define SK_RXBMU_PFI_SM_UNRESET 0x00020000
578#define SK_RXBMU_FIFO_RESET 0x00040000
579#define SK_RXBMU_FIFO_UNRESET 0x00080000
580#define SK_RXBMU_DESC_RESET 0x00100000
581#define SK_RXBMU_DESC_UNRESET 0x00200000
582#define SK_RXBMU_SUPERVISOR_IDLE 0x01000000
583
584#define SK_RXBMU_ONLINE \
585 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \
586 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \
587 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \
588 SK_RXBMU_DESC_UNRESET)
589
590#define SK_RXBMU_OFFLINE \
591 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \
592 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \
593 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \
594 SK_RXBMU_DESC_RESET)
595
596/* Block 12 -- TX sync queue 1 */
597#define SK_TXQS1_BUFCNT 0x0600
598#define SK_TXQS1_BUFCTL 0x0602
599#define SK_TXQS1_NEXTDESC 0x0604
600#define SK_TXQS1_RXBUF_LO 0x0608
601#define SK_TXQS1_RXBUF_HI 0x060C
602#define SK_TXQS1_RXSTAT 0x0610
603#define SK_TXQS1_CSUM_STARTVAL 0x0614
604#define SK_TXQS1_CSUM_STARTPOS 0x0618
605#define SK_TXQS1_CSUM_WRITEPOS 0x061A
606#define SK_TXQS1_CURADDR_LO 0x0620
607#define SK_TXQS1_CURADDR_HI 0x0624
608#define SK_TXQS1_CURCNT_LO 0x0628
609#define SK_TXQS1_CURCNT_HI 0x062C
610#define SK_TXQS1_CURBYTES 0x0630
611#define SK_TXQS1_BMU_CSR 0x0634
612#define SK_TXQS1_WATERMARK 0x0638
613#define SK_TXQS1_FLAG 0x063A
614#define SK_TXQS1_TEST1 0x063C
615#define SK_TXQS1_TEST2 0x0640
616#define SK_TXQS1_TEST3 0x0644
617
618/* Block 13 -- TX async queue 1 */
619#define SK_TXQA1_BUFCNT 0x0680
620#define SK_TXQA1_BUFCTL 0x0682
621#define SK_TXQA1_NEXTDESC 0x0684
622#define SK_TXQA1_RXBUF_LO 0x0688
623#define SK_TXQA1_RXBUF_HI 0x068C
624#define SK_TXQA1_RXSTAT 0x0690
625#define SK_TXQA1_CSUM_STARTVAL 0x0694
626#define SK_TXQA1_CSUM_STARTPOS 0x0698
627#define SK_TXQA1_CSUM_WRITEPOS 0x069A
628#define SK_TXQA1_CURADDR_LO 0x06A0
629#define SK_TXQA1_CURADDR_HI 0x06A4
630#define SK_TXQA1_CURCNT_LO 0x06A8
631#define SK_TXQA1_CURCNT_HI 0x06AC
632#define SK_TXQA1_CURBYTES 0x06B0
633#define SK_TXQA1_BMU_CSR 0x06B4
634#define SK_TXQA1_WATERMARK 0x06B8
635#define SK_TXQA1_FLAG 0x06BA
636#define SK_TXQA1_TEST1 0x06BC
637#define SK_TXQA1_TEST2 0x06C0
638#define SK_TXQA1_TEST3 0x06C4
639
640/* Block 14 -- TX sync queue 2 */
641#define SK_TXQS2_BUFCNT 0x0700
642#define SK_TXQS2_BUFCTL 0x0702
643#define SK_TXQS2_NEXTDESC 0x0704
644#define SK_TXQS2_RXBUF_LO 0x0708
645#define SK_TXQS2_RXBUF_HI 0x070C
646#define SK_TXQS2_RXSTAT 0x0710
647#define SK_TXQS2_CSUM_STARTVAL 0x0714
648#define SK_TXQS2_CSUM_STARTPOS 0x0718
649#define SK_TXQS2_CSUM_WRITEPOS 0x071A
650#define SK_TXQS2_CURADDR_LO 0x0720
651#define SK_TXQS2_CURADDR_HI 0x0724
652#define SK_TXQS2_CURCNT_LO 0x0728
653#define SK_TXQS2_CURCNT_HI 0x072C
654#define SK_TXQS2_CURBYTES 0x0730
655#define SK_TXQS2_BMU_CSR 0x0734
656#define SK_TXQS2_WATERMARK 0x0738
657#define SK_TXQS2_FLAG 0x073A
658#define SK_TXQS2_TEST1 0x073C
659#define SK_TXQS2_TEST2 0x0740
660#define SK_TXQS2_TEST3 0x0744
661
662/* Block 15 -- TX async queue 2 */
663#define SK_TXQA2_BUFCNT 0x0780
664#define SK_TXQA2_BUFCTL 0x0782
665#define SK_TXQA2_NEXTDESC 0x0784
666#define SK_TXQA2_RXBUF_LO 0x0788
667#define SK_TXQA2_RXBUF_HI 0x078C
668#define SK_TXQA2_RXSTAT 0x0790
669#define SK_TXQA2_CSUM_STARTVAL 0x0794
670#define SK_TXQA2_CSUM_STARTPOS 0x0798
671#define SK_TXQA2_CSUM_WRITEPOS 0x079A
672#define SK_TXQA2_CURADDR_LO 0x07A0
673#define SK_TXQA2_CURADDR_HI 0x07A4
674#define SK_TXQA2_CURCNT_LO 0x07A8
675#define SK_TXQA2_CURCNT_HI 0x07AC
676#define SK_TXQA2_CURBYTES 0x07B0
677#define SK_TXQA2_BMU_CSR 0x07B4
678#define SK_TXQA2_WATERMARK 0x07B8
679#define SK_TXQA2_FLAG 0x07BA
680#define SK_TXQA2_TEST1 0x07BC
681#define SK_TXQA2_TEST2 0x07C0
682#define SK_TXQA2_TEST3 0x07C4
683
684#define SK_TXBMU_CLR_IRQ_ERR 0x00000001
685#define SK_TXBMU_CLR_IRQ_EOF 0x00000002
686#define SK_TXBMU_CLR_IRQ_EOB 0x00000004
687#define SK_TXBMU_TX_START 0x00000010
688#define SK_TXBMU_TX_STOP 0x00000020
689#define SK_TXBMU_POLL_OFF 0x00000040
690#define SK_TXBMU_POLL_ON 0x00000080
691#define SK_TXBMU_TRANSFER_SM_RESET 0x00000100
692#define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200
693#define SK_TXBMU_DESCWR_SM_RESET 0x00000400
694#define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800
695#define SK_TXBMU_DESCRD_SM_RESET 0x00001000
696#define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000
697#define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000
698#define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000
699#define SK_TXBMU_PFI_SM_RESET 0x00010000
700#define SK_TXBMU_PFI_SM_UNRESET 0x00020000
701#define SK_TXBMU_FIFO_RESET 0x00040000
702#define SK_TXBMU_FIFO_UNRESET 0x00080000
703#define SK_TXBMU_DESC_RESET 0x00100000
704#define SK_TXBMU_DESC_UNRESET 0x00200000
705#define SK_TXBMU_SUPERVISOR_IDLE 0x01000000
706
707#define SK_TXBMU_ONLINE \
708 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \
709 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \
710 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \
711 SK_TXBMU_DESC_UNRESET)
712
713#define SK_TXBMU_OFFLINE \
714 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \
715 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \
716 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \
717 SK_TXBMU_DESC_RESET)
718
719/* Block 16 -- Receive RAMbuffer 1 */
720#define SK_RXRB1_START 0x0800
721#define SK_RXRB1_END 0x0804
722#define SK_RXRB1_WR_PTR 0x0808
723#define SK_RXRB1_RD_PTR 0x080C
724#define SK_RXRB1_UTHR_PAUSE 0x0810
725#define SK_RXRB1_LTHR_PAUSE 0x0814
726#define SK_RXRB1_UTHR_HIPRIO 0x0818
727#define SK_RXRB1_UTHR_LOPRIO 0x081C
728#define SK_RXRB1_PKTCNT 0x0820
729#define SK_RXRB1_LVL 0x0824
730#define SK_RXRB1_CTLTST 0x0828
731
732/* Block 17 -- Receive RAMbuffer 2 */
733#define SK_RXRB2_START 0x0880
734#define SK_RXRB2_END 0x0884
735#define SK_RXRB2_WR_PTR 0x0888
736#define SK_RXRB2_RD_PTR 0x088C
737#define SK_RXRB2_UTHR_PAUSE 0x0890
738#define SK_RXRB2_LTHR_PAUSE 0x0894
739#define SK_RXRB2_UTHR_HIPRIO 0x0898
740#define SK_RXRB2_UTHR_LOPRIO 0x089C
741#define SK_RXRB2_PKTCNT 0x08A0
742#define SK_RXRB2_LVL 0x08A4
743#define SK_RXRB2_CTLTST 0x08A8
744
745/* Block 20 -- Sync. Transmit RAMbuffer 1 */
746#define SK_TXRBS1_START 0x0A00
747#define SK_TXRBS1_END 0x0A04
748#define SK_TXRBS1_WR_PTR 0x0A08
749#define SK_TXRBS1_RD_PTR 0x0A0C
750#define SK_TXRBS1_PKTCNT 0x0A20
751#define SK_TXRBS1_LVL 0x0A24
752#define SK_TXRBS1_CTLTST 0x0A28
753
754/* Block 21 -- Async. Transmit RAMbuffer 1 */
755#define SK_TXRBA1_START 0x0A80
756#define SK_TXRBA1_END 0x0A84
757#define SK_TXRBA1_WR_PTR 0x0A88
758#define SK_TXRBA1_RD_PTR 0x0A8C
759#define SK_TXRBA1_PKTCNT 0x0AA0
760#define SK_TXRBA1_LVL 0x0AA4
761#define SK_TXRBA1_CTLTST 0x0AA8
762
763/* Block 22 -- Sync. Transmit RAMbuffer 2 */
764#define SK_TXRBS2_START 0x0B00
765#define SK_TXRBS2_END 0x0B04
766#define SK_TXRBS2_WR_PTR 0x0B08
767#define SK_TXRBS2_RD_PTR 0x0B0C
768#define SK_TXRBS2_PKTCNT 0x0B20
769#define SK_TXRBS2_LVL 0x0B24
770#define SK_TXRBS2_CTLTST 0x0B28
771
772/* Block 23 -- Async. Transmit RAMbuffer 2 */
773#define SK_TXRBA2_START 0x0B80
774#define SK_TXRBA2_END 0x0B84
775#define SK_TXRBA2_WR_PTR 0x0B88
776#define SK_TXRBA2_RD_PTR 0x0B8C
777#define SK_TXRBA2_PKTCNT 0x0BA0
778#define SK_TXRBA2_LVL 0x0BA4
779#define SK_TXRBA2_CTLTST 0x0BA8
780
781#define SK_RBCTL_RESET 0x00000001
782#define SK_RBCTL_UNRESET 0x00000002
783#define SK_RBCTL_OFF 0x00000004
784#define SK_RBCTL_ON 0x00000008
785#define SK_RBCTL_STORENFWD_OFF 0x00000010
786#define SK_RBCTL_STORENFWD_ON 0x00000020
787
788/* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */
789#define SK_RXF1_END 0x0C00
790#define SK_RXF1_WPTR 0x0C04
791#define SK_RXF1_RPTR 0x0C0C
792#define SK_RXF1_PKTCNT 0x0C10
793#define SK_RXF1_LVL 0x0C14
794#define SK_RXF1_MACCTL 0x0C18
795#define SK_RXF1_CTL 0x0C1C
796#define SK_RXLED1_CNTINIT 0x0C20
797#define SK_RXLED1_COUNTER 0x0C24
798#define SK_RXLED1_CTL 0x0C28
799#define SK_RXLED1_TST 0x0C29
800#define SK_LINK_SYNC1_CINIT 0x0C30
801#define SK_LINK_SYNC1_COUNTER 0x0C34
802#define SK_LINK_SYNC1_CTL 0x0C38
803#define SK_LINK_SYNC1_TST 0x0C39
804#define SK_LINKLED1_CTL 0x0C3C
805
806#define SK_FIFO_END 0x3F
807
808/* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */
809#define SK_RXF2_END 0x0C80
810#define SK_RXF2_WPTR 0x0C84
811#define SK_RXF2_RPTR 0x0C8C
812#define SK_RXF2_PKTCNT 0x0C90
813#define SK_RXF2_LVL 0x0C94
814#define SK_RXF2_MACCTL 0x0C98
815#define SK_RXF2_CTL 0x0C9C
816#define SK_RXLED2_CNTINIT 0x0CA0
817#define SK_RXLED2_COUNTER 0x0CA4
818#define SK_RXLED2_CTL 0x0CA8
819#define SK_RXLED2_TST 0x0CA9
820#define SK_LINK_SYNC2_CINIT 0x0CB0
821#define SK_LINK_SYNC2_COUNTER 0x0CB4
822#define SK_LINK_SYNC2_CTL 0x0CB8
823#define SK_LINK_SYNC2_TST 0x0CB9
824#define SK_LINKLED2_CTL 0x0CBC
825
826#define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001
827#define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002
828#define SK_RXMACCTL_TSTAMP_OFF 0x00000004
829#define SK_RXMACCTL_RSTAMP_ON 0x00000008
830#define SK_RXMACCTL_FLUSH_OFF 0x00000010
831#define SK_RXMACCTL_FLUSH_ON 0x00000020
832#define SK_RXMACCTL_PAUSE_OFF 0x00000040
833#define SK_RXMACCTL_PAUSE_ON 0x00000080
834#define SK_RXMACCTL_AFULL_OFF 0x00000100
835#define SK_RXMACCTL_AFULL_ON 0x00000200
836#define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400
837#define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800
838#define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000
839#define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000
840#define SK_RXMACCTL_STS_TIMEO 0x00FF0000
841#define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000
842
843#define SK_RXLEDCTL_ENABLE 0x0001
844#define SK_RXLEDCTL_COUNTER_STOP 0x0002
845#define SK_RXLEDCTL_COUNTER_START 0x0004
846
847#define SK_LINKLED_OFF 0x0001
848#define SK_LINKLED_ON 0x0002
849#define SK_LINKLED_LINKSYNC_OFF 0x0004
850#define SK_LINKLED_LINKSYNC_ON 0x0008
851#define SK_LINKLED_BLINK_OFF 0x0010
852#define SK_LINKLED_BLINK_ON 0x0020
853
854/* Block 26 -- TX MAC FIFO 1 regisrers */
855#define SK_TXF1_END 0x0D00
856#define SK_TXF1_WPTR 0x0D04
857#define SK_TXF1_RPTR 0x0D0C
858#define SK_TXF1_PKTCNT 0x0D10
859#define SK_TXF1_LVL 0x0D14
860#define SK_TXF1_MACCTL 0x0D18
861#define SK_TXF1_CTL 0x0D1C
862#define SK_TXLED1_CNTINIT 0x0D20
863#define SK_TXLED1_COUNTER 0x0D24
864#define SK_TXLED1_CTL 0x0D28
865#define SK_TXLED1_TST 0x0D29
866
867/* Block 27 -- TX MAC FIFO 2 regisrers */
868#define SK_TXF2_END 0x0D80
869#define SK_TXF2_WPTR 0x0D84
870#define SK_TXF2_RPTR 0x0D8C
871#define SK_TXF2_PKTCNT 0x0D90
872#define SK_TXF2_LVL 0x0D94
873#define SK_TXF2_MACCTL 0x0D98
874#define SK_TXF2_CTL 0x0D9C
875#define SK_TXLED2_CNTINIT 0x0DA0
876#define SK_TXLED2_COUNTER 0x0DA4
877#define SK_TXLED2_CTL 0x0DA8
878#define SK_TXLED2_TST 0x0DA9
879
880#define SK_TXMACCTL_XMAC_RESET 0x00000001
881#define SK_TXMACCTL_XMAC_UNRESET 0x00000002
882#define SK_TXMACCTL_LOOP_OFF 0x00000004
883#define SK_TXMACCTL_LOOP_ON 0x00000008
884#define SK_TXMACCTL_FLUSH_OFF 0x00000010
885#define SK_TXMACCTL_FLUSH_ON 0x00000020
886#define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040
887#define SK_TXMACCTL_WAITEMPTY_ON 0x00000080
888#define SK_TXMACCTL_AFULL_OFF 0x00000100
889#define SK_TXMACCTL_AFULL_ON 0x00000200
890#define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400
891#define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800
892#define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000
893#define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000
894#define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000
895#define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000
896
897#define SK_TXLEDCTL_ENABLE 0x0001
898#define SK_TXLEDCTL_COUNTER_STOP 0x0002
899#define SK_TXLEDCTL_COUNTER_START 0x0004
900
901#define SK_FIFO_RESET 0x00000001
902#define SK_FIFO_UNRESET 0x00000002
903#define SK_FIFO_OFF 0x00000004
904#define SK_FIFO_ON 0x00000008
905
906/* Block 0x40 to 0x4F -- XMAC 1 registers */
907#define SK_XMAC1_BASE 0x2000
908#define SK_XMAC1_END 0x23FF
909
910/* Block 0x60 to 0x6F -- XMAC 2 registers */
911#define SK_XMAC2_BASE 0x3000
912#define SK_XMAC2_END 0x33FF
913
914/* Compute relative offset of an XMAC register in the XMAC window(s). */
915#define SK_XMAC_REG(reg, mac) (((reg) * 2) + SK_XMAC1_BASE + \
916 (mac * (SK_XMAC2_BASE - SK_XMAC1_BASE)))
917
918#define SK_XM_READ_4(sc, reg) \
919 (sk_win_read_2(sc->sk_softc, \
920 SK_XMAC_REG(reg, sc->sk_port)) & 0xFFFF) | \
921 ((sk_win_read_2(sc->sk_softc, \
922 SK_XMAC_REG(reg + 2, sc->sk_port)) << 16) & 0xFFFF0000)
923
924#define SK_XM_WRITE_4(sc, reg, val) \
925 sk_win_write_2(sc->sk_softc, \
926 SK_XMAC_REG(reg, sc->sk_port), ((val) & 0xFFFF)); \
927 sk_win_write_2(sc->sk_softc, \
928 SK_XMAC_REG(reg + 2, sc->sk_port), ((val) >> 16) & 0xFFFF);
929
930#define SK_XM_READ_2(sc, reg) \
931 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(reg, sc->sk_port))
932
933#define SK_XM_WRITE_2(sc, reg, val) \
934 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(reg, sc->sk_port), val)
935
936#define SK_XM_SETBIT_4(sc, reg, x) \
937 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x))
938
939#define SK_XM_CLRBIT_4(sc, reg, x) \
940 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x))
941
942#define SK_XM_SETBIT_2(sc, reg, x) \
943 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x))
944
945#define SK_XM_CLRBIT_2(sc, reg, x) \
946 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x))
947
948
949/*
950 * The default FIFO threshold on the XMAC II is 4 bytes. On
951 * dual port NICs, this often leads to transmit underruns, so we
952 * bump the threshold a little.
953 */
954#define SK_XM_TX_FIFOTHRESH 512
955
956#define SK_PCI_VENDOR_ID 0x0000
957#define SK_PCI_DEVICE_ID 0x0002
958#define SK_PCI_COMMAND 0x0004
959#define SK_PCI_STATUS 0x0006
960#define SK_PCI_REVID 0x0008
961#define SK_PCI_CLASSCODE 0x0009
962#define SK_PCI_CACHELEN 0x000C
963#define SK_PCI_LATENCY_TIMER 0x000D
964#define SK_PCI_HEADER_TYPE 0x000E
965#define SK_PCI_LOMEM 0x0010
966#define SK_PCI_LOIO 0x0014
967#define SK_PCI_SUBVEN_ID 0x002C
968#define SK_PCI_SYBSYS_ID 0x002E
969#define SK_PCI_BIOSROM 0x0030
970#define SK_PCI_INTLINE 0x003C
971#define SK_PCI_INTPIN 0x003D
972#define SK_PCI_MINGNT 0x003E
973#define SK_PCI_MINLAT 0x003F
974
975/* device specific PCI registers */
976#define SK_PCI_OURREG1 0x0040
977#define SK_PCI_OURREG2 0x0044
978#define SK_PCI_CAPID 0x0048 /* 8 bits */
979#define SK_PCI_NEXTPTR 0x0049 /* 8 bits */
980#define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */
981#define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */
982#define SK_PCI_PME_EVENT 0x004F
983#define SK_PCI_VPD_CAPID 0x0050
984#define SK_PCI_VPD_NEXTPTR 0x0051
985#define SK_PCI_VPD_ADDR 0x0052
986#define SK_PCI_VPD_DATA 0x0054
987
988#define SK_PSTATE_MASK 0x0003
989#define SK_PSTATE_D0 0x0000
990#define SK_PSTATE_D1 0x0001
991#define SK_PSTATE_D2 0x0002
992#define SK_PSTATE_D3 0x0003
993#define SK_PME_EN 0x0010
994#define SK_PME_STATUS 0x8000
995
996/*
997 * VPD flag bit. Set to 0 to initiate a read, will become 1 when
998 * read is complete. Set to 1 to initiate a write, will become 0
999 * when write is finished.
1000 */
1001#define SK_VPD_FLAG 0x8000
1002
1003/* VPD structures */
1004struct vpd_res {
1005 u_int8_t vr_id;
1006 u_int8_t vr_len;
1007 u_int8_t vr_pad;
1008};
1009
1010struct vpd_key {
1011 char vk_key[2];
1012 u_int8_t vk_len;
1013};
1014
1015#define VPD_RES_ID 0x82 /* ID string */
1016#define VPD_RES_READ 0x90 /* start of read only area */
1017#define VPD_RES_WRITE 0x81 /* start of read/write area */
1018#define VPD_RES_END 0x78 /* end tag */
1019
1020#define CSR_WRITE_4(sc, reg, val) \
1021 bus_space_write_4(sc->sk_btag, sc->sk_bhandle, reg, val)
1022#define CSR_WRITE_2(sc, reg, val) \
1023 bus_space_write_2(sc->sk_btag, sc->sk_bhandle, reg, val)
1024#define CSR_WRITE_1(sc, reg, val) \
1025 bus_space_write_1(sc->sk_btag, sc->sk_bhandle, reg, val)
1026
1027#define CSR_READ_4(sc, reg) \
1028 bus_space_read_4(sc->sk_btag, sc->sk_bhandle, reg)
1029#define CSR_READ_2(sc, reg) \
1030 bus_space_read_2(sc->sk_btag, sc->sk_bhandle, reg)
1031#define CSR_READ_1(sc, reg) \
1032 bus_space_read_1(sc->sk_btag, sc->sk_bhandle, reg)
1033
1034struct sk_type {
1035 u_int16_t sk_vid;
1036 u_int16_t sk_did;
1037 char *sk_name;
1038};
1039
1040/* RX queue descriptor data structure */
1041struct sk_rx_desc {
1042 u_int32_t sk_ctl;
1043 u_int32_t sk_next;
1044 u_int32_t sk_data_lo;
1045 u_int32_t sk_data_hi;
1046 u_int32_t sk_xmac_rxstat;
1047 u_int32_t sk_timestamp;
1048 u_int16_t sk_csum2;
1049 u_int16_t sk_csum1;
1050 u_int16_t sk_csum2_start;
1051 u_int16_t sk_csum1_start;
1052};
1053
1054#define SK_OPCODE_DEFAULT 0x00550000
1055#define SK_OPCODE_CSUM 0x00560000
1056
1057#define SK_RXCTL_LEN 0x0000FFFF
1058#define SK_RXCTL_OPCODE 0x00FF0000
1059#define SK_RXCTL_TSTAMP_VALID 0x01000000
1060#define SK_RXCTL_STATUS_VALID 0x02000000
1061#define SK_RXCTL_DEV0 0x04000000
1062#define SK_RXCTL_EOF_INTR 0x08000000
1063#define SK_RXCTL_EOB_INTR 0x10000000
1064#define SK_RXCTL_LASTFRAG 0x20000000
1065#define SK_RXCTL_FIRSTFRAG 0x40000000
1066#define SK_RXCTL_OWN 0x80000000
1067
1068#define SK_RXSTAT \
1069 (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \
1070 SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN)
1071
1072struct sk_tx_desc {
1073 u_int32_t sk_ctl;
1074 u_int32_t sk_next;
1075 u_int32_t sk_data_lo;
1076 u_int32_t sk_data_hi;
1077 u_int32_t sk_xmac_txstat;
1078 u_int16_t sk_rsvd0;
1079 u_int16_t sk_csum_startval;
1080 u_int16_t sk_csum_startpos;
1081 u_int16_t sk_csum_writepos;
1082 u_int32_t sk_rsvd1;
1083};
1084
1085#define SK_TXCTL_LEN 0x0000FFFF
1086#define SK_TXCTL_OPCODE 0x00FF0000
1087#define SK_TXCTL_SW 0x01000000
1088#define SK_TXCTL_NOCRC 0x02000000
1089#define SK_TXCTL_STORENFWD 0x04000000
1090#define SK_TXCTL_EOF_INTR 0x08000000
1091#define SK_TXCTL_EOB_INTR 0x10000000
1092#define SK_TXCTL_LASTFRAG 0x20000000
1093#define SK_TXCTL_FIRSTFRAG 0x40000000
1094#define SK_TXCTL_OWN 0x80000000
1095
1096#define SK_TXSTAT \
1097 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN)
1098
1099#define SK_RXBYTES(x) (x) & 0x0000FFFF;
1100#define SK_TXBYTES SK_RXBYTES
1101
1102#define SK_TX_RING_CNT 512
1103#define SK_RX_RING_CNT 256
1104
1105/*
1106 * Jumbo buffer stuff. Note that we must allocate more jumbo
1107 * buffers than there are descriptors in the receive ring. This
1108 * is because we don't know how long it will take for a packet
1109 * to be released after we hand it off to the upper protocol
1110 * layers. To be safe, we allocate 1.5 times the number of
1111 * receive descriptors.
1112 */
1113#define SK_JUMBO_FRAMELEN 9018
1114#define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
1115#define SK_JSLOTS 384
1116
1117#define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN)
1118#define SK_JLEN (SK_JRAWLEN + (sizeof(u_int64_t) - \
1119 (SK_JRAWLEN % sizeof(u_int64_t))))
1120#define SK_JPAGESZ PAGE_SIZE
1121#define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ)
1122#define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID)
1123
1124struct sk_jpool_entry {
1125 int slot;
1126 SLIST_ENTRY(sk_jpool_entry) jpool_entries;
1127};
1128
1129struct sk_chain {
1130 void *sk_desc;
1131 struct mbuf *sk_mbuf;
1132 struct sk_chain *sk_next;
1133};
1134
1135struct sk_chain_data {
1136 struct sk_chain sk_tx_chain[SK_TX_RING_CNT];
1137 struct sk_chain sk_rx_chain[SK_RX_RING_CNT];
1138 int sk_tx_prod;
1139 int sk_tx_cons;
1140 int sk_tx_cnt;
1141 int sk_rx_prod;
1142 int sk_rx_cons;
1143 int sk_rx_cnt;
1144 /* Stick the jumbo mem management stuff here too. */
1145 caddr_t sk_jslots[SK_JSLOTS];
1146 void *sk_jumbo_buf;
1147
1148};
1149
1150struct sk_ring_data {
1151 struct sk_tx_desc sk_tx_ring[SK_TX_RING_CNT];
1152 struct sk_rx_desc sk_rx_ring[SK_RX_RING_CNT];
1153};
1154
1155struct sk_bcom_hack {
1156 int reg;
1157 int val;
1158};
1159
1160#define SK_INC(x, y) (x) = (x + 1) % y
1161
1162/* Forward decl. */
1163struct sk_if_softc;
1164
1165/* Softc for the GEnesis controller. */
1166struct sk_softc {
1167 bus_space_handle_t sk_bhandle; /* bus space handle */
1168 bus_space_tag_t sk_btag; /* bus space tag */
1169 void *sk_intrhand; /* irq handler handle */
1170 struct resource *sk_irq; /* IRQ resource handle */
1171 struct resource *sk_res; /* I/O or shared mem handle */
1172 u_int8_t sk_unit; /* controller number */
1173 u_int8_t sk_type;
1174 char *sk_vpd_prodname;
1175 char *sk_vpd_readonly;
1176 u_int32_t sk_rboff; /* RAMbuffer offset */
1177 u_int32_t sk_ramsize; /* amount of RAM on NIC */
1178 u_int32_t sk_pmd; /* physical media type */
1179 u_int32_t sk_intrmask;
1180 struct sk_if_softc *sk_if[2];
1181 device_t sk_devs[2];
1182 struct mtx sk_mtx;
1183};
1184
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