| sioreg.h (103881) | sioreg.h (112384) |
|---|---|
| 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)comreg.h 7.2 (Berkeley) 5/9/91 | 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)comreg.h 7.2 (Berkeley) 5/9/91 |
| 34 * $FreeBSD: head/sys/dev/sio/sioreg.h 103881 2002-09-24 02:35:57Z nyan $ | 34 * $FreeBSD: head/sys/dev/sio/sioreg.h 112384 2003-03-18 21:26:28Z sobomax $ |
| 35 */ 36 37/* Receiver clock frequency for "standard" pc serial ports. */ 38#define DEFAULT_RCLK 1843200 39 40/* interrupt enable register */ 41#define IER_ERXRDY 0x1 42#define IER_ETXRDY 0x2 --- 15 unchanged lines hidden (view full) --- 58#define FIFO_RCV_RST 0x02 59#define FIFO_XMT_RST 0x04 60#define FIFO_DMA_MODE 0x08 61#define FIFO_RX_LOW 0x00 62#define FIFO_RX_MEDL 0x40 63#define FIFO_RX_MEDH 0x80 64#define FIFO_RX_HIGH 0xc0 65 | 35 */ 36 37/* Receiver clock frequency for "standard" pc serial ports. */ 38#define DEFAULT_RCLK 1843200 39 40/* interrupt enable register */ 41#define IER_ERXRDY 0x1 42#define IER_ETXRDY 0x2 --- 15 unchanged lines hidden (view full) --- 58#define FIFO_RCV_RST 0x02 59#define FIFO_XMT_RST 0x04 60#define FIFO_DMA_MODE 0x08 61#define FIFO_RX_LOW 0x00 62#define FIFO_RX_MEDL 0x40 63#define FIFO_RX_MEDH 0x80 64#define FIFO_RX_HIGH 0xc0 65 |
| 66/* character format control register */ | 66/* character format control register (aka line control register) */ |
| 67#define CFCR_DLAB 0x80 68#define CFCR_SBREAK 0x40 69#define CFCR_PZERO 0x30 70#define CFCR_PONE 0x20 71#define CFCR_PEVEN 0x10 72#define CFCR_PODD 0x00 73#define CFCR_PENAB 0x08 74#define CFCR_STOPB 0x04 75#define CFCR_8BITS 0x03 76#define CFCR_7BITS 0x02 77#define CFCR_6BITS 0x01 78#define CFCR_5BITS 0x00 | 67#define CFCR_DLAB 0x80 68#define CFCR_SBREAK 0x40 69#define CFCR_PZERO 0x30 70#define CFCR_PONE 0x20 71#define CFCR_PEVEN 0x10 72#define CFCR_PODD 0x00 73#define CFCR_PENAB 0x08 74#define CFCR_STOPB 0x04 75#define CFCR_8BITS 0x03 76#define CFCR_7BITS 0x02 77#define CFCR_6BITS 0x01 78#define CFCR_5BITS 0x00 |
| 79#define CFCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ |
|
| 79 80/* modem control register */ | 80 81/* modem control register */ |
| 82#define MCR_PRESCALE 0x80 /* only available on 16650 up */ |
|
| 81#define MCR_LOOPBACK 0x10 82#define MCR_IENABLE 0x08 83#define MCR_DRS 0x04 84#define MCR_RTS 0x02 85#define MCR_DTR 0x01 86 87/* line status register */ 88#define LSR_RCV_FIFO 0x80 --- 11 unchanged lines hidden (view full) --- 100#define MSR_RI 0x40 101#define MSR_DSR 0x20 102#define MSR_CTS 0x10 103#define MSR_DDCD 0x08 104#define MSR_TERI 0x04 105#define MSR_DDSR 0x02 106#define MSR_DCTS 0x01 107 | 83#define MCR_LOOPBACK 0x10 84#define MCR_IENABLE 0x08 85#define MCR_DRS 0x04 86#define MCR_RTS 0x02 87#define MCR_DTR 0x01 88 89/* line status register */ 90#define LSR_RCV_FIFO 0x80 --- 11 unchanged lines hidden (view full) --- 102#define MSR_RI 0x40 103#define MSR_DSR 0x20 104#define MSR_CTS 0x10 105#define MSR_DDCD 0x08 106#define MSR_TERI 0x04 107#define MSR_DDSR 0x02 108#define MSR_DCTS 0x01 109 |
| 110/* enhanced feature register (only available on 16650 up) */ 111#define com_efr com_fifo 112#define EFR_EFE 0x10 /* enhanced functions enable */ 113 |
|
| 108#ifdef PC98 109/* Hardware extension mode register for RSB-2000/3000. */ 110#define com_emr com_msr 111#define EMR_EXBUFF 0x04 112#define EMR_CTSFLW 0x08 113#define EMR_DSRFLW 0x10 114#define EMR_RTSFLW 0x20 115#define EMR_DTRFLW 0x40 --- 17 unchanged lines hidden --- | 114#ifdef PC98 115/* Hardware extension mode register for RSB-2000/3000. */ 116#define com_emr com_msr 117#define EMR_EXBUFF 0x04 118#define EMR_CTSFLW 0x08 119#define EMR_DSRFLW 0x10 120#define EMR_RTSFLW 0x20 121#define EMR_DTRFLW 0x40 --- 17 unchanged lines hidden --- |