| sibareg.h (183371) | sibareg.h (203319) |
|---|---|
| 1/*- 2 * Copyright (c) 2007 Bruce M. Simpson. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2007 Bruce M. Simpson. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/dev/siba/sibareg.h 183371 2008-09-26 03:57:23Z imp $ | 26 * $FreeBSD: head/sys/dev/siba/sibareg.h 203319 2010-01-31 21:18:22Z weongyo $ |
| 27 */ 28 29/* 30 * TODO: sprom 31 * TODO: implement dma translation bits (if needed for system bus) 32 */ 33 34#ifndef _SIBA_SIBAREG_H_ 35#define _SIBA_SIBAREG_H_ 36 | 27 */ 28 29/* 30 * TODO: sprom 31 * TODO: implement dma translation bits (if needed for system bus) 32 */ 33 34#ifndef _SIBA_SIBAREG_H_ 35#define _SIBA_SIBAREG_H_ 36 |
| 37#define PCI_DEVICE_ID_BCM4401 0x4401 38#define PCI_DEVICE_ID_BCM4401B0 0x4402 39#define PCI_DEVICE_ID_BCM4401B1 0x170c 40#define SIBA_PCIR_BAR PCIR_BAR(0) 41#define SIBA_CCID_BCM4710 0x4710 42#define SIBA_CCID_BCM4704 0x4704 43#define SIBA_CCID_SENTRY5 0x5365 44 45/* 46 * ChipCommon registers. 47 */ 48#define SIBA_CC_CHIPID 0x0000 49#define SIBA_CC_IDMASK 0x0000ffff 50#define SIBA_CC_ID(id) (id & SIBA_CC_IDMASK) 51#define SIBA_CC_REVMASK 0x000f0000 52#define SIBA_CC_REVSHIFT 16 53#define SIBA_CC_REV(id) \ 54 ((id & SIBA_CC_REVMASK) >> SIBA_CC_REVSHIFT) 55#define SIBA_CC_PKGMASK 0x00F00000 56#define SIBA_CC_PKGSHIFT 20 57#define SIBA_CC_PKG(id) \ 58 ((id & SIBA_CC_PKGMASK) >> SIBA_CC_PKGSHIFT) 59#define SIBA_CC_NCORESMASK 0x0F000000 60#define SIBA_CC_NCORESSHIFT 24 61#define SIBA_CC_NCORES(id) \ 62 ((id & SIBA_CC_NCORESMASK) >> SIBA_CC_NCORESSHIFT) 63#define SIBA_CC_CAPS 0x0004 64#define SIBA_CC_CAPS_PWCTL 0x00040000 65#define SIBA_CC_CAPS_PMU 0x10000000 /* PMU (rev >= 20) */ 66#define SIBA_CC_CHIPCTL 0x0028 /* rev >= 11 */ 67#define SIBA_CC_CHIPSTAT 0x002C /* rev >= 11 */ 68#define SIBA_CC_BCAST_ADDR 0x0050 /* Broadcast Address */ 69#define SIBA_CC_BCAST_DATA 0x0054 /* Broadcast Data */ 70#define SIBA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */ 71#define SIBA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */ 72#define SIBA_CC_CLKSLOW 0x00b8 /* 6 <= Rev <= 9 only */ 73#define SIBA_CC_CLKSLOW_SRC 0x00000007 74#define SIBA_CC_CLKSLOW_SRC_CRYSTAL 0x00000001 75#define SIBA_CC_CLKSLOW_FSLOW 0x00000800 76#define SIBA_CC_CLKSLOW_IPLL 0x00001000 77#define SIBA_CC_CLKSLOW_ENXTAL 0x00002000 78#define SIBA_CC_CLKSYSCTL 0x00C0 /* Rev >= 3 only */ 79#define SIBA_CC_CLKCTLSTATUS 0x01e0 80#define SIBA_CC_CLKCTLSTATUS_HT 0x00010000 81#define SIBA_CC_UART0 0x0300 /* offset of UART0 */ 82#define SIBA_CC_UART1 0x0400 /* offset of UART1 */ 83#define SIBA_CC_PMUCTL 0x0600 /* PMU control */ 84#define SIBA_CC_PMUCTL_ILP 0xffff0000 /* mask */ 85#define SIBA_CC_PMUCTL_NOILP 0x00000200 86#define SIBA_CC_PMUCTL_XF 0x0000007c /* crystal freq */ 87#define SIBA_CC_PMUCTL_XF_VAL(id) ((id & 0x0000007c) >> 2) 88#define SIBA_CC_PMUCAPS 0x0604 89#define SIBA_CC_PMUCAPS_REV 0x000000ff 90#define SIBA_CC_PMU_MINRES 0x0618 91#define SIBA_CC_PMU_MAXRES 0x061c 92#define SIBA_CC_PMU_TABSEL 0x0620 93#define SIBA_CC_PMU_DEPMSK 0x0624 94#define SIBA_CC_PMU_UPDNTM 0x0628 95#define SIBA_CC_PLLCTL_ADDR 0x0660 96#define SIBA_CC_PLLCTL_DATA 0x0664 97 98#define SIBA_CC_PMU0_PLL0 0 99#define SIBA_CC_PMU0_PLL0_PDIV_MSK 0x00000001 100#define SIBA_CC_PMU0_PLL0_PDIV_FREQ 25000 101#define SIBA_CC_PMU0_PLL1 1 102#define SIBA_CC_PMU0_PLL1_IMSK 0xf0000000 103#define SIBA_CC_PMU0_PLL1_FMSK 0x0fffff00 104#define SIBA_CC_PMU0_PLL1_STOPMOD 0x00000040 105#define SIBA_CC_PMU0_PLL2 2 106#define SIBA_CC_PMU0_PLL2_IMSKHI 0x0000000f 107#define SIBA_CC_PMU1_PLL0 0 108#define SIBA_CC_PMU1_PLL0_P1DIV 0x00f00000 109#define SIBA_CC_PMU1_PLL0_P2DIV 0x0f000000 110#define SIBA_CC_PMU1_PLL2 2 111#define SIBA_CC_PMU1_PLL2_NDIVMODE 0x000e0000 112#define SIBA_CC_PMU1_PLL2_NDIVINT 0x1ff00000 113#define SIBA_CC_PMU1_PLL3 3 114#define SIBA_CC_PMU1_PLL3_NDIVFRAC 0x00ffffff 115#define SIBA_CC_PMU1_PLL5 5 116#define SIBA_CC_PMU1_PLL5_CLKDRV 0xffffff00 117 118#define SIBA_CC_PMU0_DEFAULT_XTALFREQ 20000 119#define SIBA_CC_PMU1_DEFAULT_FREQ 15360 120 121#define SIBA_CC_PMU1_PLLTAB_ENTRY \ 122{ \ 123 { 12000, 1, 3, 22, 0x9, 0xffffef }, \ 124 { 13000, 2, 1, 6, 0xb, 0x483483 }, \ 125 { 14400, 3, 1, 10, 0xa, 0x1c71c7 }, \ 126 { 15360, 4, 1, 5, 0xb, 0x755555 }, \ 127 { 16200, 5, 1, 10, 0x5, 0x6e9e06 }, \ 128 { 16800, 6, 1, 10, 0x5, 0x3cf3cf }, \ 129 { 19200, 7, 1, 9, 0x5, 0x17b425 }, \ 130 { 19800, 8, 1, 11, 0x4, 0xa57eb }, \ 131 { 20000, 9, 1, 11, 0x4, 0 }, \ 132 { 24000, 10, 3, 11, 0xa, 0 }, \ 133 { 25000, 11, 5, 16, 0xb, 0 }, \ 134 { 26000, 12, 1, 2, 0x10, 0xec4ec4 }, \ 135 { 30000, 13, 3, 8, 0xb, 0 }, \ 136 { 38400, 14, 1, 5, 0x4, 0x955555 }, \ 137 { 40000, 15, 1, 2, 0xb, 0 } \ 138} 139 140#define SIBA_CC_PMU0_PLLTAB_ENTRY \ 141{ \ 142 { 12000, 1, 73, 349525, }, { 13000, 2, 67, 725937, }, \ 143 { 14400, 3, 61, 116508, }, { 15360, 4, 57, 305834, }, \ 144 { 16200, 5, 54, 336579, }, { 16800, 6, 52, 399457, }, \ 145 { 19200, 7, 45, 873813, }, { 19800, 8, 44, 466033, }, \ 146 { 20000, 9, 44, 0, }, { 25000, 10, 70, 419430, }, \ 147 { 26000, 11, 67, 725937, }, { 30000, 12, 58, 699050, }, \ 148 { 38400, 13, 45, 873813, }, { 40000, 14, 45, 0, }, \ 149} 150 151#define SIBA_CC_PMU_4325_BURST 1 152#define SIBA_CC_PMU_4325_CLBURST 3 153#define SIBA_CC_PMU_4325_LN 10 154#define SIBA_CC_PMU_4325_CRYSTAL 13 155#define SIBA_CC_PMU_4325_RX_PWR 15 156#define SIBA_CC_PMU_4325_TX_PWR 16 157#define SIBA_CC_PMU_4325_LOGEN_PWR 18 158#define SIBA_CC_PMU_4325_AFE_PWR 19 159#define SIBA_CC_PMU_4325_BBPLL_PWR 20 160#define SIBA_CC_PMU_4325_HT 21 161#define SIBA_CC_PMU_4328_EXT_SWITCH_PWM 0 162#define SIBA_CC_PMU_4328_BB_SWITCH_PWM 1 163#define SIBA_CC_PMU_4328_BB_SWITCH_BURST 2 164#define SIBA_CC_PMU_4328_BB_EXT_SWITCH_BURST 3 165#define SIBA_CC_PMU_4328_ILP_REQUEST 4 166#define SIBA_CC_PMU_4328_RADSWITCH_PWM 5 /* radio switch */ 167#define SIBA_CC_PMU_4328_RADSWITCH_BURST 6 168#define SIBA_CC_PMU_4328_ROM_SWITCH 7 169#define SIBA_CC_PMU_4328_PA_REF 8 170#define SIBA_CC_PMU_4328_RADIO 9 171#define SIBA_CC_PMU_4328_AFE 10 172#define SIBA_CC_PMU_4328_PLL 11 173#define SIBA_CC_PMU_4328_BG_FILTBYP 12 174#define SIBA_CC_PMU_4328_TX_FILTBYP 13 175#define SIBA_CC_PMU_4328_RX_FILTBYP 14 176#define SIBA_CC_PMU_4328_CRYSTAL_PU 15 177#define SIBA_CC_PMU_4328_CRYSTAL_EN 16 178#define SIBA_CC_PMU_4328_BB_PLL_FILTBYP 17 179#define SIBA_CC_PMU_4328_RF_PLL_FILTBYP 18 180#define SIBA_CC_PMU_4328_BB_PLL_PU 19 181#define SIBA_CC_PMU_5354_BB_PLL_PU 19 182 183#define SIBA_CC_PMU_4325_RES_UPDOWN \ 184{ \ 185 { SIBA_CC_PMU_4325_CRYSTAL, 0x1501 } \ 186} 187 188#define SIBA_CC_PMU_4325_RES_DEPEND \ 189{ \ 190 { SIBA_CC_PMU_4325_HT, SIBA_CC_PMU_DEP_ADD, \ 191 ((1 << SIBA_CC_PMU_4325_RX_PWR) | \ 192 (1 << SIBA_CC_PMU_4325_TX_PWR) | \ 193 (1 << SIBA_CC_PMU_4325_LOGEN_PWR) | \ 194 (1 << SIBA_CC_PMU_4325_AFE_PWR)) } \ 195} 196 197#define SIBA_CC_PMU_4328_RES_UPDOWN \ 198{ \ 199 { SIBA_CC_PMU_4328_EXT_SWITCH_PWM, 0x0101 }, \ 200 { SIBA_CC_PMU_4328_BB_SWITCH_PWM, 0x1f01 }, \ 201 { SIBA_CC_PMU_4328_BB_SWITCH_BURST, 0x010f }, \ 202 { SIBA_CC_PMU_4328_BB_EXT_SWITCH_BURST, 0x0101 }, \ 203 { SIBA_CC_PMU_4328_ILP_REQUEST, 0x0202 }, \ 204 { SIBA_CC_PMU_4328_RADSWITCH_PWM, 0x0f01 }, \ 205 { SIBA_CC_PMU_4328_RADSWITCH_BURST, 0x0f01 }, \ 206 { SIBA_CC_PMU_4328_ROM_SWITCH, 0x0101 }, \ 207 { SIBA_CC_PMU_4328_PA_REF, 0x0f01 }, \ 208 { SIBA_CC_PMU_4328_RADIO, 0x0f01 }, \ 209 { SIBA_CC_PMU_4328_AFE, 0x0f01 }, \ 210 { SIBA_CC_PMU_4328_PLL, 0x0f01 }, \ 211 { SIBA_CC_PMU_4328_BG_FILTBYP, 0x0101 }, \ 212 { SIBA_CC_PMU_4328_TX_FILTBYP, 0x0101 }, \ 213 { SIBA_CC_PMU_4328_RX_FILTBYP, 0x0101 }, \ 214 { SIBA_CC_PMU_4328_CRYSTAL_PU, 0x0101 }, \ 215 { SIBA_CC_PMU_4328_CRYSTAL_EN, 0xa001 }, \ 216 { SIBA_CC_PMU_4328_BB_PLL_FILTBYP, 0x0101 }, \ 217 { SIBA_CC_PMU_4328_RF_PLL_FILTBYP, 0x0101 }, \ 218 { SIBA_CC_PMU_4328_BB_PLL_PU, 0x0701 }, \ 219} 220 221#define SIBA_CC_PMU_4328_RES_DEPEND \ 222{ \ 223 { SIBA_CC_PMU_4328_ILP_REQUEST, SIBA_CC_PMU_DEP_SET, \ 224 ((1 << SIBA_CC_PMU_4328_EXT_SWITCH_PWM) | \ 225 (1 << SIBA_CC_PMU_4328_BB_SWITCH_PWM)) }, \ 226} 227 228#define SIBA_CC_CHST_4325_PMUTOP_2B 0x00000200 229 230#define SIBA_BAR0 0x80 231#define SIBA_IRQMASK 0x94 232#define SIBA_GPIO_IN 0xb0 233#define SIBA_GPIO_OUT 0xb4 234#define SIBA_GPIO_OUT_EN 0xb8 235#define SIBA_GPIO_CRYSTAL 0x40 236#define SIBA_GPIO_PLL 0x80 237 238#define SIBA_REGWIN(x) \ 239 (SIBA_ENUM_START + ((x) * SIBA_CORE_LEN)) |
|
| 37#define SIBA_CORE_LEN 0x00001000 /* Size of cfg per core */ 38#define SIBA_CFG_END 0x00010000 /* Upper bound of cfg space */ 39#define SIBA_MAX_CORES (SIBA_CFG_END/SIBA_CORE_LEN) /* #max cores */ | 240#define SIBA_CORE_LEN 0x00001000 /* Size of cfg per core */ 241#define SIBA_CFG_END 0x00010000 /* Upper bound of cfg space */ 242#define SIBA_MAX_CORES (SIBA_CFG_END/SIBA_CORE_LEN) /* #max cores */ |
| 243#define SIBA_ENUM_START 0x18000000U 244#define SIBA_ENUM_END 0x18010000U |
|
| 40 | 245 |
| 41/* offset of high ID register */ 42#define SIBA_CORE_IDLO 0x00000ff8 43#define SIBA_CORE_IDHI 0x00000ffc | 246#define SIBA_DMA_TRANSLATION_MASK 0xc0000000 |
| 44 | 247 |
| 45/* 46 * Offsets of ChipCommon core registers. 47 * XXX: move to siba_cc 48 */ 49#define SIBA_CC_UART0 0x00000300 /* offset of UART0 */ 50#define SIBA_CC_UART1 0x00000400 /* offset of UART1 */ | 248#define SIBA_PCI_DMA 0x40000000U 249#define SIBA_TPS 0x0f18 250#define SIBA_TPS_BPFLAG 0x0000003f 251#define SIBA_IAS 0x0f90 /* Initiator Agent State */ 252#define SIBA_IAS_INBAND_ERR 0x00020000 253#define SIBA_IAS_TIMEOUT 0x00040000 254#define SIBA_INTR_MASK 0x0f94 255#define SIBA_TGSLOW 0x0f98 256#define SIBA_TGSLOW_RESET 0x00000001 /* target state low */ 257#define SIBA_TGSLOW_REJECT_22 0x00000002 258#define SIBA_TGSLOW_REJECT_23 0x00000004 259#define SIBA_TGSLOW_CLOCK 0x00010000 260#define SIBA_TGSLOW_FGC 0x00020000 261#define SIBA_TGSHIGH 0x0f9c 262#define SIBA_TGSHIGH_SERR 0x00000001 263#define SIBA_TGSHIGH_BUSY 0x00000004 264#define SIBA_TGSHIGH_DMA64 0x10000000 265#define SIBA_IMCFGLO 0x0fa8 266#define SIBA_IMCFGLO_SERTO 0x00000007 267#define SIBA_IMCFGLO_REQTO 0x00000070 268#define SIBA_IDLOW 0x0ff8 269#define SIBA_IDLOW_SSBREV 0xf0000000 270#define SIBA_IDLOW_SSBREV_22 0x00000000 271#define SIBA_IDLOW_SSBREV_23 0x10000000 272#define SIBA_IDLOW_SSBREV_24 0x40000000 273#define SIBA_IDLOW_SSBREV_25 0x50000000 274#define SIBA_IDLOW_SSBREV_26 0x60000000 275#define SIBA_IDLOW_SSBREV_27 0x70000000 276#define SIBA_IDHIGH 0x0ffc 277#define SIBA_IDHIGH_CORECODEMASK 0x00008FF0 /* Core Code */ 278#define SIBA_IDHIGH_CORECODE_SHIFT 4 279#define SIBA_IDHIGH_CORECODE(id) \ 280 ((id & SIBA_IDHIGH_CORECODEMASK) >> SIBA_IDHIGH_CORECODE_SHIFT) 281/* Revision Code (low part) */ 282#define SIBA_IDHIGH_REVLO 0x0000000f 283/* Revision Code (high part) */ 284#define SIBA_IDHIGH_REVHI 0x00007000 285#define SIBA_IDHIGH_REVHI_SHIFT 8 286#define SIBA_IDHIGH_REV(id) \ 287 ((id & SIBA_IDHIGH_REVLO) | ((id & SIBA_IDHIGH_REVHI) >> \ 288 SIBA_IDHIGH_REVHI_SHIFT)) 289#define SIBA_IDHIGH_VENDORMASK 0xFFFF0000 /* Vendor Code */ 290#define SIBA_IDHIGH_VENDOR_SHIFT 16 291#define SIBA_IDHIGH_VENDOR(id) \ 292 ((id & SIBA_IDHIGH_VENDORMASK) >> SIBA_IDHIGH_VENDOR_SHIFT) |
| 51 | 293 |
| 52#define SIBA_CC_CCID 0x0000 53#define SIBA_CC_IDMASK 0x0000FFFF 54#define SIBA_CC_REVMASK 0x000F0000 55#define SIBA_CC_REVSHIFT 16 56#define SIBA_CC_PACKMASK 0x00F00000 57#define SIBA_CC_PACKSHIFT 20 58#define SIBA_CC_NRCORESMASK 0x0F000000 59#define SIBA_CC_NRCORESSHIFT 24 | 294#define SIBA_SPROMSIZE_R123 64 295#define SIBA_SPROMSIZE_R4 220 296#define SIBA_SPROM_BASE 0x1000 297#define SIBA_SPROM_REV_CRC 0xff00 298#define SIBA_SPROM1_MAC_80211BG 0x1048 299#define SIBA_SPROM1_MAC_ETH 0x104e 300#define SIBA_SPROM1_MAC_80211A 0x1054 301#define SIBA_SPROM1_ETHPHY 0x105a 302#define SIBA_SPROM1_ETHPHY_MII_ETH0 0x001f 303#define SIBA_SPROM1_ETHPHY_MII_ETH1 0x03e0 304#define SIBA_SPROM1_ETHPHY_MDIO_ETH0 (1 << 14) 305#define SIBA_SPROM1_ETHPHY_MDIO_ETH1 (1 << 15) 306#define SIBA_SPROM1_BOARDINFO 0x105c 307#define SIBA_SPROM1_BOARDINFO_BREV 0x00ff 308#define SIBA_SPROM1_BOARDINFO_CCODE 0x0f00 309#define SIBA_SPROM1_BOARDINFO_ANTBG 0x3000 310#define SIBA_SPROM1_BOARDINFO_ANTA 0xc000 311#define SIBA_SPROM1_PA0B0 0x105e 312#define SIBA_SPROM1_PA0B1 0x1060 313#define SIBA_SPROM1_PA0B2 0x1062 314#define SIBA_SPROM1_GPIOA 0x1064 315#define SIBA_SPROM1_GPIOA_P0 0x00ff 316#define SIBA_SPROM1_GPIOA_P1 0xff00 317#define SIBA_SPROM1_GPIOB 0x1066 318#define SIBA_SPROM1_GPIOB_P2 0x00ff 319#define SIBA_SPROM1_GPIOB_P3 0xff00 320#define SIBA_SPROM1_MAXPWR 0x1068 321#define SIBA_SPROM1_MAXPWR_BG 0x00ff 322#define SIBA_SPROM1_MAXPWR_A 0xff00 323#define SIBA_SPROM1_PA1B0 0x106a 324#define SIBA_SPROM1_PA1B1 0x106c 325#define SIBA_SPROM1_PA1B2 0x106e 326#define SIBA_SPROM1_TSSI 0x1070 327#define SIBA_SPROM1_TSSI_BG 0x00ff 328#define SIBA_SPROM1_TSSI_A 0xff00 329#define SIBA_SPROM1_BFLOW 0x1072 330#define SIBA_SPROM1_AGAIN 0x1074 331#define SIBA_SPROM1_AGAIN_BG 0x00ff 332#define SIBA_SPROM1_AGAIN_A 0xff00 333#define SIBA_SPROM2_BFHIGH 0x1038 334#define SIBA_SPROM3_MAC_80211BG 0x104a 335#define SIBA_SPROM4_MAC_80211BG 0x104c 336#define SIBA_SPROM4_ETHPHY 0x105a 337#define SIBA_SPROM4_ETHPHY_ET0A 0x001f 338#define SIBA_SPROM4_ETHPHY_ET1A 0x03e0 339#define SIBA_SPROM4_CCODE 0x1052 340#define SIBA_SPROM4_ANTAVAIL 0x105d 341#define SIBA_SPROM4_ANTAVAIL_A 0x00ff 342#define SIBA_SPROM4_ANTAVAIL_BG 0xff00 343#define SIBA_SPROM4_BFLOW 0x1044 344#define SIBA_SPROM4_AGAIN01 0x105e 345#define SIBA_SPROM4_AGAIN0 0x00ff 346#define SIBA_SPROM4_AGAIN1 0xff00 347#define SIBA_SPROM4_AGAIN23 0x1060 348#define SIBA_SPROM4_AGAIN2 0x00ff 349#define SIBA_SPROM4_AGAIN3 0xff00 350#define SIBA_SPROM4_BFHIGH 0x1046 351#define SIBA_SPROM4_MAXP_BG 0x1080 352#define SIBA_SPROM4_MAXP_BG_MASK 0x00ff 353#define SIBA_SPROM4_TSSI_BG 0xff00 354#define SIBA_SPROM4_MAXP_A 0x108a 355#define SIBA_SPROM4_MAXP_A_MASK 0x00ff 356#define SIBA_SPROM4_TSSI_A 0xff00 357#define SIBA_SPROM4_GPIOA 0x1056 358#define SIBA_SPROM4_GPIOA_P0 0x00ff 359#define SIBA_SPROM4_GPIOA_P1 0xff00 360#define SIBA_SPROM4_GPIOB 0x1058 361#define SIBA_SPROM4_GPIOB_P2 0x00ff 362#define SIBA_SPROM4_GPIOB_P3 0xff00 363#define SIBA_SPROM5_BFLOW 0x104a 364#define SIBA_SPROM5_BFHIGH 0x104c 365#define SIBA_SPROM5_MAC_80211BG 0x1052 366#define SIBA_SPROM5_CCODE 0x1044 367#define SIBA_SPROM5_GPIOA 0x1076 368#define SIBA_SPROM5_GPIOA_P0 0x00ff 369#define SIBA_SPROM5_GPIOA_P1 0xff00 370#define SIBA_SPROM5_GPIOB 0x1078 371#define SIBA_SPROM5_GPIOB_P2 0x00ff 372#define SIBA_SPROM5_GPIOB_P3 0xff00 373#define SIBA_SPROM8_BFLOW 0x1084 374#define SIBA_SPROM8_BFHIGH 0x1086 375#define SIBA_SPROM8_CCODE 0x1092 376#define SIBA_SPROM8_ANTAVAIL 0x109c 377#define SIBA_SPROM8_ANTAVAIL_A 0xff00 378#define SIBA_SPROM8_ANTAVAIL_BG 0x00ff 379#define SIBA_SPROM8_AGAIN01 0x109e 380#define SIBA_SPROM8_AGAIN0 0x00ff 381#define SIBA_SPROM8_AGAIN1 0xff00 382#define SIBA_SPROM8_AGAIN23 0x10a0 383#define SIBA_SPROM8_AGAIN2 0x00ff 384#define SIBA_SPROM8_AGAIN3 0xff00 385#define SIBA_SPROM8_GPIOA 0x1096 386#define SIBA_SPROM8_GPIOA_P0 0x00ff 387#define SIBA_SPROM8_GPIOA_P1 0xff00 388#define SIBA_SPROM8_GPIOB 0x1098 389#define SIBA_SPROM8_GPIOB_P2 0x00ff 390#define SIBA_SPROM8_GPIOB_P3 0xff00 391#define SIBA_SPROM8_MAXP_BG 0x10c0 392#define SIBA_SPROM8_MAXP_BG_MASK 0x00ff 393#define SIBA_SPROM8_TSSI_BG 0xff00 394#define SIBA_SPROM8_MAXP_A 0x10c8 395#define SIBA_SPROM8_MAXP_A_MASK 0x00ff 396#define SIBA_SPROM8_TSSI_A 0xff00 |
| 60 | 397 |
| 61#define SIBA_IDHIGH_RCLO 0x0000000F /* Revision Code (low part) */ 62#define SIBA_IDHIGH_CC 0x00008FF0 /* Core Code */ 63#define SIBA_IDHIGH_CC_SHIFT 4 64#define SIBA_IDHIGH_RCHI 0x00007000 /* Revision Code (high part) */ 65#define SIBA_IDHIGH_RCHI_SHIFT 8 66#define SIBA_IDHIGH_VC 0xFFFF0000 /* Vendor Code */ 67#define SIBA_IDHIGH_VC_SHIFT 16 | 398#define SIBA_BOARDVENDOR_DELL 0x1028 399#define SIBA_BOARDVENDOR_BCM 0x14e4 400#define SIBA_BOARD_BCM4309G 0x0421 401#define SIBA_BOARD_MP4318 0x044a 402#define SIBA_BOARD_BU4306 0x0416 403#define SIBA_BOARD_BU4309 0x040a |
| 68 | 404 |
| 69#define SIBA_CCID_BCM4710 0x4710 70#define SIBA_CCID_BCM4704 0x4704 71#define SIBA_CCID_SENTRY5 0x5365 | 405#define SIBA_PCICORE_BCAST_ADDR SIBA_CC_BCAST_ADDR 406#define SIBA_PCICORE_BCAST_DATA SIBA_CC_BCAST_DATA 407#define SIBA_PCICORE_SBTOPCI0 0x0100 408#define SIBA_PCICORE_SBTOPCI1 0x0104 409#define SIBA_PCICORE_SBTOPCI2 0x0108 410#define SIBA_PCICORE_MDIO_CTL 0x0128 411#define SIBA_PCICORE_MDIO_DATA 0x012c 412#define SIBA_PCICORE_SBTOPCI_PREF 0x00000004 413#define SIBA_PCICORE_SBTOPCI_BURST 0x00000008 414#define SIBA_PCICORE_SBTOPCI_MRM 0x00000020 |
| 72 73#endif /* _SIBA_SIBAREG_H_ */ | 415 416#endif /* _SIBA_SIBAREG_H_ */ |