26 */
27
28#ifndef _SYS_EFX_H
29#define _SYS_EFX_H
30
31#include "efsys.h"
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
37#define EFX_STATIC_ASSERT(_cond) ((void)sizeof(char[(_cond) ? 1 : -1]))
38
39#define EFX_ARRAY_SIZE(_array) (sizeof(_array) / sizeof((_array)[0]))
40
41#ifndef EFSYS_MEM_IS_NULL
42#define EFSYS_MEM_IS_NULL(_esmp) ((_esmp)->esm_base == NULL)
43#endif
44
45typedef enum efx_family_e {
46 EFX_FAMILY_INVALID,
47 EFX_FAMILY_FALCON,
48 EFX_FAMILY_SIENA,
49 EFX_FAMILY_NTYPES
50} efx_family_t;
51
52extern __checkReturn int
53efx_family(
54 __in uint16_t venid,
55 __in uint16_t devid,
56 __out efx_family_t *efp);
57
58extern __checkReturn int
59efx_infer_family(
60 __in efsys_bar_t *esbp,
61 __out efx_family_t *efp);
62
63#define EFX_PCI_VENID_SFC 0x1924
64#define EFX_PCI_DEVID_FALCON 0x0710
65#define EFX_PCI_DEVID_BETHPAGE 0x0803
66#define EFX_PCI_DEVID_SIENA 0x0813
67#define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
68
69#define EFX_MEM_BAR 2
70
71/* Error codes */
72
73enum {
74 EFX_ERR_INVALID,
75 EFX_ERR_SRAM_OOB,
76 EFX_ERR_BUFID_DC_OOB,
77 EFX_ERR_MEM_PERR,
78 EFX_ERR_RBUF_OWN,
79 EFX_ERR_TBUF_OWN,
80 EFX_ERR_RDESQ_OWN,
81 EFX_ERR_TDESQ_OWN,
82 EFX_ERR_EVQ_OWN,
83 EFX_ERR_EVFF_OFLO,
84 EFX_ERR_ILL_ADDR,
85 EFX_ERR_SRAM_PERR,
86 EFX_ERR_NCODES
87};
88
89/* NIC */
90
91typedef struct efx_nic_s efx_nic_t;
92
93extern __checkReturn int
94efx_nic_create(
95 __in efx_family_t family,
96 __in efsys_identifier_t *esip,
97 __in efsys_bar_t *esbp,
98 __in efsys_lock_t *eslp,
99 __deref_out efx_nic_t **enpp);
100
101extern __checkReturn int
102efx_nic_probe(
103 __in efx_nic_t *enp);
104
105#if EFSYS_OPT_PCIE_TUNE
106
107extern __checkReturn int
108efx_nic_pcie_tune(
109 __in efx_nic_t *enp,
110 unsigned int nlanes);
111
112extern __checkReturn int
113efx_nic_pcie_extended_sync(
114 __in efx_nic_t *enp);
115
116#endif /* EFSYS_OPT_PCIE_TUNE */
117
118extern __checkReturn int
119efx_nic_init(
120 __in efx_nic_t *enp);
121
122extern __checkReturn int
123efx_nic_reset(
124 __in efx_nic_t *enp);
125
126#if EFSYS_OPT_DIAG
127
128extern __checkReturn int
129efx_nic_register_test(
130 __in efx_nic_t *enp);
131
132#endif /* EFSYS_OPT_DIAG */
133
134extern void
135efx_nic_fini(
136 __in efx_nic_t *enp);
137
138extern void
139efx_nic_unprobe(
140 __in efx_nic_t *enp);
141
142extern void
143efx_nic_destroy(
144 __in efx_nic_t *enp);
145
146#if EFSYS_OPT_MCDI
147
148typedef struct efx_mcdi_req_s efx_mcdi_req_t;
149
150typedef enum efx_mcdi_exception_e {
151 EFX_MCDI_EXCEPTION_MC_REBOOT,
152 EFX_MCDI_EXCEPTION_MC_BADASSERT,
153} efx_mcdi_exception_t;
154
155typedef struct efx_mcdi_transport_s {
156 void *emt_context;
157 void (*emt_execute)(void *, efx_mcdi_req_t *);
158 void (*emt_ev_cpl)(void *);
159 void (*emt_exception)(void *, efx_mcdi_exception_t);
160} efx_mcdi_transport_t;
161
162extern __checkReturn int
163efx_mcdi_init(
164 __in efx_nic_t *enp,
165 __in const efx_mcdi_transport_t *mtp);
166
167extern __checkReturn int
168efx_mcdi_reboot(
169 __in efx_nic_t *enp);
170
171extern void
172efx_mcdi_request_start(
173 __in efx_nic_t *enp,
174 __in efx_mcdi_req_t *emrp,
175 __in boolean_t ev_cpl);
176
177extern __checkReturn boolean_t
178efx_mcdi_request_poll(
179 __in efx_nic_t *enp);
180
181extern __checkReturn boolean_t
182efx_mcdi_request_abort(
183 __in efx_nic_t *enp);
184
185extern void
186efx_mcdi_fini(
187 __in efx_nic_t *enp);
188
189#endif /* EFSYS_OPT_MCDI */
190
191/* INTR */
192
193#define EFX_NINTR_FALCON 64
194#define EFX_NINTR_SIENA 1024
195
196typedef enum efx_intr_type_e {
197 EFX_INTR_INVALID = 0,
198 EFX_INTR_LINE,
199 EFX_INTR_MESSAGE,
200 EFX_INTR_NTYPES
201} efx_intr_type_t;
202
203#define EFX_INTR_SIZE (sizeof (efx_oword_t))
204
205extern __checkReturn int
206efx_intr_init(
207 __in efx_nic_t *enp,
208 __in efx_intr_type_t type,
209 __in efsys_mem_t *esmp);
210
211extern void
212efx_intr_enable(
213 __in efx_nic_t *enp);
214
215extern void
216efx_intr_disable(
217 __in efx_nic_t *enp);
218
219extern void
220efx_intr_disable_unlocked(
221 __in efx_nic_t *enp);
222
223#define EFX_INTR_NEVQS 32
224
225extern __checkReturn int
226efx_intr_trigger(
227 __in efx_nic_t *enp,
228 __in unsigned int level);
229
230extern void
231efx_intr_status_line(
232 __in efx_nic_t *enp,
233 __out boolean_t *fatalp,
234 __out uint32_t *maskp);
235
236extern void
237efx_intr_status_message(
238 __in efx_nic_t *enp,
239 __in unsigned int message,
240 __out boolean_t *fatalp);
241
242extern void
243efx_intr_fatal(
244 __in efx_nic_t *enp);
245
246extern void
247efx_intr_fini(
248 __in efx_nic_t *enp);
249
250/* MAC */
251
252#if EFSYS_OPT_MAC_STATS
253
254/* START MKCONFIG GENERATED EfxHeaderMacBlock bb8d39428b6fdcf5 */
255typedef enum efx_mac_stat_e {
256 EFX_MAC_RX_OCTETS,
257 EFX_MAC_RX_PKTS,
258 EFX_MAC_RX_UNICST_PKTS,
259 EFX_MAC_RX_MULTICST_PKTS,
260 EFX_MAC_RX_BRDCST_PKTS,
261 EFX_MAC_RX_PAUSE_PKTS,
262 EFX_MAC_RX_LE_64_PKTS,
263 EFX_MAC_RX_65_TO_127_PKTS,
264 EFX_MAC_RX_128_TO_255_PKTS,
265 EFX_MAC_RX_256_TO_511_PKTS,
266 EFX_MAC_RX_512_TO_1023_PKTS,
267 EFX_MAC_RX_1024_TO_15XX_PKTS,
268 EFX_MAC_RX_GE_15XX_PKTS,
269 EFX_MAC_RX_ERRORS,
270 EFX_MAC_RX_FCS_ERRORS,
271 EFX_MAC_RX_DROP_EVENTS,
272 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
273 EFX_MAC_RX_SYMBOL_ERRORS,
274 EFX_MAC_RX_ALIGN_ERRORS,
275 EFX_MAC_RX_INTERNAL_ERRORS,
276 EFX_MAC_RX_JABBER_PKTS,
277 EFX_MAC_RX_LANE0_CHAR_ERR,
278 EFX_MAC_RX_LANE1_CHAR_ERR,
279 EFX_MAC_RX_LANE2_CHAR_ERR,
280 EFX_MAC_RX_LANE3_CHAR_ERR,
281 EFX_MAC_RX_LANE0_DISP_ERR,
282 EFX_MAC_RX_LANE1_DISP_ERR,
283 EFX_MAC_RX_LANE2_DISP_ERR,
284 EFX_MAC_RX_LANE3_DISP_ERR,
285 EFX_MAC_RX_MATCH_FAULT,
286 EFX_MAC_RX_NODESC_DROP_CNT,
287 EFX_MAC_TX_OCTETS,
288 EFX_MAC_TX_PKTS,
289 EFX_MAC_TX_UNICST_PKTS,
290 EFX_MAC_TX_MULTICST_PKTS,
291 EFX_MAC_TX_BRDCST_PKTS,
292 EFX_MAC_TX_PAUSE_PKTS,
293 EFX_MAC_TX_LE_64_PKTS,
294 EFX_MAC_TX_65_TO_127_PKTS,
295 EFX_MAC_TX_128_TO_255_PKTS,
296 EFX_MAC_TX_256_TO_511_PKTS,
297 EFX_MAC_TX_512_TO_1023_PKTS,
298 EFX_MAC_TX_1024_TO_15XX_PKTS,
299 EFX_MAC_TX_GE_15XX_PKTS,
300 EFX_MAC_TX_ERRORS,
301 EFX_MAC_TX_SGL_COL_PKTS,
302 EFX_MAC_TX_MULT_COL_PKTS,
303 EFX_MAC_TX_EX_COL_PKTS,
304 EFX_MAC_TX_LATE_COL_PKTS,
305 EFX_MAC_TX_DEF_PKTS,
306 EFX_MAC_TX_EX_DEF_PKTS,
307 EFX_MAC_NSTATS
308} efx_mac_stat_t;
309
310/* END MKCONFIG GENERATED EfxHeaderMacBlock */
311
312#endif /* EFSYS_OPT_MAC_STATS */
313
314typedef enum efx_link_mode_e {
315 EFX_LINK_UNKNOWN = 0,
316 EFX_LINK_DOWN,
317 EFX_LINK_10HDX,
318 EFX_LINK_10FDX,
319 EFX_LINK_100HDX,
320 EFX_LINK_100FDX,
321 EFX_LINK_1000HDX,
322 EFX_LINK_1000FDX,
323 EFX_LINK_10000FDX,
324 EFX_LINK_NMODES
325} efx_link_mode_t;
326
327#define EFX_MAC_SDU_MAX 9202
328
329#define EFX_MAC_PDU(_sdu) \
330 P2ROUNDUP(((_sdu) \
331 + /* EtherII */ 14 \
332 + /* VLAN */ 4 \
333 + /* CRC */ 4 \
334 + /* bug16011 */ 16), \
335 (1 << 3))
336
337#define EFX_MAC_PDU_MIN 60
338#define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
339
340extern __checkReturn int
341efx_mac_pdu_set(
342 __in efx_nic_t *enp,
343 __in size_t pdu);
344
345extern __checkReturn int
346efx_mac_addr_set(
347 __in efx_nic_t *enp,
348 __in uint8_t *addr);
349
350extern __checkReturn int
351efx_mac_filter_set(
352 __in efx_nic_t *enp,
353 __in boolean_t unicst,
354 __in boolean_t brdcst);
355
356extern __checkReturn int
357efx_mac_drain(
358 __in efx_nic_t *enp,
359 __in boolean_t enabled);
360
361extern __checkReturn int
362efx_mac_up(
363 __in efx_nic_t *enp,
364 __out boolean_t *mac_upp);
365
366#define EFX_FCNTL_RESPOND 0x00000001
367#define EFX_FCNTL_GENERATE 0x00000002
368
369extern __checkReturn int
370efx_mac_fcntl_set(
371 __in efx_nic_t *enp,
372 __in unsigned int fcntl,
373 __in boolean_t autoneg);
374
375extern void
376efx_mac_fcntl_get(
377 __in efx_nic_t *enp,
378 __out unsigned int *fcntl_wantedp,
379 __out unsigned int *fcntl_linkp);
380
381#define EFX_MAC_HASH_BITS (1 << 8)
382
383extern __checkReturn int
384efx_mac_hash_set(
385 __in efx_nic_t *enp,
386 __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket);
387
388#if EFSYS_OPT_MAC_STATS
389
390#if EFSYS_OPT_NAMES
391
392extern __checkReturn const char __cs *
393efx_mac_stat_name(
394 __in efx_nic_t *enp,
395 __in unsigned int id);
396
397#endif /* EFSYS_OPT_NAMES */
398
399#define EFX_MAC_STATS_SIZE 0x400
400
401/*
402 * Upload mac statistics supported by the hardware into the given buffer.
403 *
404 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
405 * and page aligned.
406 *
407 * The hardware will only DMA statistics that it understands (of course).
408 * Drivers should not make any assumptions about which statistics are
409 * supported, especially when the statistics are generated by firmware.
410 *
411 * Thus, drivers should zero this buffer before use, so that not-understood
412 * statistics read back as zero.
413 */
414extern __checkReturn int
415efx_mac_stats_upload(
416 __in efx_nic_t *enp,
417 __in efsys_mem_t *esmp);
418
419extern __checkReturn int
420efx_mac_stats_periodic(
421 __in efx_nic_t *enp,
422 __in efsys_mem_t *esmp,
423 __in uint16_t period_ms,
424 __in boolean_t events);
425
426extern __checkReturn int
427efx_mac_stats_update(
428 __in efx_nic_t *enp,
429 __in efsys_mem_t *esmp,
430 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
431 __out_opt uint32_t *generationp);
432
433#endif /* EFSYS_OPT_MAC_STATS */
434
435/* MON */
436
437typedef enum efx_mon_type_e {
438 EFX_MON_INVALID = 0,
439 EFX_MON_NULL,
440 EFX_MON_LM87,
441 EFX_MON_MAX6647,
442 EFX_MON_SFC90X0,
443 EFX_MON_NTYPES
444} efx_mon_type_t;
445
446#if EFSYS_OPT_NAMES
447
448extern const char __cs *
449efx_mon_name(
450 __in efx_nic_t *enp);
451
452#endif /* EFSYS_OPT_NAMES */
453
454extern __checkReturn int
455efx_mon_init(
456 __in efx_nic_t *enp);
457
458#if EFSYS_OPT_MON_STATS
459
460#define EFX_MON_STATS_SIZE 0x100
461
462/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 16a14e61aa4f8d80 */
463typedef enum efx_mon_stat_e {
464 EFX_MON_STAT_2_5V,
465 EFX_MON_STAT_VCCP1,
466 EFX_MON_STAT_VCC,
467 EFX_MON_STAT_5V,
468 EFX_MON_STAT_12V,
469 EFX_MON_STAT_VCCP2,
470 EFX_MON_STAT_EXT_TEMP,
471 EFX_MON_STAT_INT_TEMP,
472 EFX_MON_STAT_AIN1,
473 EFX_MON_STAT_AIN2,
474 EFX_MON_STAT_INT_COOLING,
475 EFX_MON_STAT_EXT_COOLING,
476 EFX_MON_STAT_1V,
477 EFX_MON_STAT_1_2V,
478 EFX_MON_STAT_1_8V,
479 EFX_MON_STAT_3_3V,
480 EFX_MON_NSTATS
481} efx_mon_stat_t;
482
483/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
484
485typedef enum efx_mon_stat_state_e {
486 EFX_MON_STAT_STATE_OK = 0,
487 EFX_MON_STAT_STATE_WARNING = 1,
488 EFX_MON_STAT_STATE_FATAL = 2,
489 EFX_MON_STAT_STATE_BROKEN = 3,
490} efx_mon_stat_state_t;
491
492typedef struct efx_mon_stat_value_t {
493 uint16_t emsv_value;
494 uint16_t emsv_state;
495} efx_mon_stat_value_t;
496
497#if EFSYS_OPT_NAMES
498
499extern const char __cs *
500efx_mon_stat_name(
501 __in efx_nic_t *enp,
502 __in efx_mon_stat_t id);
503
504#endif /* EFSYS_OPT_NAMES */
505
506extern __checkReturn int
507efx_mon_stats_update(
508 __in efx_nic_t *enp,
509 __in efsys_mem_t *esmp,
510 __out_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
511
512#endif /* EFSYS_OPT_MON_STATS */
513
514extern void
515efx_mon_fini(
516 __in efx_nic_t *enp);
517
518/* PHY */
519
520#define PMA_PMD_MMD 1
521#define PCS_MMD 3
522#define PHY_XS_MMD 4
523#define DTE_XS_MMD 5
524#define AN_MMD 7
525#define CL22EXT_MMD 29
526
527#define MAXMMD ((1 << 5) - 1)
528
529/* PHY types */
530#define EFX_PHY_NULL 0x0
531#define EFX_PHY_TXC43128 0x1
532#define EFX_PHY_SFX7101 0x3
533#define EFX_PHY_QT2022C2 0x4
534#define EFX_PHY_SFT9001A 0x8
535#define EFX_PHY_QT2025C 0x9
536#define EFX_PHY_SFT9001B 0xa
537#define EFX_PHY_QLX111V 0xc
538
539extern __checkReturn int
540efx_phy_verify(
541 __in efx_nic_t *enp);
542
543#if EFSYS_OPT_PHY_LED_CONTROL
544
545typedef enum efx_phy_led_mode_e {
546 EFX_PHY_LED_DEFAULT = 0,
547 EFX_PHY_LED_OFF,
548 EFX_PHY_LED_ON,
549 EFX_PHY_LED_FLASH,
550 EFX_PHY_LED_NMODES
551} efx_phy_led_mode_t;
552
553extern __checkReturn int
554efx_phy_led_set(
555 __in efx_nic_t *enp,
556 __in efx_phy_led_mode_t mode);
557
558#endif /* EFSYS_OPT_PHY_LED_CONTROL */
559
560extern __checkReturn int
561efx_port_init(
562 __in efx_nic_t *enp);
563
564#if EFSYS_OPT_LOOPBACK
565
566typedef enum efx_loopback_type_e {
567 EFX_LOOPBACK_OFF = 0,
568 EFX_LOOPBACK_DATA = 1,
569 EFX_LOOPBACK_GMAC = 2,
570 EFX_LOOPBACK_XGMII = 3,
571 EFX_LOOPBACK_XGXS = 4,
572 EFX_LOOPBACK_XAUI = 5,
573 EFX_LOOPBACK_GMII = 6,
574 EFX_LOOPBACK_SGMII = 7,
575 EFX_LOOPBACK_XGBR = 8,
576 EFX_LOOPBACK_XFI = 9,
577 EFX_LOOPBACK_XAUI_FAR = 10,
578 EFX_LOOPBACK_GMII_FAR = 11,
579 EFX_LOOPBACK_SGMII_FAR = 12,
580 EFX_LOOPBACK_XFI_FAR = 13,
581 EFX_LOOPBACK_GPHY = 14,
582 EFX_LOOPBACK_PHY_XS = 15,
583 EFX_LOOPBACK_PCS = 16,
584 EFX_LOOPBACK_PMA_PMD = 17,
585 EFX_LOOPBACK_NTYPES
586} efx_loopback_type_t;
587
588#define EFX_LOOPBACK_MAC_MASK \
589 ((1 << EFX_LOOPBACK_DATA) | \
590 (1 << EFX_LOOPBACK_GMAC) | \
591 (1 << EFX_LOOPBACK_XGMII) | \
592 (1 << EFX_LOOPBACK_XGXS) | \
593 (1 << EFX_LOOPBACK_XAUI) | \
594 (1 << EFX_LOOPBACK_GMII) | \
595 (1 << EFX_LOOPBACK_SGMII) | \
596 (1 << EFX_LOOPBACK_XGBR) | \
597 (1 << EFX_LOOPBACK_XFI) | \
598 (1 << EFX_LOOPBACK_XAUI_FAR) | \
599 (1 << EFX_LOOPBACK_GMII_FAR) | \
600 (1 << EFX_LOOPBACK_SGMII_FAR) | \
601 (1 << EFX_LOOPBACK_XFI_FAR))
602
603#define EFX_LOOPBACK_MASK \
604 ((1 << EFX_LOOPBACK_NTYPES) - 1)
605
606extern __checkReturn int
607efx_port_loopback_set(
608 __in efx_nic_t *enp,
609 __in efx_link_mode_t link_mode,
610 __in efx_loopback_type_t type);
611
612#if EFSYS_OPT_NAMES
613
614extern __checkReturn const char __cs *
615efx_loopback_type_name(
616 __in efx_nic_t *enp,
617 __in efx_loopback_type_t type);
618
619#endif /* EFSYS_OPT_NAMES */
620
621#endif /* EFSYS_OPT_LOOPBACK */
622
623extern __checkReturn int
624efx_port_poll(
625 __in efx_nic_t *enp,
626 __out efx_link_mode_t *link_modep);
627
628extern void
629efx_port_fini(
630 __in efx_nic_t *enp);
631
632typedef enum efx_phy_cap_type_e {
633 EFX_PHY_CAP_INVALID = 0,
634 EFX_PHY_CAP_10HDX,
635 EFX_PHY_CAP_10FDX,
636 EFX_PHY_CAP_100HDX,
637 EFX_PHY_CAP_100FDX,
638 EFX_PHY_CAP_1000HDX,
639 EFX_PHY_CAP_1000FDX,
640 EFX_PHY_CAP_10000FDX,
641 EFX_PHY_CAP_PAUSE,
642 EFX_PHY_CAP_ASYM,
643 EFX_PHY_CAP_AN,
644 EFX_PHY_CAP_NTYPES
645} efx_phy_cap_type_t;
646
647
648#define EFX_PHY_CAP_CURRENT 0x00000000
649#define EFX_PHY_CAP_DEFAULT 0x00000001
650#define EFX_PHY_CAP_PERM 0x00000002
651
652extern void
653efx_phy_adv_cap_get(
654 __in efx_nic_t *enp,
655 __in uint32_t flag,
656 __out uint32_t *maskp);
657
658extern __checkReturn int
659efx_phy_adv_cap_set(
660 __in efx_nic_t *enp,
661 __in uint32_t mask);
662
663extern void
664efx_phy_lp_cap_get(
665 __in efx_nic_t *enp,
666 __out uint32_t *maskp);
667
668extern __checkReturn int
669efx_phy_oui_get(
670 __in efx_nic_t *enp,
671 __out uint32_t *ouip);
672
673typedef enum efx_phy_media_type_e {
674 EFX_PHY_MEDIA_INVALID = 0,
675 EFX_PHY_MEDIA_XAUI,
676 EFX_PHY_MEDIA_CX4,
677 EFX_PHY_MEDIA_KX4,
678 EFX_PHY_MEDIA_XFP,
679 EFX_PHY_MEDIA_SFP_PLUS,
680 EFX_PHY_MEDIA_BASE_T,
681 EFX_PHY_MEDIA_NTYPES
682} efx_phy_media_type_t;
683
684/* Get the type of medium currently used. If the board has ports for
685 * modules, a module is present, and we recognise the media type of
686 * the module, then this will be the media type of the module.
687 * Otherwise it will be the media type of the port.
688 */
689extern void
690efx_phy_media_type_get(
691 __in efx_nic_t *enp,
692 __out efx_phy_media_type_t *typep);
693
694#if EFSYS_OPT_PHY_STATS
695
696/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
697typedef enum efx_phy_stat_e {
698 EFX_PHY_STAT_OUI,
699 EFX_PHY_STAT_PMA_PMD_LINK_UP,
700 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
701 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
702 EFX_PHY_STAT_PMA_PMD_REV_A,
703 EFX_PHY_STAT_PMA_PMD_REV_B,
704 EFX_PHY_STAT_PMA_PMD_REV_C,
705 EFX_PHY_STAT_PMA_PMD_REV_D,
706 EFX_PHY_STAT_PCS_LINK_UP,
707 EFX_PHY_STAT_PCS_RX_FAULT,
708 EFX_PHY_STAT_PCS_TX_FAULT,
709 EFX_PHY_STAT_PCS_BER,
710 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
711 EFX_PHY_STAT_PHY_XS_LINK_UP,
712 EFX_PHY_STAT_PHY_XS_RX_FAULT,
713 EFX_PHY_STAT_PHY_XS_TX_FAULT,
714 EFX_PHY_STAT_PHY_XS_ALIGN,
715 EFX_PHY_STAT_PHY_XS_SYNC_A,
716 EFX_PHY_STAT_PHY_XS_SYNC_B,
717 EFX_PHY_STAT_PHY_XS_SYNC_C,
718 EFX_PHY_STAT_PHY_XS_SYNC_D,
719 EFX_PHY_STAT_AN_LINK_UP,
720 EFX_PHY_STAT_AN_MASTER,
721 EFX_PHY_STAT_AN_LOCAL_RX_OK,
722 EFX_PHY_STAT_AN_REMOTE_RX_OK,
723 EFX_PHY_STAT_CL22EXT_LINK_UP,
724 EFX_PHY_STAT_SNR_A,
725 EFX_PHY_STAT_SNR_B,
726 EFX_PHY_STAT_SNR_C,
727 EFX_PHY_STAT_SNR_D,
728 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
729 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
730 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
731 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
732 EFX_PHY_STAT_AN_COMPLETE,
733 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
734 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
735 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
736 EFX_PHY_STAT_PCS_FW_VERSION_0,
737 EFX_PHY_STAT_PCS_FW_VERSION_1,
738 EFX_PHY_STAT_PCS_FW_VERSION_2,
739 EFX_PHY_STAT_PCS_FW_VERSION_3,
740 EFX_PHY_STAT_PCS_FW_BUILD_YY,
741 EFX_PHY_STAT_PCS_FW_BUILD_MM,
742 EFX_PHY_STAT_PCS_FW_BUILD_DD,
743 EFX_PHY_STAT_PCS_OP_MODE,
744 EFX_PHY_NSTATS
745} efx_phy_stat_t;
746
747/* END MKCONFIG GENERATED PhyHeaderStatsBlock */
748
749#if EFSYS_OPT_NAMES
750
751extern const char __cs *
752efx_phy_stat_name(
753 __in efx_nic_t *enp,
754 __in efx_phy_stat_t stat);
755
756#endif /* EFSYS_OPT_NAMES */
757
758#define EFX_PHY_STATS_SIZE 0x100
759
760extern __checkReturn int
761efx_phy_stats_update(
762 __in efx_nic_t *enp,
763 __in efsys_mem_t *esmp,
764 __out_ecount(EFX_PHY_NSTATS) uint32_t *stat);
765
766#endif /* EFSYS_OPT_PHY_STATS */
767
768#if EFSYS_OPT_PHY_PROPS
769
770#if EFSYS_OPT_NAMES
771
772extern const char __cs *
773efx_phy_prop_name(
774 __in efx_nic_t *enp,
775 __in unsigned int id);
776
777#endif /* EFSYS_OPT_NAMES */
778
779#define EFX_PHY_PROP_DEFAULT 0x00000001
780
781extern __checkReturn int
782efx_phy_prop_get(
783 __in efx_nic_t *enp,
784 __in unsigned int id,
785 __in uint32_t flags,
786 __out uint32_t *valp);
787
788extern __checkReturn int
789efx_phy_prop_set(
790 __in efx_nic_t *enp,
791 __in unsigned int id,
792 __in uint32_t val);
793
794#endif /* EFSYS_OPT_PHY_PROPS */
795
796#if EFSYS_OPT_PHY_BIST
797
798typedef enum efx_phy_bist_type_e {
799 EFX_PHY_BIST_TYPE_UNKNOWN,
800 EFX_PHY_BIST_TYPE_NORMAL,
801 EFX_PHY_BIST_TYPE_CABLE_SHORT,
802 EFX_PHY_BIST_TYPE_CABLE_LONG,
803 EFX_PHY_BIST_TYPE_NTYPES,
804} efx_phy_bist_type_t;
805
806typedef enum efx_phy_bist_result_e {
807 EFX_PHY_BIST_RESULT_UNKNOWN,
808 EFX_PHY_BIST_RESULT_RUNNING,
809 EFX_PHY_BIST_RESULT_PASSED,
810 EFX_PHY_BIST_RESULT_FAILED,
811} efx_phy_bist_result_t;
812
813typedef enum efx_phy_cable_status_e {
814 EFX_PHY_CABLE_STATUS_OK,
815 EFX_PHY_CABLE_STATUS_INVALID,
816 EFX_PHY_CABLE_STATUS_OPEN,
817 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
818 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
819 EFX_PHY_CABLE_STATUS_BUSY,
820} efx_phy_cable_status_t;
821
822typedef enum efx_phy_bist_value_e {
823 EFX_PHY_BIST_CABLE_LENGTH_A,
824 EFX_PHY_BIST_CABLE_LENGTH_B,
825 EFX_PHY_BIST_CABLE_LENGTH_C,
826 EFX_PHY_BIST_CABLE_LENGTH_D,
827 EFX_PHY_BIST_CABLE_STATUS_A,
828 EFX_PHY_BIST_CABLE_STATUS_B,
829 EFX_PHY_BIST_CABLE_STATUS_C,
830 EFX_PHY_BIST_CABLE_STATUS_D,
831 EFX_PHY_BIST_FAULT_CODE,
832 EFX_PHY_BIST_NVALUES,
833} efx_phy_bist_value_t;
834
835extern __checkReturn int
836efx_phy_bist_start(
837 __in efx_nic_t *enp,
838 __in efx_phy_bist_type_t type);
839
840extern __checkReturn int
841efx_phy_bist_poll(
842 __in efx_nic_t *enp,
843 __in efx_phy_bist_type_t type,
844 __out efx_phy_bist_result_t *resultp,
845 __out_opt uint32_t *value_maskp,
846 __out_ecount_opt(count) unsigned long *valuesp,
847 __in size_t count);
848
849extern void
850efx_phy_bist_stop(
851 __in efx_nic_t *enp,
852 __in efx_phy_bist_type_t type);
853
854#endif /* EFSYS_OPT_PHY_BIST */
855
856#define EFX_FEATURE_IPV6 0x00000001
857#define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
858#define EFX_FEATURE_LINK_EVENTS 0x00000004
859#define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
860#define EFX_FEATURE_WOL 0x00000010
861#define EFX_FEATURE_MCDI 0x00000020
862#define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
863#define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
864
865typedef struct efx_nic_cfg_s {
866 uint32_t enc_board_type;
867 uint32_t enc_phy_type;
868#if EFSYS_OPT_NAMES
869 char enc_phy_name[21];
870#endif
871 char enc_phy_revision[21];
872 efx_mon_type_t enc_mon_type;
873#if EFSYS_OPT_MON_STATS
874 uint32_t enc_mon_stat_mask;
875#endif
876 unsigned int enc_features;
877 uint8_t enc_mac_addr[6];
878 uint8_t enc_port;
879 uint32_t enc_evq_limit;
880 uint32_t enc_txq_limit;
881 uint32_t enc_rxq_limit;
882 uint32_t enc_buftbl_limit;
883 uint32_t enc_evq_moderation_max;
884#if EFSYS_OPT_LOOPBACK
885 uint32_t enc_loopback_types[EFX_LINK_NMODES];
886#endif /* EFSYS_OPT_LOOPBACK */
887#if EFSYS_OPT_PHY_FLAGS
888 uint32_t enc_phy_flags_mask;
889#endif /* EFSYS_OPT_PHY_FLAGS */
890#if EFSYS_OPT_PHY_LED_CONTROL
891 uint32_t enc_led_mask;
892#endif /* EFSYS_OPT_PHY_LED_CONTROL */
893#if EFSYS_OPT_PHY_STATS
894 uint64_t enc_phy_stat_mask;
895#endif /* EFSYS_OPT_PHY_STATS */
896#if EFSYS_OPT_PHY_PROPS
897 unsigned int enc_phy_nprops;
898#endif /* EFSYS_OPT_PHY_PROPS */
899#if EFSYS_OPT_SIENA
900 uint8_t enc_siena_channel;
901#if EFSYS_OPT_PHY_STATS
902 uint32_t enc_siena_phy_stat_mask;
903#endif /* EFSYS_OPT_PHY_STATS */
904#if EFSYS_OPT_MON_STATS
905 uint32_t enc_siena_mon_stat_mask;
906#endif /* EFSYS_OPT_MON_STATS */
907#endif /* EFSYS_OPT_SIENA */
908#if EFSYS_OPT_PHY_BIST
909 uint32_t enc_bist_mask;
910#endif /* EFSYS_OPT_PHY_BIST */
911} efx_nic_cfg_t;
912
913extern const efx_nic_cfg_t *
914efx_nic_cfg_get(
915 __in efx_nic_t *enp);
916
917#if EFSYS_OPT_VPD
918
919typedef enum efx_vpd_tag_e {
920 EFX_VPD_ID = 0x02,
921 EFX_VPD_END = 0x0f,
922 EFX_VPD_RO = 0x10,
923 EFX_VPD_RW = 0x11,
924} efx_vpd_tag_t;
925
926typedef uint16_t efx_vpd_keyword_t;
927
928typedef struct efx_vpd_value_s {
929 efx_vpd_tag_t evv_tag;
930 efx_vpd_keyword_t evv_keyword;
931 uint8_t evv_length;
932 uint8_t evv_value[0x100];
933} efx_vpd_value_t;
934
935
936#define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
937
938extern __checkReturn int
939efx_vpd_init(
940 __in efx_nic_t *enp);
941
942extern __checkReturn int
943efx_vpd_size(
944 __in efx_nic_t *enp,
945 __out size_t *sizep);
946
947extern __checkReturn int
948efx_vpd_read(
949 __in efx_nic_t *enp,
950 __out_bcount(size) caddr_t data,
951 __in size_t size);
952
953extern __checkReturn int
954efx_vpd_verify(
955 __in efx_nic_t *enp,
956 __in_bcount(size) caddr_t data,
957 __in size_t size);
958
959extern __checkReturn int
960efx_vpd_reinit(
961 __in efx_nic_t *enp,
962 __in_bcount(size) caddr_t data,
963 __in size_t size);
964
965extern __checkReturn int
966efx_vpd_get(
967 __in efx_nic_t *enp,
968 __in_bcount(size) caddr_t data,
969 __in size_t size,
970 __inout efx_vpd_value_t *evvp);
971
972extern __checkReturn int
973efx_vpd_set(
974 __in efx_nic_t *enp,
975 __inout_bcount(size) caddr_t data,
976 __in size_t size,
977 __in efx_vpd_value_t *evvp);
978
979extern __checkReturn int
980efx_vpd_next(
981 __in efx_nic_t *enp,
982 __inout_bcount(size) caddr_t data,
983 __in size_t size,
984 __out efx_vpd_value_t *evvp,
985 __inout unsigned int *contp);
986
987extern __checkReturn int
988efx_vpd_write(
989 __in efx_nic_t *enp,
990 __in_bcount(size) caddr_t data,
991 __in size_t size);
992
993extern void
994efx_vpd_fini(
995 __in efx_nic_t *enp);
996
997#endif /* EFSYS_OPT_VPD */
998
999/* NVRAM */
1000
1001#if EFSYS_OPT_NVRAM
1002
1003typedef enum efx_nvram_type_e {
1004 EFX_NVRAM_INVALID = 0,
1005 EFX_NVRAM_BOOTROM,
1006 EFX_NVRAM_BOOTROM_CFG,
1007 EFX_NVRAM_MC_FIRMWARE,
1008 EFX_NVRAM_MC_GOLDEN,
1009 EFX_NVRAM_PHY,
1010 EFX_NVRAM_NULLPHY,
1011 EFX_NVRAM_NTYPES,
1012} efx_nvram_type_t;
1013
1014extern __checkReturn int
1015efx_nvram_init(
1016 __in efx_nic_t *enp);
1017
1018#if EFSYS_OPT_DIAG
1019
1020extern __checkReturn int
1021efx_nvram_test(
1022 __in efx_nic_t *enp);
1023
1024#endif /* EFSYS_OPT_DIAG */
1025
1026extern __checkReturn int
1027efx_nvram_size(
1028 __in efx_nic_t *enp,
1029 __in efx_nvram_type_t type,
1030 __out size_t *sizep);
1031
1032extern __checkReturn int
1033efx_nvram_rw_start(
1034 __in efx_nic_t *enp,
1035 __in efx_nvram_type_t type,
1036 __out_opt size_t *pref_chunkp);
1037
1038extern void
1039efx_nvram_rw_finish(
1040 __in efx_nic_t *enp,
1041 __in efx_nvram_type_t type);
1042
1043extern __checkReturn int
1044efx_nvram_get_version(
1045 __in efx_nic_t *enp,
1046 __in efx_nvram_type_t type,
1047 __out uint32_t *subtypep,
1048 __out_ecount(4) uint16_t version[4]);
1049
1050extern __checkReturn int
1051efx_nvram_read_chunk(
1052 __in efx_nic_t *enp,
1053 __in efx_nvram_type_t type,
1054 __in unsigned int offset,
1055 __out_bcount(size) caddr_t data,
1056 __in size_t size);
1057
1058extern __checkReturn int
1059efx_nvram_set_version(
1060 __in efx_nic_t *enp,
1061 __in efx_nvram_type_t type,
1062 __out uint16_t version[4]);
1063
1064extern __checkReturn int
1065efx_nvram_erase(
1066 __in efx_nic_t *enp,
1067 __in efx_nvram_type_t type);
1068
1069extern __checkReturn int
1070efx_nvram_write_chunk(
1071 __in efx_nic_t *enp,
1072 __in efx_nvram_type_t type,
1073 __in unsigned int offset,
1074 __in_bcount(size) caddr_t data,
1075 __in size_t size);
1076
1077extern void
1078efx_nvram_fini(
1079 __in efx_nic_t *enp);
1080
1081#endif /* EFSYS_OPT_NVRAM */
1082
1083#if EFSYS_OPT_BOOTCFG
1084
1085extern int
1086efx_bootcfg_read(
1087 __in efx_nic_t *enp,
1088 __out_bcount(size) caddr_t data,
1089 __in size_t size);
1090
1091extern int
1092efx_bootcfg_write(
1093 __in efx_nic_t *enp,
1094 __in_bcount(size) caddr_t data,
1095 __in size_t size);
1096
1097#endif /* EFSYS_OPT_BOOTCFG */
1098
1099#if EFSYS_OPT_WOL
1100
1101typedef enum efx_wol_type_e {
1102 EFX_WOL_TYPE_INVALID,
1103 EFX_WOL_TYPE_MAGIC,
1104 EFX_WOL_TYPE_BITMAP,
1105 EFX_WOL_TYPE_LINK,
1106 EFX_WOL_NTYPES,
1107} efx_wol_type_t;
1108
1109typedef enum efx_lightsout_offload_type_e {
1110 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1111 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1112 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1113} efx_lightsout_offload_type_t;
1114
1115#define EFX_WOL_BITMAP_MASK_SIZE (48)
1116#define EFX_WOL_BITMAP_VALUE_SIZE (128)
1117
1118typedef union efx_wol_param_u {
1119 struct {
1120 uint8_t mac_addr[6];
1121 } ewp_magic;
1122 struct {
1123 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */
1124 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1125 uint8_t value_len;
1126 } ewp_bitmap;
1127} efx_wol_param_t;
1128
1129typedef union efx_lightsout_offload_param_u {
1130 struct {
1131 uint8_t mac_addr[6];
1132 uint32_t ip;
1133 } elop_arp;
1134 struct {
1135 uint8_t mac_addr[6];
1136 uint32_t solicited_node[4];
1137 uint32_t ip[4];
1138 } elop_ns;
1139} efx_lightsout_offload_param_t;
1140
1141extern __checkReturn int
1142efx_wol_init(
1143 __in efx_nic_t *enp);
1144
1145extern __checkReturn int
1146efx_wol_filter_clear(
1147 __in efx_nic_t *enp);
1148
1149extern __checkReturn int
1150efx_wol_filter_add(
1151 __in efx_nic_t *enp,
1152 __in efx_wol_type_t type,
1153 __in efx_wol_param_t *paramp,
1154 __out uint32_t *filter_idp);
1155
1156extern __checkReturn int
1157efx_wol_filter_remove(
1158 __in efx_nic_t *enp,
1159 __in uint32_t filter_id);
1160
1161extern __checkReturn int
1162efx_lightsout_offload_add(
1163 __in efx_nic_t *enp,
1164 __in efx_lightsout_offload_type_t type,
1165 __in efx_lightsout_offload_param_t *paramp,
1166 __out uint32_t *filter_idp);
1167
1168extern __checkReturn int
1169efx_lightsout_offload_remove(
1170 __in efx_nic_t *enp,
1171 __in efx_lightsout_offload_type_t type,
1172 __in uint32_t filter_id);
1173
1174extern void
1175efx_wol_fini(
1176 __in efx_nic_t *enp);
1177
1178#endif /* EFSYS_OPT_WOL */
1179
1180#if EFSYS_OPT_DIAG
1181
1182typedef enum efx_pattern_type_t {
1183 EFX_PATTERN_BYTE_INCREMENT = 0,
1184 EFX_PATTERN_ALL_THE_SAME,
1185 EFX_PATTERN_BIT_ALTERNATE,
1186 EFX_PATTERN_BYTE_ALTERNATE,
1187 EFX_PATTERN_BYTE_CHANGING,
1188 EFX_PATTERN_BIT_SWEEP,
1189 EFX_PATTERN_NTYPES
1190} efx_pattern_type_t;
1191
1192typedef void
1193(*efx_sram_pattern_fn_t)(
1194 __in size_t row,
1195 __in boolean_t negate,
1196 __out efx_qword_t *eqp);
1197
1198extern __checkReturn int
1199efx_sram_test(
1200 __in efx_nic_t *enp,
1201 __in efx_pattern_type_t type);
1202
1203#endif /* EFSYS_OPT_DIAG */
1204
1205extern __checkReturn int
1206efx_sram_buf_tbl_set(
1207 __in efx_nic_t *enp,
1208 __in uint32_t id,
1209 __in efsys_mem_t *esmp,
1210 __in size_t n);
1211
1212extern void
1213efx_sram_buf_tbl_clear(
1214 __in efx_nic_t *enp,
1215 __in uint32_t id,
1216 __in size_t n);
1217
1218#define EFX_BUF_TBL_SIZE 0x20000
1219
1220#define EFX_BUF_SIZE 4096
1221
1222/* EV */
1223
1224typedef struct efx_evq_s efx_evq_t;
1225
1226#if EFSYS_OPT_QSTATS
1227
1228/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock d5614a5d669c8ca3 */
1229typedef enum efx_ev_qstat_e {
1230 EV_ALL,
1231 EV_RX,
1232 EV_RX_OK,
1233 EV_RX_RECOVERY,
1234 EV_RX_FRM_TRUNC,
1235 EV_RX_TOBE_DISC,
1236 EV_RX_PAUSE_FRM_ERR,
1237 EV_RX_BUF_OWNER_ID_ERR,
1238 EV_RX_IPV4_HDR_CHKSUM_ERR,
1239 EV_RX_TCP_UDP_CHKSUM_ERR,
1240 EV_RX_ETH_CRC_ERR,
1241 EV_RX_IP_FRAG_ERR,
1242 EV_RX_MCAST_PKT,
1243 EV_RX_MCAST_HASH_MATCH,
1244 EV_RX_TCP_IPV4,
1245 EV_RX_TCP_IPV6,
1246 EV_RX_UDP_IPV4,
1247 EV_RX_UDP_IPV6,
1248 EV_RX_OTHER_IPV4,
1249 EV_RX_OTHER_IPV6,
1250 EV_RX_NON_IP,
1251 EV_RX_OVERRUN,
1252 EV_TX,
1253 EV_TX_WQ_FF_FULL,
1254 EV_TX_PKT_ERR,
1255 EV_TX_PKT_TOO_BIG,
1256 EV_TX_UNEXPECTED,
1257 EV_GLOBAL,
1258 EV_GLOBAL_PHY,
1259 EV_GLOBAL_MNT,
1260 EV_GLOBAL_RX_RECOVERY,
1261 EV_DRIVER,
1262 EV_DRIVER_SRM_UPD_DONE,
1263 EV_DRIVER_TX_DESCQ_FLS_DONE,
1264 EV_DRIVER_RX_DESCQ_FLS_DONE,
1265 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1266 EV_DRIVER_RX_DSC_ERROR,
1267 EV_DRIVER_TX_DSC_ERROR,
1268 EV_DRV_GEN,
1269 EV_MCDI_RESPONSE,
1270 EV_NQSTATS
1271} efx_ev_qstat_t;
1272
1273/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1274
1275#endif /* EFSYS_OPT_QSTATS */
1276
1277extern __checkReturn int
1278efx_ev_init(
1279 __in efx_nic_t *enp);
1280
1281extern void
1282efx_ev_fini(
1283 __in efx_nic_t *enp);
1284
1285#define EFX_MASK(_max, _min) (-((_max) << 1) ^ -(_min))
1286
1287#define EFX_EVQ_MAXNEVS 32768
1288#define EFX_EVQ_MINNEVS 512
1289
1290#define EFX_EVQ_NEVS_MASK EFX_MASK(EFX_EVQ_MAXNEVS, EFX_EVQ_MINNEVS)
1291
1292#define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1293#define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1294
1295extern __checkReturn int
1296efx_ev_qcreate(
1297 __in efx_nic_t *enp,
1298 __in unsigned int index,
1299 __in efsys_mem_t *esmp,
1300 __in size_t n,
1301 __in uint32_t id,
1302 __deref_out efx_evq_t **eepp);
1303
1304extern void
1305efx_ev_qpost(
1306 __in efx_evq_t *eep,
1307 __in uint16_t data);
1308
1309typedef __checkReturn boolean_t
1310(*efx_initialized_ev_t)(
1311 __in_opt void *arg);
1312
1313#define EFX_PKT_UNICAST 0x0004
1314#define EFX_PKT_START 0x0008
1315
1316#define EFX_PKT_VLAN_TAGGED 0x0010
1317#define EFX_CKSUM_TCPUDP 0x0020
1318#define EFX_CKSUM_IPV4 0x0040
1319#define EFX_PKT_CONT 0x0080
1320
1321#define EFX_CHECK_VLAN 0x0100
1322#define EFX_PKT_TCP 0x0200
1323#define EFX_PKT_UDP 0x0400
1324#define EFX_PKT_IPV4 0x0800
1325
1326#define EFX_PKT_IPV6 0x1000
1327#define EFX_ADDR_MISMATCH 0x4000
1328#define EFX_DISCARD 0x8000
1329
1330#define EFX_EV_RX_NLABELS 32
1331#define EFX_EV_TX_NLABELS 32
1332
1333typedef __checkReturn boolean_t
1334(*efx_rx_ev_t)(
1335 __in_opt void *arg,
1336 __in uint32_t label,
1337 __in uint32_t id,
1338 __in uint32_t size,
1339 __in uint16_t flags);
1340
1341typedef __checkReturn boolean_t
1342(*efx_tx_ev_t)(
1343 __in_opt void *arg,
1344 __in uint32_t label,
1345 __in uint32_t id);
1346
1347#define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1348#define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1349#define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1350#define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1351#define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1352#define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1353
1354typedef __checkReturn boolean_t
1355(*efx_exception_ev_t)(
1356 __in_opt void *arg,
1357 __in uint32_t label,
1358 __in uint32_t data);
1359
1360typedef __checkReturn boolean_t
1361(*efx_rxq_flush_done_ev_t)(
1362 __in_opt void *arg,
| 26 */
27
28#ifndef _SYS_EFX_H
29#define _SYS_EFX_H
30
31#include "efsys.h"
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
37#define EFX_STATIC_ASSERT(_cond) ((void)sizeof(char[(_cond) ? 1 : -1]))
38
39#define EFX_ARRAY_SIZE(_array) (sizeof(_array) / sizeof((_array)[0]))
40
41#ifndef EFSYS_MEM_IS_NULL
42#define EFSYS_MEM_IS_NULL(_esmp) ((_esmp)->esm_base == NULL)
43#endif
44
45typedef enum efx_family_e {
46 EFX_FAMILY_INVALID,
47 EFX_FAMILY_FALCON,
48 EFX_FAMILY_SIENA,
49 EFX_FAMILY_NTYPES
50} efx_family_t;
51
52extern __checkReturn int
53efx_family(
54 __in uint16_t venid,
55 __in uint16_t devid,
56 __out efx_family_t *efp);
57
58extern __checkReturn int
59efx_infer_family(
60 __in efsys_bar_t *esbp,
61 __out efx_family_t *efp);
62
63#define EFX_PCI_VENID_SFC 0x1924
64#define EFX_PCI_DEVID_FALCON 0x0710
65#define EFX_PCI_DEVID_BETHPAGE 0x0803
66#define EFX_PCI_DEVID_SIENA 0x0813
67#define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
68
69#define EFX_MEM_BAR 2
70
71/* Error codes */
72
73enum {
74 EFX_ERR_INVALID,
75 EFX_ERR_SRAM_OOB,
76 EFX_ERR_BUFID_DC_OOB,
77 EFX_ERR_MEM_PERR,
78 EFX_ERR_RBUF_OWN,
79 EFX_ERR_TBUF_OWN,
80 EFX_ERR_RDESQ_OWN,
81 EFX_ERR_TDESQ_OWN,
82 EFX_ERR_EVQ_OWN,
83 EFX_ERR_EVFF_OFLO,
84 EFX_ERR_ILL_ADDR,
85 EFX_ERR_SRAM_PERR,
86 EFX_ERR_NCODES
87};
88
89/* NIC */
90
91typedef struct efx_nic_s efx_nic_t;
92
93extern __checkReturn int
94efx_nic_create(
95 __in efx_family_t family,
96 __in efsys_identifier_t *esip,
97 __in efsys_bar_t *esbp,
98 __in efsys_lock_t *eslp,
99 __deref_out efx_nic_t **enpp);
100
101extern __checkReturn int
102efx_nic_probe(
103 __in efx_nic_t *enp);
104
105#if EFSYS_OPT_PCIE_TUNE
106
107extern __checkReturn int
108efx_nic_pcie_tune(
109 __in efx_nic_t *enp,
110 unsigned int nlanes);
111
112extern __checkReturn int
113efx_nic_pcie_extended_sync(
114 __in efx_nic_t *enp);
115
116#endif /* EFSYS_OPT_PCIE_TUNE */
117
118extern __checkReturn int
119efx_nic_init(
120 __in efx_nic_t *enp);
121
122extern __checkReturn int
123efx_nic_reset(
124 __in efx_nic_t *enp);
125
126#if EFSYS_OPT_DIAG
127
128extern __checkReturn int
129efx_nic_register_test(
130 __in efx_nic_t *enp);
131
132#endif /* EFSYS_OPT_DIAG */
133
134extern void
135efx_nic_fini(
136 __in efx_nic_t *enp);
137
138extern void
139efx_nic_unprobe(
140 __in efx_nic_t *enp);
141
142extern void
143efx_nic_destroy(
144 __in efx_nic_t *enp);
145
146#if EFSYS_OPT_MCDI
147
148typedef struct efx_mcdi_req_s efx_mcdi_req_t;
149
150typedef enum efx_mcdi_exception_e {
151 EFX_MCDI_EXCEPTION_MC_REBOOT,
152 EFX_MCDI_EXCEPTION_MC_BADASSERT,
153} efx_mcdi_exception_t;
154
155typedef struct efx_mcdi_transport_s {
156 void *emt_context;
157 void (*emt_execute)(void *, efx_mcdi_req_t *);
158 void (*emt_ev_cpl)(void *);
159 void (*emt_exception)(void *, efx_mcdi_exception_t);
160} efx_mcdi_transport_t;
161
162extern __checkReturn int
163efx_mcdi_init(
164 __in efx_nic_t *enp,
165 __in const efx_mcdi_transport_t *mtp);
166
167extern __checkReturn int
168efx_mcdi_reboot(
169 __in efx_nic_t *enp);
170
171extern void
172efx_mcdi_request_start(
173 __in efx_nic_t *enp,
174 __in efx_mcdi_req_t *emrp,
175 __in boolean_t ev_cpl);
176
177extern __checkReturn boolean_t
178efx_mcdi_request_poll(
179 __in efx_nic_t *enp);
180
181extern __checkReturn boolean_t
182efx_mcdi_request_abort(
183 __in efx_nic_t *enp);
184
185extern void
186efx_mcdi_fini(
187 __in efx_nic_t *enp);
188
189#endif /* EFSYS_OPT_MCDI */
190
191/* INTR */
192
193#define EFX_NINTR_FALCON 64
194#define EFX_NINTR_SIENA 1024
195
196typedef enum efx_intr_type_e {
197 EFX_INTR_INVALID = 0,
198 EFX_INTR_LINE,
199 EFX_INTR_MESSAGE,
200 EFX_INTR_NTYPES
201} efx_intr_type_t;
202
203#define EFX_INTR_SIZE (sizeof (efx_oword_t))
204
205extern __checkReturn int
206efx_intr_init(
207 __in efx_nic_t *enp,
208 __in efx_intr_type_t type,
209 __in efsys_mem_t *esmp);
210
211extern void
212efx_intr_enable(
213 __in efx_nic_t *enp);
214
215extern void
216efx_intr_disable(
217 __in efx_nic_t *enp);
218
219extern void
220efx_intr_disable_unlocked(
221 __in efx_nic_t *enp);
222
223#define EFX_INTR_NEVQS 32
224
225extern __checkReturn int
226efx_intr_trigger(
227 __in efx_nic_t *enp,
228 __in unsigned int level);
229
230extern void
231efx_intr_status_line(
232 __in efx_nic_t *enp,
233 __out boolean_t *fatalp,
234 __out uint32_t *maskp);
235
236extern void
237efx_intr_status_message(
238 __in efx_nic_t *enp,
239 __in unsigned int message,
240 __out boolean_t *fatalp);
241
242extern void
243efx_intr_fatal(
244 __in efx_nic_t *enp);
245
246extern void
247efx_intr_fini(
248 __in efx_nic_t *enp);
249
250/* MAC */
251
252#if EFSYS_OPT_MAC_STATS
253
254/* START MKCONFIG GENERATED EfxHeaderMacBlock bb8d39428b6fdcf5 */
255typedef enum efx_mac_stat_e {
256 EFX_MAC_RX_OCTETS,
257 EFX_MAC_RX_PKTS,
258 EFX_MAC_RX_UNICST_PKTS,
259 EFX_MAC_RX_MULTICST_PKTS,
260 EFX_MAC_RX_BRDCST_PKTS,
261 EFX_MAC_RX_PAUSE_PKTS,
262 EFX_MAC_RX_LE_64_PKTS,
263 EFX_MAC_RX_65_TO_127_PKTS,
264 EFX_MAC_RX_128_TO_255_PKTS,
265 EFX_MAC_RX_256_TO_511_PKTS,
266 EFX_MAC_RX_512_TO_1023_PKTS,
267 EFX_MAC_RX_1024_TO_15XX_PKTS,
268 EFX_MAC_RX_GE_15XX_PKTS,
269 EFX_MAC_RX_ERRORS,
270 EFX_MAC_RX_FCS_ERRORS,
271 EFX_MAC_RX_DROP_EVENTS,
272 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
273 EFX_MAC_RX_SYMBOL_ERRORS,
274 EFX_MAC_RX_ALIGN_ERRORS,
275 EFX_MAC_RX_INTERNAL_ERRORS,
276 EFX_MAC_RX_JABBER_PKTS,
277 EFX_MAC_RX_LANE0_CHAR_ERR,
278 EFX_MAC_RX_LANE1_CHAR_ERR,
279 EFX_MAC_RX_LANE2_CHAR_ERR,
280 EFX_MAC_RX_LANE3_CHAR_ERR,
281 EFX_MAC_RX_LANE0_DISP_ERR,
282 EFX_MAC_RX_LANE1_DISP_ERR,
283 EFX_MAC_RX_LANE2_DISP_ERR,
284 EFX_MAC_RX_LANE3_DISP_ERR,
285 EFX_MAC_RX_MATCH_FAULT,
286 EFX_MAC_RX_NODESC_DROP_CNT,
287 EFX_MAC_TX_OCTETS,
288 EFX_MAC_TX_PKTS,
289 EFX_MAC_TX_UNICST_PKTS,
290 EFX_MAC_TX_MULTICST_PKTS,
291 EFX_MAC_TX_BRDCST_PKTS,
292 EFX_MAC_TX_PAUSE_PKTS,
293 EFX_MAC_TX_LE_64_PKTS,
294 EFX_MAC_TX_65_TO_127_PKTS,
295 EFX_MAC_TX_128_TO_255_PKTS,
296 EFX_MAC_TX_256_TO_511_PKTS,
297 EFX_MAC_TX_512_TO_1023_PKTS,
298 EFX_MAC_TX_1024_TO_15XX_PKTS,
299 EFX_MAC_TX_GE_15XX_PKTS,
300 EFX_MAC_TX_ERRORS,
301 EFX_MAC_TX_SGL_COL_PKTS,
302 EFX_MAC_TX_MULT_COL_PKTS,
303 EFX_MAC_TX_EX_COL_PKTS,
304 EFX_MAC_TX_LATE_COL_PKTS,
305 EFX_MAC_TX_DEF_PKTS,
306 EFX_MAC_TX_EX_DEF_PKTS,
307 EFX_MAC_NSTATS
308} efx_mac_stat_t;
309
310/* END MKCONFIG GENERATED EfxHeaderMacBlock */
311
312#endif /* EFSYS_OPT_MAC_STATS */
313
314typedef enum efx_link_mode_e {
315 EFX_LINK_UNKNOWN = 0,
316 EFX_LINK_DOWN,
317 EFX_LINK_10HDX,
318 EFX_LINK_10FDX,
319 EFX_LINK_100HDX,
320 EFX_LINK_100FDX,
321 EFX_LINK_1000HDX,
322 EFX_LINK_1000FDX,
323 EFX_LINK_10000FDX,
324 EFX_LINK_NMODES
325} efx_link_mode_t;
326
327#define EFX_MAC_SDU_MAX 9202
328
329#define EFX_MAC_PDU(_sdu) \
330 P2ROUNDUP(((_sdu) \
331 + /* EtherII */ 14 \
332 + /* VLAN */ 4 \
333 + /* CRC */ 4 \
334 + /* bug16011 */ 16), \
335 (1 << 3))
336
337#define EFX_MAC_PDU_MIN 60
338#define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
339
340extern __checkReturn int
341efx_mac_pdu_set(
342 __in efx_nic_t *enp,
343 __in size_t pdu);
344
345extern __checkReturn int
346efx_mac_addr_set(
347 __in efx_nic_t *enp,
348 __in uint8_t *addr);
349
350extern __checkReturn int
351efx_mac_filter_set(
352 __in efx_nic_t *enp,
353 __in boolean_t unicst,
354 __in boolean_t brdcst);
355
356extern __checkReturn int
357efx_mac_drain(
358 __in efx_nic_t *enp,
359 __in boolean_t enabled);
360
361extern __checkReturn int
362efx_mac_up(
363 __in efx_nic_t *enp,
364 __out boolean_t *mac_upp);
365
366#define EFX_FCNTL_RESPOND 0x00000001
367#define EFX_FCNTL_GENERATE 0x00000002
368
369extern __checkReturn int
370efx_mac_fcntl_set(
371 __in efx_nic_t *enp,
372 __in unsigned int fcntl,
373 __in boolean_t autoneg);
374
375extern void
376efx_mac_fcntl_get(
377 __in efx_nic_t *enp,
378 __out unsigned int *fcntl_wantedp,
379 __out unsigned int *fcntl_linkp);
380
381#define EFX_MAC_HASH_BITS (1 << 8)
382
383extern __checkReturn int
384efx_mac_hash_set(
385 __in efx_nic_t *enp,
386 __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket);
387
388#if EFSYS_OPT_MAC_STATS
389
390#if EFSYS_OPT_NAMES
391
392extern __checkReturn const char __cs *
393efx_mac_stat_name(
394 __in efx_nic_t *enp,
395 __in unsigned int id);
396
397#endif /* EFSYS_OPT_NAMES */
398
399#define EFX_MAC_STATS_SIZE 0x400
400
401/*
402 * Upload mac statistics supported by the hardware into the given buffer.
403 *
404 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
405 * and page aligned.
406 *
407 * The hardware will only DMA statistics that it understands (of course).
408 * Drivers should not make any assumptions about which statistics are
409 * supported, especially when the statistics are generated by firmware.
410 *
411 * Thus, drivers should zero this buffer before use, so that not-understood
412 * statistics read back as zero.
413 */
414extern __checkReturn int
415efx_mac_stats_upload(
416 __in efx_nic_t *enp,
417 __in efsys_mem_t *esmp);
418
419extern __checkReturn int
420efx_mac_stats_periodic(
421 __in efx_nic_t *enp,
422 __in efsys_mem_t *esmp,
423 __in uint16_t period_ms,
424 __in boolean_t events);
425
426extern __checkReturn int
427efx_mac_stats_update(
428 __in efx_nic_t *enp,
429 __in efsys_mem_t *esmp,
430 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
431 __out_opt uint32_t *generationp);
432
433#endif /* EFSYS_OPT_MAC_STATS */
434
435/* MON */
436
437typedef enum efx_mon_type_e {
438 EFX_MON_INVALID = 0,
439 EFX_MON_NULL,
440 EFX_MON_LM87,
441 EFX_MON_MAX6647,
442 EFX_MON_SFC90X0,
443 EFX_MON_NTYPES
444} efx_mon_type_t;
445
446#if EFSYS_OPT_NAMES
447
448extern const char __cs *
449efx_mon_name(
450 __in efx_nic_t *enp);
451
452#endif /* EFSYS_OPT_NAMES */
453
454extern __checkReturn int
455efx_mon_init(
456 __in efx_nic_t *enp);
457
458#if EFSYS_OPT_MON_STATS
459
460#define EFX_MON_STATS_SIZE 0x100
461
462/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 16a14e61aa4f8d80 */
463typedef enum efx_mon_stat_e {
464 EFX_MON_STAT_2_5V,
465 EFX_MON_STAT_VCCP1,
466 EFX_MON_STAT_VCC,
467 EFX_MON_STAT_5V,
468 EFX_MON_STAT_12V,
469 EFX_MON_STAT_VCCP2,
470 EFX_MON_STAT_EXT_TEMP,
471 EFX_MON_STAT_INT_TEMP,
472 EFX_MON_STAT_AIN1,
473 EFX_MON_STAT_AIN2,
474 EFX_MON_STAT_INT_COOLING,
475 EFX_MON_STAT_EXT_COOLING,
476 EFX_MON_STAT_1V,
477 EFX_MON_STAT_1_2V,
478 EFX_MON_STAT_1_8V,
479 EFX_MON_STAT_3_3V,
480 EFX_MON_NSTATS
481} efx_mon_stat_t;
482
483/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
484
485typedef enum efx_mon_stat_state_e {
486 EFX_MON_STAT_STATE_OK = 0,
487 EFX_MON_STAT_STATE_WARNING = 1,
488 EFX_MON_STAT_STATE_FATAL = 2,
489 EFX_MON_STAT_STATE_BROKEN = 3,
490} efx_mon_stat_state_t;
491
492typedef struct efx_mon_stat_value_t {
493 uint16_t emsv_value;
494 uint16_t emsv_state;
495} efx_mon_stat_value_t;
496
497#if EFSYS_OPT_NAMES
498
499extern const char __cs *
500efx_mon_stat_name(
501 __in efx_nic_t *enp,
502 __in efx_mon_stat_t id);
503
504#endif /* EFSYS_OPT_NAMES */
505
506extern __checkReturn int
507efx_mon_stats_update(
508 __in efx_nic_t *enp,
509 __in efsys_mem_t *esmp,
510 __out_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
511
512#endif /* EFSYS_OPT_MON_STATS */
513
514extern void
515efx_mon_fini(
516 __in efx_nic_t *enp);
517
518/* PHY */
519
520#define PMA_PMD_MMD 1
521#define PCS_MMD 3
522#define PHY_XS_MMD 4
523#define DTE_XS_MMD 5
524#define AN_MMD 7
525#define CL22EXT_MMD 29
526
527#define MAXMMD ((1 << 5) - 1)
528
529/* PHY types */
530#define EFX_PHY_NULL 0x0
531#define EFX_PHY_TXC43128 0x1
532#define EFX_PHY_SFX7101 0x3
533#define EFX_PHY_QT2022C2 0x4
534#define EFX_PHY_SFT9001A 0x8
535#define EFX_PHY_QT2025C 0x9
536#define EFX_PHY_SFT9001B 0xa
537#define EFX_PHY_QLX111V 0xc
538
539extern __checkReturn int
540efx_phy_verify(
541 __in efx_nic_t *enp);
542
543#if EFSYS_OPT_PHY_LED_CONTROL
544
545typedef enum efx_phy_led_mode_e {
546 EFX_PHY_LED_DEFAULT = 0,
547 EFX_PHY_LED_OFF,
548 EFX_PHY_LED_ON,
549 EFX_PHY_LED_FLASH,
550 EFX_PHY_LED_NMODES
551} efx_phy_led_mode_t;
552
553extern __checkReturn int
554efx_phy_led_set(
555 __in efx_nic_t *enp,
556 __in efx_phy_led_mode_t mode);
557
558#endif /* EFSYS_OPT_PHY_LED_CONTROL */
559
560extern __checkReturn int
561efx_port_init(
562 __in efx_nic_t *enp);
563
564#if EFSYS_OPT_LOOPBACK
565
566typedef enum efx_loopback_type_e {
567 EFX_LOOPBACK_OFF = 0,
568 EFX_LOOPBACK_DATA = 1,
569 EFX_LOOPBACK_GMAC = 2,
570 EFX_LOOPBACK_XGMII = 3,
571 EFX_LOOPBACK_XGXS = 4,
572 EFX_LOOPBACK_XAUI = 5,
573 EFX_LOOPBACK_GMII = 6,
574 EFX_LOOPBACK_SGMII = 7,
575 EFX_LOOPBACK_XGBR = 8,
576 EFX_LOOPBACK_XFI = 9,
577 EFX_LOOPBACK_XAUI_FAR = 10,
578 EFX_LOOPBACK_GMII_FAR = 11,
579 EFX_LOOPBACK_SGMII_FAR = 12,
580 EFX_LOOPBACK_XFI_FAR = 13,
581 EFX_LOOPBACK_GPHY = 14,
582 EFX_LOOPBACK_PHY_XS = 15,
583 EFX_LOOPBACK_PCS = 16,
584 EFX_LOOPBACK_PMA_PMD = 17,
585 EFX_LOOPBACK_NTYPES
586} efx_loopback_type_t;
587
588#define EFX_LOOPBACK_MAC_MASK \
589 ((1 << EFX_LOOPBACK_DATA) | \
590 (1 << EFX_LOOPBACK_GMAC) | \
591 (1 << EFX_LOOPBACK_XGMII) | \
592 (1 << EFX_LOOPBACK_XGXS) | \
593 (1 << EFX_LOOPBACK_XAUI) | \
594 (1 << EFX_LOOPBACK_GMII) | \
595 (1 << EFX_LOOPBACK_SGMII) | \
596 (1 << EFX_LOOPBACK_XGBR) | \
597 (1 << EFX_LOOPBACK_XFI) | \
598 (1 << EFX_LOOPBACK_XAUI_FAR) | \
599 (1 << EFX_LOOPBACK_GMII_FAR) | \
600 (1 << EFX_LOOPBACK_SGMII_FAR) | \
601 (1 << EFX_LOOPBACK_XFI_FAR))
602
603#define EFX_LOOPBACK_MASK \
604 ((1 << EFX_LOOPBACK_NTYPES) - 1)
605
606extern __checkReturn int
607efx_port_loopback_set(
608 __in efx_nic_t *enp,
609 __in efx_link_mode_t link_mode,
610 __in efx_loopback_type_t type);
611
612#if EFSYS_OPT_NAMES
613
614extern __checkReturn const char __cs *
615efx_loopback_type_name(
616 __in efx_nic_t *enp,
617 __in efx_loopback_type_t type);
618
619#endif /* EFSYS_OPT_NAMES */
620
621#endif /* EFSYS_OPT_LOOPBACK */
622
623extern __checkReturn int
624efx_port_poll(
625 __in efx_nic_t *enp,
626 __out efx_link_mode_t *link_modep);
627
628extern void
629efx_port_fini(
630 __in efx_nic_t *enp);
631
632typedef enum efx_phy_cap_type_e {
633 EFX_PHY_CAP_INVALID = 0,
634 EFX_PHY_CAP_10HDX,
635 EFX_PHY_CAP_10FDX,
636 EFX_PHY_CAP_100HDX,
637 EFX_PHY_CAP_100FDX,
638 EFX_PHY_CAP_1000HDX,
639 EFX_PHY_CAP_1000FDX,
640 EFX_PHY_CAP_10000FDX,
641 EFX_PHY_CAP_PAUSE,
642 EFX_PHY_CAP_ASYM,
643 EFX_PHY_CAP_AN,
644 EFX_PHY_CAP_NTYPES
645} efx_phy_cap_type_t;
646
647
648#define EFX_PHY_CAP_CURRENT 0x00000000
649#define EFX_PHY_CAP_DEFAULT 0x00000001
650#define EFX_PHY_CAP_PERM 0x00000002
651
652extern void
653efx_phy_adv_cap_get(
654 __in efx_nic_t *enp,
655 __in uint32_t flag,
656 __out uint32_t *maskp);
657
658extern __checkReturn int
659efx_phy_adv_cap_set(
660 __in efx_nic_t *enp,
661 __in uint32_t mask);
662
663extern void
664efx_phy_lp_cap_get(
665 __in efx_nic_t *enp,
666 __out uint32_t *maskp);
667
668extern __checkReturn int
669efx_phy_oui_get(
670 __in efx_nic_t *enp,
671 __out uint32_t *ouip);
672
673typedef enum efx_phy_media_type_e {
674 EFX_PHY_MEDIA_INVALID = 0,
675 EFX_PHY_MEDIA_XAUI,
676 EFX_PHY_MEDIA_CX4,
677 EFX_PHY_MEDIA_KX4,
678 EFX_PHY_MEDIA_XFP,
679 EFX_PHY_MEDIA_SFP_PLUS,
680 EFX_PHY_MEDIA_BASE_T,
681 EFX_PHY_MEDIA_NTYPES
682} efx_phy_media_type_t;
683
684/* Get the type of medium currently used. If the board has ports for
685 * modules, a module is present, and we recognise the media type of
686 * the module, then this will be the media type of the module.
687 * Otherwise it will be the media type of the port.
688 */
689extern void
690efx_phy_media_type_get(
691 __in efx_nic_t *enp,
692 __out efx_phy_media_type_t *typep);
693
694#if EFSYS_OPT_PHY_STATS
695
696/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
697typedef enum efx_phy_stat_e {
698 EFX_PHY_STAT_OUI,
699 EFX_PHY_STAT_PMA_PMD_LINK_UP,
700 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
701 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
702 EFX_PHY_STAT_PMA_PMD_REV_A,
703 EFX_PHY_STAT_PMA_PMD_REV_B,
704 EFX_PHY_STAT_PMA_PMD_REV_C,
705 EFX_PHY_STAT_PMA_PMD_REV_D,
706 EFX_PHY_STAT_PCS_LINK_UP,
707 EFX_PHY_STAT_PCS_RX_FAULT,
708 EFX_PHY_STAT_PCS_TX_FAULT,
709 EFX_PHY_STAT_PCS_BER,
710 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
711 EFX_PHY_STAT_PHY_XS_LINK_UP,
712 EFX_PHY_STAT_PHY_XS_RX_FAULT,
713 EFX_PHY_STAT_PHY_XS_TX_FAULT,
714 EFX_PHY_STAT_PHY_XS_ALIGN,
715 EFX_PHY_STAT_PHY_XS_SYNC_A,
716 EFX_PHY_STAT_PHY_XS_SYNC_B,
717 EFX_PHY_STAT_PHY_XS_SYNC_C,
718 EFX_PHY_STAT_PHY_XS_SYNC_D,
719 EFX_PHY_STAT_AN_LINK_UP,
720 EFX_PHY_STAT_AN_MASTER,
721 EFX_PHY_STAT_AN_LOCAL_RX_OK,
722 EFX_PHY_STAT_AN_REMOTE_RX_OK,
723 EFX_PHY_STAT_CL22EXT_LINK_UP,
724 EFX_PHY_STAT_SNR_A,
725 EFX_PHY_STAT_SNR_B,
726 EFX_PHY_STAT_SNR_C,
727 EFX_PHY_STAT_SNR_D,
728 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
729 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
730 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
731 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
732 EFX_PHY_STAT_AN_COMPLETE,
733 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
734 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
735 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
736 EFX_PHY_STAT_PCS_FW_VERSION_0,
737 EFX_PHY_STAT_PCS_FW_VERSION_1,
738 EFX_PHY_STAT_PCS_FW_VERSION_2,
739 EFX_PHY_STAT_PCS_FW_VERSION_3,
740 EFX_PHY_STAT_PCS_FW_BUILD_YY,
741 EFX_PHY_STAT_PCS_FW_BUILD_MM,
742 EFX_PHY_STAT_PCS_FW_BUILD_DD,
743 EFX_PHY_STAT_PCS_OP_MODE,
744 EFX_PHY_NSTATS
745} efx_phy_stat_t;
746
747/* END MKCONFIG GENERATED PhyHeaderStatsBlock */
748
749#if EFSYS_OPT_NAMES
750
751extern const char __cs *
752efx_phy_stat_name(
753 __in efx_nic_t *enp,
754 __in efx_phy_stat_t stat);
755
756#endif /* EFSYS_OPT_NAMES */
757
758#define EFX_PHY_STATS_SIZE 0x100
759
760extern __checkReturn int
761efx_phy_stats_update(
762 __in efx_nic_t *enp,
763 __in efsys_mem_t *esmp,
764 __out_ecount(EFX_PHY_NSTATS) uint32_t *stat);
765
766#endif /* EFSYS_OPT_PHY_STATS */
767
768#if EFSYS_OPT_PHY_PROPS
769
770#if EFSYS_OPT_NAMES
771
772extern const char __cs *
773efx_phy_prop_name(
774 __in efx_nic_t *enp,
775 __in unsigned int id);
776
777#endif /* EFSYS_OPT_NAMES */
778
779#define EFX_PHY_PROP_DEFAULT 0x00000001
780
781extern __checkReturn int
782efx_phy_prop_get(
783 __in efx_nic_t *enp,
784 __in unsigned int id,
785 __in uint32_t flags,
786 __out uint32_t *valp);
787
788extern __checkReturn int
789efx_phy_prop_set(
790 __in efx_nic_t *enp,
791 __in unsigned int id,
792 __in uint32_t val);
793
794#endif /* EFSYS_OPT_PHY_PROPS */
795
796#if EFSYS_OPT_PHY_BIST
797
798typedef enum efx_phy_bist_type_e {
799 EFX_PHY_BIST_TYPE_UNKNOWN,
800 EFX_PHY_BIST_TYPE_NORMAL,
801 EFX_PHY_BIST_TYPE_CABLE_SHORT,
802 EFX_PHY_BIST_TYPE_CABLE_LONG,
803 EFX_PHY_BIST_TYPE_NTYPES,
804} efx_phy_bist_type_t;
805
806typedef enum efx_phy_bist_result_e {
807 EFX_PHY_BIST_RESULT_UNKNOWN,
808 EFX_PHY_BIST_RESULT_RUNNING,
809 EFX_PHY_BIST_RESULT_PASSED,
810 EFX_PHY_BIST_RESULT_FAILED,
811} efx_phy_bist_result_t;
812
813typedef enum efx_phy_cable_status_e {
814 EFX_PHY_CABLE_STATUS_OK,
815 EFX_PHY_CABLE_STATUS_INVALID,
816 EFX_PHY_CABLE_STATUS_OPEN,
817 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
818 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
819 EFX_PHY_CABLE_STATUS_BUSY,
820} efx_phy_cable_status_t;
821
822typedef enum efx_phy_bist_value_e {
823 EFX_PHY_BIST_CABLE_LENGTH_A,
824 EFX_PHY_BIST_CABLE_LENGTH_B,
825 EFX_PHY_BIST_CABLE_LENGTH_C,
826 EFX_PHY_BIST_CABLE_LENGTH_D,
827 EFX_PHY_BIST_CABLE_STATUS_A,
828 EFX_PHY_BIST_CABLE_STATUS_B,
829 EFX_PHY_BIST_CABLE_STATUS_C,
830 EFX_PHY_BIST_CABLE_STATUS_D,
831 EFX_PHY_BIST_FAULT_CODE,
832 EFX_PHY_BIST_NVALUES,
833} efx_phy_bist_value_t;
834
835extern __checkReturn int
836efx_phy_bist_start(
837 __in efx_nic_t *enp,
838 __in efx_phy_bist_type_t type);
839
840extern __checkReturn int
841efx_phy_bist_poll(
842 __in efx_nic_t *enp,
843 __in efx_phy_bist_type_t type,
844 __out efx_phy_bist_result_t *resultp,
845 __out_opt uint32_t *value_maskp,
846 __out_ecount_opt(count) unsigned long *valuesp,
847 __in size_t count);
848
849extern void
850efx_phy_bist_stop(
851 __in efx_nic_t *enp,
852 __in efx_phy_bist_type_t type);
853
854#endif /* EFSYS_OPT_PHY_BIST */
855
856#define EFX_FEATURE_IPV6 0x00000001
857#define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
858#define EFX_FEATURE_LINK_EVENTS 0x00000004
859#define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
860#define EFX_FEATURE_WOL 0x00000010
861#define EFX_FEATURE_MCDI 0x00000020
862#define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
863#define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
864
865typedef struct efx_nic_cfg_s {
866 uint32_t enc_board_type;
867 uint32_t enc_phy_type;
868#if EFSYS_OPT_NAMES
869 char enc_phy_name[21];
870#endif
871 char enc_phy_revision[21];
872 efx_mon_type_t enc_mon_type;
873#if EFSYS_OPT_MON_STATS
874 uint32_t enc_mon_stat_mask;
875#endif
876 unsigned int enc_features;
877 uint8_t enc_mac_addr[6];
878 uint8_t enc_port;
879 uint32_t enc_evq_limit;
880 uint32_t enc_txq_limit;
881 uint32_t enc_rxq_limit;
882 uint32_t enc_buftbl_limit;
883 uint32_t enc_evq_moderation_max;
884#if EFSYS_OPT_LOOPBACK
885 uint32_t enc_loopback_types[EFX_LINK_NMODES];
886#endif /* EFSYS_OPT_LOOPBACK */
887#if EFSYS_OPT_PHY_FLAGS
888 uint32_t enc_phy_flags_mask;
889#endif /* EFSYS_OPT_PHY_FLAGS */
890#if EFSYS_OPT_PHY_LED_CONTROL
891 uint32_t enc_led_mask;
892#endif /* EFSYS_OPT_PHY_LED_CONTROL */
893#if EFSYS_OPT_PHY_STATS
894 uint64_t enc_phy_stat_mask;
895#endif /* EFSYS_OPT_PHY_STATS */
896#if EFSYS_OPT_PHY_PROPS
897 unsigned int enc_phy_nprops;
898#endif /* EFSYS_OPT_PHY_PROPS */
899#if EFSYS_OPT_SIENA
900 uint8_t enc_siena_channel;
901#if EFSYS_OPT_PHY_STATS
902 uint32_t enc_siena_phy_stat_mask;
903#endif /* EFSYS_OPT_PHY_STATS */
904#if EFSYS_OPT_MON_STATS
905 uint32_t enc_siena_mon_stat_mask;
906#endif /* EFSYS_OPT_MON_STATS */
907#endif /* EFSYS_OPT_SIENA */
908#if EFSYS_OPT_PHY_BIST
909 uint32_t enc_bist_mask;
910#endif /* EFSYS_OPT_PHY_BIST */
911} efx_nic_cfg_t;
912
913extern const efx_nic_cfg_t *
914efx_nic_cfg_get(
915 __in efx_nic_t *enp);
916
917#if EFSYS_OPT_VPD
918
919typedef enum efx_vpd_tag_e {
920 EFX_VPD_ID = 0x02,
921 EFX_VPD_END = 0x0f,
922 EFX_VPD_RO = 0x10,
923 EFX_VPD_RW = 0x11,
924} efx_vpd_tag_t;
925
926typedef uint16_t efx_vpd_keyword_t;
927
928typedef struct efx_vpd_value_s {
929 efx_vpd_tag_t evv_tag;
930 efx_vpd_keyword_t evv_keyword;
931 uint8_t evv_length;
932 uint8_t evv_value[0x100];
933} efx_vpd_value_t;
934
935
936#define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
937
938extern __checkReturn int
939efx_vpd_init(
940 __in efx_nic_t *enp);
941
942extern __checkReturn int
943efx_vpd_size(
944 __in efx_nic_t *enp,
945 __out size_t *sizep);
946
947extern __checkReturn int
948efx_vpd_read(
949 __in efx_nic_t *enp,
950 __out_bcount(size) caddr_t data,
951 __in size_t size);
952
953extern __checkReturn int
954efx_vpd_verify(
955 __in efx_nic_t *enp,
956 __in_bcount(size) caddr_t data,
957 __in size_t size);
958
959extern __checkReturn int
960efx_vpd_reinit(
961 __in efx_nic_t *enp,
962 __in_bcount(size) caddr_t data,
963 __in size_t size);
964
965extern __checkReturn int
966efx_vpd_get(
967 __in efx_nic_t *enp,
968 __in_bcount(size) caddr_t data,
969 __in size_t size,
970 __inout efx_vpd_value_t *evvp);
971
972extern __checkReturn int
973efx_vpd_set(
974 __in efx_nic_t *enp,
975 __inout_bcount(size) caddr_t data,
976 __in size_t size,
977 __in efx_vpd_value_t *evvp);
978
979extern __checkReturn int
980efx_vpd_next(
981 __in efx_nic_t *enp,
982 __inout_bcount(size) caddr_t data,
983 __in size_t size,
984 __out efx_vpd_value_t *evvp,
985 __inout unsigned int *contp);
986
987extern __checkReturn int
988efx_vpd_write(
989 __in efx_nic_t *enp,
990 __in_bcount(size) caddr_t data,
991 __in size_t size);
992
993extern void
994efx_vpd_fini(
995 __in efx_nic_t *enp);
996
997#endif /* EFSYS_OPT_VPD */
998
999/* NVRAM */
1000
1001#if EFSYS_OPT_NVRAM
1002
1003typedef enum efx_nvram_type_e {
1004 EFX_NVRAM_INVALID = 0,
1005 EFX_NVRAM_BOOTROM,
1006 EFX_NVRAM_BOOTROM_CFG,
1007 EFX_NVRAM_MC_FIRMWARE,
1008 EFX_NVRAM_MC_GOLDEN,
1009 EFX_NVRAM_PHY,
1010 EFX_NVRAM_NULLPHY,
1011 EFX_NVRAM_NTYPES,
1012} efx_nvram_type_t;
1013
1014extern __checkReturn int
1015efx_nvram_init(
1016 __in efx_nic_t *enp);
1017
1018#if EFSYS_OPT_DIAG
1019
1020extern __checkReturn int
1021efx_nvram_test(
1022 __in efx_nic_t *enp);
1023
1024#endif /* EFSYS_OPT_DIAG */
1025
1026extern __checkReturn int
1027efx_nvram_size(
1028 __in efx_nic_t *enp,
1029 __in efx_nvram_type_t type,
1030 __out size_t *sizep);
1031
1032extern __checkReturn int
1033efx_nvram_rw_start(
1034 __in efx_nic_t *enp,
1035 __in efx_nvram_type_t type,
1036 __out_opt size_t *pref_chunkp);
1037
1038extern void
1039efx_nvram_rw_finish(
1040 __in efx_nic_t *enp,
1041 __in efx_nvram_type_t type);
1042
1043extern __checkReturn int
1044efx_nvram_get_version(
1045 __in efx_nic_t *enp,
1046 __in efx_nvram_type_t type,
1047 __out uint32_t *subtypep,
1048 __out_ecount(4) uint16_t version[4]);
1049
1050extern __checkReturn int
1051efx_nvram_read_chunk(
1052 __in efx_nic_t *enp,
1053 __in efx_nvram_type_t type,
1054 __in unsigned int offset,
1055 __out_bcount(size) caddr_t data,
1056 __in size_t size);
1057
1058extern __checkReturn int
1059efx_nvram_set_version(
1060 __in efx_nic_t *enp,
1061 __in efx_nvram_type_t type,
1062 __out uint16_t version[4]);
1063
1064extern __checkReturn int
1065efx_nvram_erase(
1066 __in efx_nic_t *enp,
1067 __in efx_nvram_type_t type);
1068
1069extern __checkReturn int
1070efx_nvram_write_chunk(
1071 __in efx_nic_t *enp,
1072 __in efx_nvram_type_t type,
1073 __in unsigned int offset,
1074 __in_bcount(size) caddr_t data,
1075 __in size_t size);
1076
1077extern void
1078efx_nvram_fini(
1079 __in efx_nic_t *enp);
1080
1081#endif /* EFSYS_OPT_NVRAM */
1082
1083#if EFSYS_OPT_BOOTCFG
1084
1085extern int
1086efx_bootcfg_read(
1087 __in efx_nic_t *enp,
1088 __out_bcount(size) caddr_t data,
1089 __in size_t size);
1090
1091extern int
1092efx_bootcfg_write(
1093 __in efx_nic_t *enp,
1094 __in_bcount(size) caddr_t data,
1095 __in size_t size);
1096
1097#endif /* EFSYS_OPT_BOOTCFG */
1098
1099#if EFSYS_OPT_WOL
1100
1101typedef enum efx_wol_type_e {
1102 EFX_WOL_TYPE_INVALID,
1103 EFX_WOL_TYPE_MAGIC,
1104 EFX_WOL_TYPE_BITMAP,
1105 EFX_WOL_TYPE_LINK,
1106 EFX_WOL_NTYPES,
1107} efx_wol_type_t;
1108
1109typedef enum efx_lightsout_offload_type_e {
1110 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1111 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1112 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1113} efx_lightsout_offload_type_t;
1114
1115#define EFX_WOL_BITMAP_MASK_SIZE (48)
1116#define EFX_WOL_BITMAP_VALUE_SIZE (128)
1117
1118typedef union efx_wol_param_u {
1119 struct {
1120 uint8_t mac_addr[6];
1121 } ewp_magic;
1122 struct {
1123 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */
1124 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1125 uint8_t value_len;
1126 } ewp_bitmap;
1127} efx_wol_param_t;
1128
1129typedef union efx_lightsout_offload_param_u {
1130 struct {
1131 uint8_t mac_addr[6];
1132 uint32_t ip;
1133 } elop_arp;
1134 struct {
1135 uint8_t mac_addr[6];
1136 uint32_t solicited_node[4];
1137 uint32_t ip[4];
1138 } elop_ns;
1139} efx_lightsout_offload_param_t;
1140
1141extern __checkReturn int
1142efx_wol_init(
1143 __in efx_nic_t *enp);
1144
1145extern __checkReturn int
1146efx_wol_filter_clear(
1147 __in efx_nic_t *enp);
1148
1149extern __checkReturn int
1150efx_wol_filter_add(
1151 __in efx_nic_t *enp,
1152 __in efx_wol_type_t type,
1153 __in efx_wol_param_t *paramp,
1154 __out uint32_t *filter_idp);
1155
1156extern __checkReturn int
1157efx_wol_filter_remove(
1158 __in efx_nic_t *enp,
1159 __in uint32_t filter_id);
1160
1161extern __checkReturn int
1162efx_lightsout_offload_add(
1163 __in efx_nic_t *enp,
1164 __in efx_lightsout_offload_type_t type,
1165 __in efx_lightsout_offload_param_t *paramp,
1166 __out uint32_t *filter_idp);
1167
1168extern __checkReturn int
1169efx_lightsout_offload_remove(
1170 __in efx_nic_t *enp,
1171 __in efx_lightsout_offload_type_t type,
1172 __in uint32_t filter_id);
1173
1174extern void
1175efx_wol_fini(
1176 __in efx_nic_t *enp);
1177
1178#endif /* EFSYS_OPT_WOL */
1179
1180#if EFSYS_OPT_DIAG
1181
1182typedef enum efx_pattern_type_t {
1183 EFX_PATTERN_BYTE_INCREMENT = 0,
1184 EFX_PATTERN_ALL_THE_SAME,
1185 EFX_PATTERN_BIT_ALTERNATE,
1186 EFX_PATTERN_BYTE_ALTERNATE,
1187 EFX_PATTERN_BYTE_CHANGING,
1188 EFX_PATTERN_BIT_SWEEP,
1189 EFX_PATTERN_NTYPES
1190} efx_pattern_type_t;
1191
1192typedef void
1193(*efx_sram_pattern_fn_t)(
1194 __in size_t row,
1195 __in boolean_t negate,
1196 __out efx_qword_t *eqp);
1197
1198extern __checkReturn int
1199efx_sram_test(
1200 __in efx_nic_t *enp,
1201 __in efx_pattern_type_t type);
1202
1203#endif /* EFSYS_OPT_DIAG */
1204
1205extern __checkReturn int
1206efx_sram_buf_tbl_set(
1207 __in efx_nic_t *enp,
1208 __in uint32_t id,
1209 __in efsys_mem_t *esmp,
1210 __in size_t n);
1211
1212extern void
1213efx_sram_buf_tbl_clear(
1214 __in efx_nic_t *enp,
1215 __in uint32_t id,
1216 __in size_t n);
1217
1218#define EFX_BUF_TBL_SIZE 0x20000
1219
1220#define EFX_BUF_SIZE 4096
1221
1222/* EV */
1223
1224typedef struct efx_evq_s efx_evq_t;
1225
1226#if EFSYS_OPT_QSTATS
1227
1228/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock d5614a5d669c8ca3 */
1229typedef enum efx_ev_qstat_e {
1230 EV_ALL,
1231 EV_RX,
1232 EV_RX_OK,
1233 EV_RX_RECOVERY,
1234 EV_RX_FRM_TRUNC,
1235 EV_RX_TOBE_DISC,
1236 EV_RX_PAUSE_FRM_ERR,
1237 EV_RX_BUF_OWNER_ID_ERR,
1238 EV_RX_IPV4_HDR_CHKSUM_ERR,
1239 EV_RX_TCP_UDP_CHKSUM_ERR,
1240 EV_RX_ETH_CRC_ERR,
1241 EV_RX_IP_FRAG_ERR,
1242 EV_RX_MCAST_PKT,
1243 EV_RX_MCAST_HASH_MATCH,
1244 EV_RX_TCP_IPV4,
1245 EV_RX_TCP_IPV6,
1246 EV_RX_UDP_IPV4,
1247 EV_RX_UDP_IPV6,
1248 EV_RX_OTHER_IPV4,
1249 EV_RX_OTHER_IPV6,
1250 EV_RX_NON_IP,
1251 EV_RX_OVERRUN,
1252 EV_TX,
1253 EV_TX_WQ_FF_FULL,
1254 EV_TX_PKT_ERR,
1255 EV_TX_PKT_TOO_BIG,
1256 EV_TX_UNEXPECTED,
1257 EV_GLOBAL,
1258 EV_GLOBAL_PHY,
1259 EV_GLOBAL_MNT,
1260 EV_GLOBAL_RX_RECOVERY,
1261 EV_DRIVER,
1262 EV_DRIVER_SRM_UPD_DONE,
1263 EV_DRIVER_TX_DESCQ_FLS_DONE,
1264 EV_DRIVER_RX_DESCQ_FLS_DONE,
1265 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1266 EV_DRIVER_RX_DSC_ERROR,
1267 EV_DRIVER_TX_DSC_ERROR,
1268 EV_DRV_GEN,
1269 EV_MCDI_RESPONSE,
1270 EV_NQSTATS
1271} efx_ev_qstat_t;
1272
1273/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1274
1275#endif /* EFSYS_OPT_QSTATS */
1276
1277extern __checkReturn int
1278efx_ev_init(
1279 __in efx_nic_t *enp);
1280
1281extern void
1282efx_ev_fini(
1283 __in efx_nic_t *enp);
1284
1285#define EFX_MASK(_max, _min) (-((_max) << 1) ^ -(_min))
1286
1287#define EFX_EVQ_MAXNEVS 32768
1288#define EFX_EVQ_MINNEVS 512
1289
1290#define EFX_EVQ_NEVS_MASK EFX_MASK(EFX_EVQ_MAXNEVS, EFX_EVQ_MINNEVS)
1291
1292#define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1293#define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1294
1295extern __checkReturn int
1296efx_ev_qcreate(
1297 __in efx_nic_t *enp,
1298 __in unsigned int index,
1299 __in efsys_mem_t *esmp,
1300 __in size_t n,
1301 __in uint32_t id,
1302 __deref_out efx_evq_t **eepp);
1303
1304extern void
1305efx_ev_qpost(
1306 __in efx_evq_t *eep,
1307 __in uint16_t data);
1308
1309typedef __checkReturn boolean_t
1310(*efx_initialized_ev_t)(
1311 __in_opt void *arg);
1312
1313#define EFX_PKT_UNICAST 0x0004
1314#define EFX_PKT_START 0x0008
1315
1316#define EFX_PKT_VLAN_TAGGED 0x0010
1317#define EFX_CKSUM_TCPUDP 0x0020
1318#define EFX_CKSUM_IPV4 0x0040
1319#define EFX_PKT_CONT 0x0080
1320
1321#define EFX_CHECK_VLAN 0x0100
1322#define EFX_PKT_TCP 0x0200
1323#define EFX_PKT_UDP 0x0400
1324#define EFX_PKT_IPV4 0x0800
1325
1326#define EFX_PKT_IPV6 0x1000
1327#define EFX_ADDR_MISMATCH 0x4000
1328#define EFX_DISCARD 0x8000
1329
1330#define EFX_EV_RX_NLABELS 32
1331#define EFX_EV_TX_NLABELS 32
1332
1333typedef __checkReturn boolean_t
1334(*efx_rx_ev_t)(
1335 __in_opt void *arg,
1336 __in uint32_t label,
1337 __in uint32_t id,
1338 __in uint32_t size,
1339 __in uint16_t flags);
1340
1341typedef __checkReturn boolean_t
1342(*efx_tx_ev_t)(
1343 __in_opt void *arg,
1344 __in uint32_t label,
1345 __in uint32_t id);
1346
1347#define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1348#define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1349#define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1350#define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1351#define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1352#define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1353
1354typedef __checkReturn boolean_t
1355(*efx_exception_ev_t)(
1356 __in_opt void *arg,
1357 __in uint32_t label,
1358 __in uint32_t data);
1359
1360typedef __checkReturn boolean_t
1361(*efx_rxq_flush_done_ev_t)(
1362 __in_opt void *arg,
|
1374
1375typedef __checkReturn boolean_t
1376(*efx_software_ev_t)(
1377 __in_opt void *arg,
1378 __in uint16_t magic);
1379
1380typedef __checkReturn boolean_t
1381(*efx_sram_ev_t)(
1382 __in_opt void *arg,
1383 __in uint32_t code);
1384
1385#define EFX_SRAM_CLEAR 0
1386#define EFX_SRAM_UPDATE 1
1387#define EFX_SRAM_ILLEGAL_CLEAR 2
1388
1389typedef __checkReturn boolean_t
1390(*efx_wake_up_ev_t)(
1391 __in_opt void *arg,
1392 __in uint32_t label);
1393
1394typedef __checkReturn boolean_t
1395(*efx_timer_ev_t)(
1396 __in_opt void *arg,
1397 __in uint32_t label);
1398
1399typedef __checkReturn boolean_t
1400(*efx_link_change_ev_t)(
1401 __in_opt void *arg,
1402 __in efx_link_mode_t link_mode);
1403
1404#if EFSYS_OPT_MON_STATS
1405
1406typedef __checkReturn boolean_t
1407(*efx_monitor_ev_t)(
1408 __in_opt void *arg,
1409 __in efx_mon_stat_t id,
1410 __in efx_mon_stat_value_t value);
1411
1412#endif /* EFSYS_OPT_MON_STATS */
1413
1414#if EFSYS_OPT_MAC_STATS
1415
1416typedef __checkReturn boolean_t
1417(*efx_mac_stats_ev_t)(
1418 __in_opt void *arg,
1419 __in uint32_t generation
1420 );
1421
1422#endif /* EFSYS_OPT_MAC_STATS */
1423
1424typedef struct efx_ev_callbacks_s {
1425 efx_initialized_ev_t eec_initialized;
1426 efx_rx_ev_t eec_rx;
1427 efx_tx_ev_t eec_tx;
1428 efx_exception_ev_t eec_exception;
1429 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1430 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1431 efx_txq_flush_done_ev_t eec_txq_flush_done;
1432 efx_software_ev_t eec_software;
1433 efx_sram_ev_t eec_sram;
1434 efx_wake_up_ev_t eec_wake_up;
1435 efx_timer_ev_t eec_timer;
1436 efx_link_change_ev_t eec_link_change;
1437#if EFSYS_OPT_MON_STATS
1438 efx_monitor_ev_t eec_monitor;
1439#endif /* EFSYS_OPT_MON_STATS */
1440#if EFSYS_OPT_MAC_STATS
1441 efx_mac_stats_ev_t eec_mac_stats;
1442#endif /* EFSYS_OPT_MON_STATS */
1443} efx_ev_callbacks_t;
1444
1445extern __checkReturn boolean_t
1446efx_ev_qpending(
1447 __in efx_evq_t *eep,
1448 __in unsigned int count);
1449
1450#if EFSYS_OPT_EV_PREFETCH
1451
1452extern void
1453efx_ev_qprefetch(
1454 __in efx_evq_t *eep,
1455 __in unsigned int count);
1456
1457#endif /* EFSYS_OPT_EV_PREFETCH */
1458
1459extern void
1460efx_ev_qpoll(
1461 __in efx_evq_t *eep,
1462 __inout unsigned int *countp,
1463 __in const efx_ev_callbacks_t *eecp,
1464 __in_opt void *arg);
1465
1466extern __checkReturn int
1467efx_ev_qmoderate(
1468 __in efx_evq_t *eep,
1469 __in unsigned int us);
1470
1471extern __checkReturn int
1472efx_ev_qprime(
1473 __in efx_evq_t *eep,
1474 __in unsigned int count);
1475
1476#if EFSYS_OPT_QSTATS
1477
1478#if EFSYS_OPT_NAMES
1479
1480extern const char __cs *
1481efx_ev_qstat_name(
1482 __in efx_nic_t *enp,
1483 __in unsigned int id);
1484
1485#endif /* EFSYS_OPT_NAMES */
1486
1487extern void
1488efx_ev_qstats_update(
1489 __in efx_evq_t *eep,
1490 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1491
1492#endif /* EFSYS_OPT_QSTATS */
1493
1494extern void
1495efx_ev_qdestroy(
1496 __in efx_evq_t *eep);
1497
1498/* RX */
1499
1500typedef struct efx_rxq_s efx_rxq_t;
1501
1502extern __checkReturn int
1503efx_rx_init(
1504 __in efx_nic_t *enp);
1505
1506extern void
1507efx_rx_fini(
1508 __in efx_nic_t *enp);
1509
1510#if EFSYS_OPT_RX_HDR_SPLIT
1511 __checkReturn int
1512efx_rx_hdr_split_enable(
1513 __in efx_nic_t *enp,
1514 __in unsigned int hdr_buf_size,
1515 __in unsigned int pld_buf_size);
1516
1517#endif /* EFSYS_OPT_RX_HDR_SPLIT */
1518
1519#if EFSYS_OPT_RX_SCATTER
1520 __checkReturn int
1521efx_rx_scatter_enable(
1522 __in efx_nic_t *enp,
1523 __in unsigned int buf_size);
1524#endif /* EFSYS_OPT_RX_SCATTER */
1525
1526#if EFSYS_OPT_RX_SCALE
1527
1528typedef enum efx_rx_hash_alg_e {
1529 EFX_RX_HASHALG_LFSR = 0,
1530 EFX_RX_HASHALG_TOEPLITZ
1531} efx_rx_hash_alg_t;
1532
1533typedef enum efx_rx_hash_type_e {
1534 EFX_RX_HASH_IPV4 = 0,
1535 EFX_RX_HASH_TCPIPV4,
1536 EFX_RX_HASH_IPV6,
1537 EFX_RX_HASH_TCPIPV6,
1538} efx_rx_hash_type_t;
1539
1540#define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1541#define EFX_MAXRSS 64 /* RX indirection entry range */
1542#define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1543
1544extern __checkReturn int
1545efx_rx_scale_mode_set(
1546 __in efx_nic_t *enp,
1547 __in efx_rx_hash_alg_t alg,
1548 __in efx_rx_hash_type_t type,
1549 __in boolean_t insert);
1550
1551extern __checkReturn int
1552efx_rx_scale_tbl_set(
1553 __in efx_nic_t *enp,
1554 __in_ecount(n) unsigned int *table,
1555 __in size_t n);
1556
1557extern __checkReturn int
1558efx_rx_scale_toeplitz_ipv4_key_set(
1559 __in efx_nic_t *enp,
1560 __in_ecount(n) uint8_t *key,
1561 __in size_t n);
1562
1563extern __checkReturn int
1564efx_rx_scale_toeplitz_ipv6_key_set(
1565 __in efx_nic_t *enp,
1566 __in_ecount(n) uint8_t *key,
1567 __in size_t n);
1568
1569/*
1570 * The prefix is a byte array of one of the forms:
1571 *
1572 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1573 * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.TT.TT.TT.TT
1574 * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.LL.LL
1575 *
1576 * where:
1577 *
1578 * TT.TT.TT.TT is a 32-bit Toeplitz hash
1579 * LL.LL is a 16-bit LFSR hash
1580 *
1581 * Hash values are in network (big-endian) byte order.
1582 */
1583
1584#define EFX_RX_PREFIX_SIZE 16
1585
1586#define EFX_RX_HASH_VALUE(_func, _buffer) \
1587 (((_func) == EFX_RX_HASHALG_LFSR) ? \
1588 ((uint16_t)(((_buffer)[14] << 8) | (_buffer)[15])) : \
1589 ((uint32_t)(((_buffer)[12] << 24) | \
1590 ((_buffer)[13] << 16) | \
1591 ((_buffer)[14] << 8) | \
1592 (_buffer)[15])))
1593
1594#define EFX_RX_HASH_SIZE(_func) \
1595 (((_func) == EFX_RX_HASHALG_LFSR) ? \
1596 sizeof (uint16_t) : \
1597 sizeof (uint32_t))
1598
1599#endif /* EFSYS_OPT_RX_SCALE */
1600
1601#define EFX_RXQ_MAXNDESCS 4096
1602#define EFX_RXQ_MINNDESCS 512
1603
1604#define EFX_RXQ_NDESCS_MASK EFX_MASK(EFX_RXQ_MAXNDESCS, EFX_RXQ_MINNDESCS)
1605
1606#define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1607#define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1608#define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1609
1610typedef enum efx_rxq_type_e {
1611 EFX_RXQ_TYPE_DEFAULT,
1612 EFX_RXQ_TYPE_SPLIT_HEADER,
1613 EFX_RXQ_TYPE_SPLIT_PAYLOAD,
1614 EFX_RXQ_TYPE_SCATTER,
1615 EFX_RXQ_NTYPES
1616} efx_rxq_type_t;
1617
1618extern __checkReturn int
1619efx_rx_qcreate(
1620 __in efx_nic_t *enp,
1621 __in unsigned int index,
1622 __in unsigned int label,
1623 __in efx_rxq_type_t type,
1624 __in efsys_mem_t *esmp,
1625 __in size_t n,
1626 __in uint32_t id,
1627 __in efx_evq_t *eep,
1628 __deref_out efx_rxq_t **erpp);
1629
1630typedef struct efx_buffer_s {
1631 efsys_dma_addr_t eb_addr;
1632 size_t eb_size;
1633 boolean_t eb_eop;
1634} efx_buffer_t;
1635
1636extern void
1637efx_rx_qpost(
1638 __in efx_rxq_t *erp,
1639 __in_ecount(n) efsys_dma_addr_t *addrp,
1640 __in size_t size,
1641 __in unsigned int n,
1642 __in unsigned int completed,
1643 __in unsigned int added);
1644
1645extern void
1646efx_rx_qpush(
1647 __in efx_rxq_t *erp,
1648 __in unsigned int added);
1649
1650extern void
1651efx_rx_qflush(
1652 __in efx_rxq_t *erp);
1653
1654extern void
1655efx_rx_qenable(
1656 __in efx_rxq_t *erp);
1657
1658extern void
1659efx_rx_qdestroy(
1660 __in efx_rxq_t *erp);
1661
1662/* TX */
1663
1664typedef struct efx_txq_s efx_txq_t;
1665
1666#if EFSYS_OPT_QSTATS
1667
1668/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 536c5fa5014944bf */
1669typedef enum efx_tx_qstat_e {
1670 TX_POST,
1671 TX_UNALIGNED_SPLIT,
1672 TX_NQSTATS
1673} efx_tx_qstat_t;
1674
1675/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1676
1677#endif /* EFSYS_OPT_QSTATS */
1678
1679extern __checkReturn int
1680efx_tx_init(
1681 __in efx_nic_t *enp);
1682
1683extern void
1684efx_tx_fini(
1685 __in efx_nic_t *enp);
1686
1687#define EFX_TXQ_MAXNDESCS 4096
1688#define EFX_TXQ_MINNDESCS 512
1689
1690#define EFX_TXQ_NDESCS_MASK EFX_MASK(EFX_TXQ_MAXNDESCS, EFX_TXQ_MINNDESCS)
1691
1692#define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1693#define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1694#define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1695
1696extern __checkReturn int
1697efx_tx_qcreate(
1698 __in efx_nic_t *enp,
1699 __in unsigned int index,
1700 __in unsigned int label,
1701 __in efsys_mem_t *esmp,
1702 __in size_t n,
1703 __in uint32_t id,
1704 __in uint16_t flags,
1705 __in efx_evq_t *eep,
1706 __deref_out efx_txq_t **etpp);
1707
1708extern __checkReturn int
1709efx_tx_qpost(
1710 __in efx_txq_t *etp,
1711 __in_ecount(n) efx_buffer_t *eb,
1712 __in unsigned int n,
1713 __in unsigned int completed,
1714 __inout unsigned int *addedp);
1715
1716extern void
1717efx_tx_qpush(
1718 __in efx_txq_t *etp,
1719 __in unsigned int added);
1720
1721extern void
1722efx_tx_qflush(
1723 __in efx_txq_t *etp);
1724
1725extern void
1726efx_tx_qenable(
1727 __in efx_txq_t *etp);
1728
1729#if EFSYS_OPT_QSTATS
1730
1731#if EFSYS_OPT_NAMES
1732
1733extern const char __cs *
1734efx_tx_qstat_name(
1735 __in efx_nic_t *etp,
1736 __in unsigned int id);
1737
1738#endif /* EFSYS_OPT_NAMES */
1739
1740extern void
1741efx_tx_qstats_update(
1742 __in efx_txq_t *etp,
1743 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
1744
1745#endif /* EFSYS_OPT_QSTATS */
1746
1747extern void
1748efx_tx_qdestroy(
1749 __in efx_txq_t *etp);
1750
1751
1752/* FILTER */
1753
1754#if EFSYS_OPT_FILTER
1755
1756typedef enum efx_filter_flag_e {
1757 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across
1758 * multiple queues */
1759 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */
1760 EFX_FILTER_FLAG_RX_OVERRIDE_IP = 0x04, /* MAC filter overrides
1761 * any matching IP filter */
1762} efx_filter_flag_t;
1763
1764typedef struct efx_filter_spec_s {
1765 uint8_t efs_type;
1766 uint8_t efs_flags;
1767 uint16_t efs_dmaq_id;
1768 uint32_t efs_dword[3];
1769} efx_filter_spec_t;
1770
1771extern __checkReturn int
1772efx_filter_init(
1773 __in efx_nic_t *enp);
1774
1775extern void
1776efx_filter_fini(
1777 __in efx_nic_t *enp);
1778
1779extern __checkReturn int
1780efx_rx_filter_insert(
1781 __in efx_rxq_t *erp,
1782 __inout efx_filter_spec_t *spec);
1783
1784extern __checkReturn int
1785efx_rx_filter_remove(
1786 __in efx_rxq_t *erp,
1787 __inout efx_filter_spec_t *spec);
1788
1789 void
1790efx_filter_restore(
1791 __in efx_nic_t *enp);
1792
1793extern void
1794efx_filter_spec_rx_ipv4_tcp_full(
1795 __inout efx_filter_spec_t *spec,
1796 __in unsigned int flags,
1797 __in uint32_t src_ip,
1798 __in uint16_t src_tcp,
1799 __in uint32_t dest_ip,
1800 __in uint16_t dest_tcp);
1801
1802extern void
1803efx_filter_spec_rx_ipv4_tcp_wild(
1804 __inout efx_filter_spec_t *spec,
1805 __in unsigned int flags,
1806 __in uint32_t dest_ip,
1807 __in uint16_t dest_tcp);
1808
1809extern void
1810efx_filter_spec_rx_ipv4_udp_full(
1811 __inout efx_filter_spec_t *spec,
1812 __in unsigned int flags,
1813 __in uint32_t src_ip,
1814 __in uint16_t src_udp,
1815 __in uint32_t dest_ip,
1816 __in uint16_t dest_udp);
1817
1818extern void
1819efx_filter_spec_rx_ipv4_udp_wild(
1820 __inout efx_filter_spec_t *spec,
1821 __in unsigned int flags,
1822 __in uint32_t dest_ip,
1823 __in uint16_t dest_udp);
1824
1825extern void
1826efx_filter_spec_rx_mac_full(
1827 __inout efx_filter_spec_t *spec,
1828 __in unsigned int flags,
1829 __in uint16_t vlan_id,
1830 __in uint8_t *dest_mac);
1831
1832extern void
1833efx_filter_spec_rx_mac_wild(
1834 __inout efx_filter_spec_t *spec,
1835 __in unsigned int flags,
1836 __in uint8_t *dest_mac);
1837
1838
1839extern __checkReturn int
1840efx_tx_filter_insert(
1841 __in efx_txq_t *etp,
1842 __inout efx_filter_spec_t *spec);
1843
1844extern __checkReturn int
1845efx_tx_filter_remove(
1846 __in efx_txq_t *etp,
1847 __inout efx_filter_spec_t *spec);
1848
1849extern void
1850efx_filter_spec_tx_ipv4_tcp_full(
1851 __inout efx_filter_spec_t *spec,
1852 __in uint32_t src_ip,
1853 __in uint16_t src_tcp,
1854 __in uint32_t dest_ip,
1855 __in uint16_t dest_tcp);
1856
1857extern void
1858efx_filter_spec_tx_ipv4_tcp_wild(
1859 __inout efx_filter_spec_t *spec,
1860 __in uint32_t src_ip,
1861 __in uint16_t src_tcp);
1862
1863extern void
1864efx_filter_spec_tx_ipv4_udp_full(
1865 __inout efx_filter_spec_t *spec,
1866 __in uint32_t src_ip,
1867 __in uint16_t src_udp,
1868 __in uint32_t dest_ip,
1869 __in uint16_t dest_udp);
1870
1871extern void
1872efx_filter_spec_tx_ipv4_udp_wild(
1873 __inout efx_filter_spec_t *spec,
1874 __in uint32_t src_ip,
1875 __in uint16_t src_udp);
1876
1877extern void
1878efx_filter_spec_tx_mac_full(
1879 __inout efx_filter_spec_t *spec,
1880 __in uint16_t vlan_id,
1881 __in uint8_t *src_mac);
1882
1883extern void
1884efx_filter_spec_tx_mac_wild(
1885 __inout efx_filter_spec_t *spec,
1886 __in uint8_t *src_mac);
1887
1888#endif /* EFSYS_OPT_FILTER */
1889
1890
1891#ifdef __cplusplus
1892}
1893#endif
1894
1895#endif /* _SYS_EFX_H */
| 1374
1375typedef __checkReturn boolean_t
1376(*efx_software_ev_t)(
1377 __in_opt void *arg,
1378 __in uint16_t magic);
1379
1380typedef __checkReturn boolean_t
1381(*efx_sram_ev_t)(
1382 __in_opt void *arg,
1383 __in uint32_t code);
1384
1385#define EFX_SRAM_CLEAR 0
1386#define EFX_SRAM_UPDATE 1
1387#define EFX_SRAM_ILLEGAL_CLEAR 2
1388
1389typedef __checkReturn boolean_t
1390(*efx_wake_up_ev_t)(
1391 __in_opt void *arg,
1392 __in uint32_t label);
1393
1394typedef __checkReturn boolean_t
1395(*efx_timer_ev_t)(
1396 __in_opt void *arg,
1397 __in uint32_t label);
1398
1399typedef __checkReturn boolean_t
1400(*efx_link_change_ev_t)(
1401 __in_opt void *arg,
1402 __in efx_link_mode_t link_mode);
1403
1404#if EFSYS_OPT_MON_STATS
1405
1406typedef __checkReturn boolean_t
1407(*efx_monitor_ev_t)(
1408 __in_opt void *arg,
1409 __in efx_mon_stat_t id,
1410 __in efx_mon_stat_value_t value);
1411
1412#endif /* EFSYS_OPT_MON_STATS */
1413
1414#if EFSYS_OPT_MAC_STATS
1415
1416typedef __checkReturn boolean_t
1417(*efx_mac_stats_ev_t)(
1418 __in_opt void *arg,
1419 __in uint32_t generation
1420 );
1421
1422#endif /* EFSYS_OPT_MAC_STATS */
1423
1424typedef struct efx_ev_callbacks_s {
1425 efx_initialized_ev_t eec_initialized;
1426 efx_rx_ev_t eec_rx;
1427 efx_tx_ev_t eec_tx;
1428 efx_exception_ev_t eec_exception;
1429 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1430 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1431 efx_txq_flush_done_ev_t eec_txq_flush_done;
1432 efx_software_ev_t eec_software;
1433 efx_sram_ev_t eec_sram;
1434 efx_wake_up_ev_t eec_wake_up;
1435 efx_timer_ev_t eec_timer;
1436 efx_link_change_ev_t eec_link_change;
1437#if EFSYS_OPT_MON_STATS
1438 efx_monitor_ev_t eec_monitor;
1439#endif /* EFSYS_OPT_MON_STATS */
1440#if EFSYS_OPT_MAC_STATS
1441 efx_mac_stats_ev_t eec_mac_stats;
1442#endif /* EFSYS_OPT_MON_STATS */
1443} efx_ev_callbacks_t;
1444
1445extern __checkReturn boolean_t
1446efx_ev_qpending(
1447 __in efx_evq_t *eep,
1448 __in unsigned int count);
1449
1450#if EFSYS_OPT_EV_PREFETCH
1451
1452extern void
1453efx_ev_qprefetch(
1454 __in efx_evq_t *eep,
1455 __in unsigned int count);
1456
1457#endif /* EFSYS_OPT_EV_PREFETCH */
1458
1459extern void
1460efx_ev_qpoll(
1461 __in efx_evq_t *eep,
1462 __inout unsigned int *countp,
1463 __in const efx_ev_callbacks_t *eecp,
1464 __in_opt void *arg);
1465
1466extern __checkReturn int
1467efx_ev_qmoderate(
1468 __in efx_evq_t *eep,
1469 __in unsigned int us);
1470
1471extern __checkReturn int
1472efx_ev_qprime(
1473 __in efx_evq_t *eep,
1474 __in unsigned int count);
1475
1476#if EFSYS_OPT_QSTATS
1477
1478#if EFSYS_OPT_NAMES
1479
1480extern const char __cs *
1481efx_ev_qstat_name(
1482 __in efx_nic_t *enp,
1483 __in unsigned int id);
1484
1485#endif /* EFSYS_OPT_NAMES */
1486
1487extern void
1488efx_ev_qstats_update(
1489 __in efx_evq_t *eep,
1490 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1491
1492#endif /* EFSYS_OPT_QSTATS */
1493
1494extern void
1495efx_ev_qdestroy(
1496 __in efx_evq_t *eep);
1497
1498/* RX */
1499
1500typedef struct efx_rxq_s efx_rxq_t;
1501
1502extern __checkReturn int
1503efx_rx_init(
1504 __in efx_nic_t *enp);
1505
1506extern void
1507efx_rx_fini(
1508 __in efx_nic_t *enp);
1509
1510#if EFSYS_OPT_RX_HDR_SPLIT
1511 __checkReturn int
1512efx_rx_hdr_split_enable(
1513 __in efx_nic_t *enp,
1514 __in unsigned int hdr_buf_size,
1515 __in unsigned int pld_buf_size);
1516
1517#endif /* EFSYS_OPT_RX_HDR_SPLIT */
1518
1519#if EFSYS_OPT_RX_SCATTER
1520 __checkReturn int
1521efx_rx_scatter_enable(
1522 __in efx_nic_t *enp,
1523 __in unsigned int buf_size);
1524#endif /* EFSYS_OPT_RX_SCATTER */
1525
1526#if EFSYS_OPT_RX_SCALE
1527
1528typedef enum efx_rx_hash_alg_e {
1529 EFX_RX_HASHALG_LFSR = 0,
1530 EFX_RX_HASHALG_TOEPLITZ
1531} efx_rx_hash_alg_t;
1532
1533typedef enum efx_rx_hash_type_e {
1534 EFX_RX_HASH_IPV4 = 0,
1535 EFX_RX_HASH_TCPIPV4,
1536 EFX_RX_HASH_IPV6,
1537 EFX_RX_HASH_TCPIPV6,
1538} efx_rx_hash_type_t;
1539
1540#define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1541#define EFX_MAXRSS 64 /* RX indirection entry range */
1542#define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1543
1544extern __checkReturn int
1545efx_rx_scale_mode_set(
1546 __in efx_nic_t *enp,
1547 __in efx_rx_hash_alg_t alg,
1548 __in efx_rx_hash_type_t type,
1549 __in boolean_t insert);
1550
1551extern __checkReturn int
1552efx_rx_scale_tbl_set(
1553 __in efx_nic_t *enp,
1554 __in_ecount(n) unsigned int *table,
1555 __in size_t n);
1556
1557extern __checkReturn int
1558efx_rx_scale_toeplitz_ipv4_key_set(
1559 __in efx_nic_t *enp,
1560 __in_ecount(n) uint8_t *key,
1561 __in size_t n);
1562
1563extern __checkReturn int
1564efx_rx_scale_toeplitz_ipv6_key_set(
1565 __in efx_nic_t *enp,
1566 __in_ecount(n) uint8_t *key,
1567 __in size_t n);
1568
1569/*
1570 * The prefix is a byte array of one of the forms:
1571 *
1572 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1573 * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.TT.TT.TT.TT
1574 * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.LL.LL
1575 *
1576 * where:
1577 *
1578 * TT.TT.TT.TT is a 32-bit Toeplitz hash
1579 * LL.LL is a 16-bit LFSR hash
1580 *
1581 * Hash values are in network (big-endian) byte order.
1582 */
1583
1584#define EFX_RX_PREFIX_SIZE 16
1585
1586#define EFX_RX_HASH_VALUE(_func, _buffer) \
1587 (((_func) == EFX_RX_HASHALG_LFSR) ? \
1588 ((uint16_t)(((_buffer)[14] << 8) | (_buffer)[15])) : \
1589 ((uint32_t)(((_buffer)[12] << 24) | \
1590 ((_buffer)[13] << 16) | \
1591 ((_buffer)[14] << 8) | \
1592 (_buffer)[15])))
1593
1594#define EFX_RX_HASH_SIZE(_func) \
1595 (((_func) == EFX_RX_HASHALG_LFSR) ? \
1596 sizeof (uint16_t) : \
1597 sizeof (uint32_t))
1598
1599#endif /* EFSYS_OPT_RX_SCALE */
1600
1601#define EFX_RXQ_MAXNDESCS 4096
1602#define EFX_RXQ_MINNDESCS 512
1603
1604#define EFX_RXQ_NDESCS_MASK EFX_MASK(EFX_RXQ_MAXNDESCS, EFX_RXQ_MINNDESCS)
1605
1606#define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1607#define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1608#define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1609
1610typedef enum efx_rxq_type_e {
1611 EFX_RXQ_TYPE_DEFAULT,
1612 EFX_RXQ_TYPE_SPLIT_HEADER,
1613 EFX_RXQ_TYPE_SPLIT_PAYLOAD,
1614 EFX_RXQ_TYPE_SCATTER,
1615 EFX_RXQ_NTYPES
1616} efx_rxq_type_t;
1617
1618extern __checkReturn int
1619efx_rx_qcreate(
1620 __in efx_nic_t *enp,
1621 __in unsigned int index,
1622 __in unsigned int label,
1623 __in efx_rxq_type_t type,
1624 __in efsys_mem_t *esmp,
1625 __in size_t n,
1626 __in uint32_t id,
1627 __in efx_evq_t *eep,
1628 __deref_out efx_rxq_t **erpp);
1629
1630typedef struct efx_buffer_s {
1631 efsys_dma_addr_t eb_addr;
1632 size_t eb_size;
1633 boolean_t eb_eop;
1634} efx_buffer_t;
1635
1636extern void
1637efx_rx_qpost(
1638 __in efx_rxq_t *erp,
1639 __in_ecount(n) efsys_dma_addr_t *addrp,
1640 __in size_t size,
1641 __in unsigned int n,
1642 __in unsigned int completed,
1643 __in unsigned int added);
1644
1645extern void
1646efx_rx_qpush(
1647 __in efx_rxq_t *erp,
1648 __in unsigned int added);
1649
1650extern void
1651efx_rx_qflush(
1652 __in efx_rxq_t *erp);
1653
1654extern void
1655efx_rx_qenable(
1656 __in efx_rxq_t *erp);
1657
1658extern void
1659efx_rx_qdestroy(
1660 __in efx_rxq_t *erp);
1661
1662/* TX */
1663
1664typedef struct efx_txq_s efx_txq_t;
1665
1666#if EFSYS_OPT_QSTATS
1667
1668/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 536c5fa5014944bf */
1669typedef enum efx_tx_qstat_e {
1670 TX_POST,
1671 TX_UNALIGNED_SPLIT,
1672 TX_NQSTATS
1673} efx_tx_qstat_t;
1674
1675/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1676
1677#endif /* EFSYS_OPT_QSTATS */
1678
1679extern __checkReturn int
1680efx_tx_init(
1681 __in efx_nic_t *enp);
1682
1683extern void
1684efx_tx_fini(
1685 __in efx_nic_t *enp);
1686
1687#define EFX_TXQ_MAXNDESCS 4096
1688#define EFX_TXQ_MINNDESCS 512
1689
1690#define EFX_TXQ_NDESCS_MASK EFX_MASK(EFX_TXQ_MAXNDESCS, EFX_TXQ_MINNDESCS)
1691
1692#define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1693#define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1694#define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1695
1696extern __checkReturn int
1697efx_tx_qcreate(
1698 __in efx_nic_t *enp,
1699 __in unsigned int index,
1700 __in unsigned int label,
1701 __in efsys_mem_t *esmp,
1702 __in size_t n,
1703 __in uint32_t id,
1704 __in uint16_t flags,
1705 __in efx_evq_t *eep,
1706 __deref_out efx_txq_t **etpp);
1707
1708extern __checkReturn int
1709efx_tx_qpost(
1710 __in efx_txq_t *etp,
1711 __in_ecount(n) efx_buffer_t *eb,
1712 __in unsigned int n,
1713 __in unsigned int completed,
1714 __inout unsigned int *addedp);
1715
1716extern void
1717efx_tx_qpush(
1718 __in efx_txq_t *etp,
1719 __in unsigned int added);
1720
1721extern void
1722efx_tx_qflush(
1723 __in efx_txq_t *etp);
1724
1725extern void
1726efx_tx_qenable(
1727 __in efx_txq_t *etp);
1728
1729#if EFSYS_OPT_QSTATS
1730
1731#if EFSYS_OPT_NAMES
1732
1733extern const char __cs *
1734efx_tx_qstat_name(
1735 __in efx_nic_t *etp,
1736 __in unsigned int id);
1737
1738#endif /* EFSYS_OPT_NAMES */
1739
1740extern void
1741efx_tx_qstats_update(
1742 __in efx_txq_t *etp,
1743 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
1744
1745#endif /* EFSYS_OPT_QSTATS */
1746
1747extern void
1748efx_tx_qdestroy(
1749 __in efx_txq_t *etp);
1750
1751
1752/* FILTER */
1753
1754#if EFSYS_OPT_FILTER
1755
1756typedef enum efx_filter_flag_e {
1757 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across
1758 * multiple queues */
1759 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */
1760 EFX_FILTER_FLAG_RX_OVERRIDE_IP = 0x04, /* MAC filter overrides
1761 * any matching IP filter */
1762} efx_filter_flag_t;
1763
1764typedef struct efx_filter_spec_s {
1765 uint8_t efs_type;
1766 uint8_t efs_flags;
1767 uint16_t efs_dmaq_id;
1768 uint32_t efs_dword[3];
1769} efx_filter_spec_t;
1770
1771extern __checkReturn int
1772efx_filter_init(
1773 __in efx_nic_t *enp);
1774
1775extern void
1776efx_filter_fini(
1777 __in efx_nic_t *enp);
1778
1779extern __checkReturn int
1780efx_rx_filter_insert(
1781 __in efx_rxq_t *erp,
1782 __inout efx_filter_spec_t *spec);
1783
1784extern __checkReturn int
1785efx_rx_filter_remove(
1786 __in efx_rxq_t *erp,
1787 __inout efx_filter_spec_t *spec);
1788
1789 void
1790efx_filter_restore(
1791 __in efx_nic_t *enp);
1792
1793extern void
1794efx_filter_spec_rx_ipv4_tcp_full(
1795 __inout efx_filter_spec_t *spec,
1796 __in unsigned int flags,
1797 __in uint32_t src_ip,
1798 __in uint16_t src_tcp,
1799 __in uint32_t dest_ip,
1800 __in uint16_t dest_tcp);
1801
1802extern void
1803efx_filter_spec_rx_ipv4_tcp_wild(
1804 __inout efx_filter_spec_t *spec,
1805 __in unsigned int flags,
1806 __in uint32_t dest_ip,
1807 __in uint16_t dest_tcp);
1808
1809extern void
1810efx_filter_spec_rx_ipv4_udp_full(
1811 __inout efx_filter_spec_t *spec,
1812 __in unsigned int flags,
1813 __in uint32_t src_ip,
1814 __in uint16_t src_udp,
1815 __in uint32_t dest_ip,
1816 __in uint16_t dest_udp);
1817
1818extern void
1819efx_filter_spec_rx_ipv4_udp_wild(
1820 __inout efx_filter_spec_t *spec,
1821 __in unsigned int flags,
1822 __in uint32_t dest_ip,
1823 __in uint16_t dest_udp);
1824
1825extern void
1826efx_filter_spec_rx_mac_full(
1827 __inout efx_filter_spec_t *spec,
1828 __in unsigned int flags,
1829 __in uint16_t vlan_id,
1830 __in uint8_t *dest_mac);
1831
1832extern void
1833efx_filter_spec_rx_mac_wild(
1834 __inout efx_filter_spec_t *spec,
1835 __in unsigned int flags,
1836 __in uint8_t *dest_mac);
1837
1838
1839extern __checkReturn int
1840efx_tx_filter_insert(
1841 __in efx_txq_t *etp,
1842 __inout efx_filter_spec_t *spec);
1843
1844extern __checkReturn int
1845efx_tx_filter_remove(
1846 __in efx_txq_t *etp,
1847 __inout efx_filter_spec_t *spec);
1848
1849extern void
1850efx_filter_spec_tx_ipv4_tcp_full(
1851 __inout efx_filter_spec_t *spec,
1852 __in uint32_t src_ip,
1853 __in uint16_t src_tcp,
1854 __in uint32_t dest_ip,
1855 __in uint16_t dest_tcp);
1856
1857extern void
1858efx_filter_spec_tx_ipv4_tcp_wild(
1859 __inout efx_filter_spec_t *spec,
1860 __in uint32_t src_ip,
1861 __in uint16_t src_tcp);
1862
1863extern void
1864efx_filter_spec_tx_ipv4_udp_full(
1865 __inout efx_filter_spec_t *spec,
1866 __in uint32_t src_ip,
1867 __in uint16_t src_udp,
1868 __in uint32_t dest_ip,
1869 __in uint16_t dest_udp);
1870
1871extern void
1872efx_filter_spec_tx_ipv4_udp_wild(
1873 __inout efx_filter_spec_t *spec,
1874 __in uint32_t src_ip,
1875 __in uint16_t src_udp);
1876
1877extern void
1878efx_filter_spec_tx_mac_full(
1879 __inout efx_filter_spec_t *spec,
1880 __in uint16_t vlan_id,
1881 __in uint8_t *src_mac);
1882
1883extern void
1884efx_filter_spec_tx_mac_wild(
1885 __inout efx_filter_spec_t *spec,
1886 __in uint8_t *src_mac);
1887
1888#endif /* EFSYS_OPT_FILTER */
1889
1890
1891#ifdef __cplusplus
1892}
1893#endif
1894
1895#endif /* _SYS_EFX_H */
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