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if_sfreg.h (50863)	if_sfreg.h (53468)
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 *	1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 *
32 * $FreeBSD: head/sys/dev/sf/if_sfreg.h 50863 1999-09-03 20:58:39Z wpaul $	32 * $FreeBSD: head/sys/dev/sf/if_sfreg.h 53468 1999-11-20 18:29:44Z wpaul $
33 / 34 35/ 36 * Registers for the Adaptec AIC-6915 Starfire. The Starfire has a 512K 37 * register space. These registers can be accessed in the following way: 38 * - PCI config registers are always accessible through PCI config space 39 * - Full 512K space mapped into memory using PCI memory mapped access 40 * - 256-byte I/O space mapped through PCI I/O access 41 * - Full 512K space mapped through indirect I/O using PCI I/O access 42 * It's possible to use either memory mapped mode or I/O mode to access 43 * the registers, but memory mapped is usually the easiest. All registers 44 * are 32 bits wide and must be accessed using 32-bit operations. 45 / 46 47/ 48 * Adaptec PCI vendor ID. 49 / 50#define AD_VENDORID 0x9004 51 52/ 53 * AIC-6915 PCI device ID. 54 / 55#define AD_DEVICEID_STARFIRE 0x6915 56 57/ 58 * AIC-6915 subsystem IDs. Adaptec uses the subsystem ID to identify 59 * the exact kind of NIC on which the ASIC is mounted. Currently there 60 * are six different variations. Note: the Adaptec manual lists code 0x28 61 * for two different NICs: the 62044 and the 69011/TX. This is a typo: 62 * the code for the 62044 is really 0x18.	33 / 34 35/ 36 * Registers for the Adaptec AIC-6915 Starfire. The Starfire has a 512K 37 * register space. These registers can be accessed in the following way: 38 * - PCI config registers are always accessible through PCI config space 39 * - Full 512K space mapped into memory using PCI memory mapped access 40 * - 256-byte I/O space mapped through PCI I/O access 41 * - Full 512K space mapped through indirect I/O using PCI I/O access 42 * It's possible to use either memory mapped mode or I/O mode to access 43 * the registers, but memory mapped is usually the easiest. All registers 44 * are 32 bits wide and must be accessed using 32-bit operations. 45 / 46 47/ 48 * Adaptec PCI vendor ID. 49 / 50#define AD_VENDORID 0x9004 51 52/ 53 * AIC-6915 PCI device ID. 54 / 55#define AD_DEVICEID_STARFIRE 0x6915 56 57/ 58 * AIC-6915 subsystem IDs. Adaptec uses the subsystem ID to identify 59 * the exact kind of NIC on which the ASIC is mounted. Currently there 60 * are six different variations. Note: the Adaptec manual lists code 0x28 61 * for two different NICs: the 62044 and the 69011/TX. This is a typo: 62 * the code for the 62044 is really 0x18.
	63 * 64 * Note that there also appears to be an 0x19 code for a newer rev 65 * 62044 card.
63 / 64#define AD_SUBSYSID_62011_REV0 0x0008 / single port 10/100baseTX 64-bit / 65#define AD_SUBSYSID_62011_REV1 0x0009 / single port 10/100baseTX 64-bit / 66#define AD_SUBSYSID_62022 0x0010 / dual port 10/100baseTX 64-bit */	66 / 67#define AD_SUBSYSID_62011_REV0 0x0008 / single port 10/100baseTX 64-bit / 68#define AD_SUBSYSID_62011_REV1 0x0009 / single port 10/100baseTX 64-bit / 69#define AD_SUBSYSID_62022 0x0010 / dual port 10/100baseTX 64-bit */
67#define AD_SUBSYSID_62044 0x0018 /* quad port 10/100baseTX 64-bit */	70#define AD_SUBSYSID_62044_REV0 0x0018 /* quad port 10/100baseTX 64-bit / 71#define AD_SUBSYSID_62044_REV1 0x0019 / quad port 10/100baseTX 64-bit */
68#define AD_SUBSYSID_62020 0x0020 /* single port 10/100baseFX 64-bit / 69#define AD_SUBSYSID_69011 0x0028 / single port 10/100baseTX 32-bit / 70 71/ 72 * Starfire internal register space map. The entire register space 73 * is available using PCI memory mapped mode. The SF_RMAP_INTREG 74 * space is available using PCI I/O mode. The entire space can be 75 * accessed using indirect I/O using the indirect I/O addr and 76 * indirect I/O data registers located within the SF_RMAP_INTREG space. 77 / 78#define SF_RMAP_ROMADDR_BASE 0x00000 / Expansion ROM space / 79#define SF_RMAP_ROMADDR_MAX 0x3FFFF 80 81#define SF_RMAP_EXGPIO_BASE 0x40000 / External general purpose regs / 82#define SF_RMAP_EXGPIO_MAX 0x3FFFF 83 84#define SF_RMAP_INTREG_BASE 0x50000 / Internal functional registers / 85#define SF_RMAP_INTREG_MAX 0x500FF 86#define SF_RMAP_GENREG_BASE 0x50100 / General purpose registers / 87#define SF_RMAP_GENREG_MAX 0x5FFFF 88 89#define SF_RMAP_FIFO_BASE 0x60000 90#define SF_RMAP_FIFO_MAX 0x6FFFF 91 92#define SF_RMAP_STS_BASE 0x70000 93#define SF_RMAP_STS_MAX 0x70083 94 95#define SF_RMAP_RSVD_BASE 0x70084 96#define SF_RMAP_RSVD_MAX 0x7FFFF 97 98/ 99 * PCI config header registers, 0x0000 to 0x003F 100 / 101#define SF_PCI_VENDOR_ID 0x0000 102#define SF_PCI_DEVICE_ID 0x0002 103#define SF_PCI_COMMAND 0x0004 104#define SF_PCI_STATUS 0x0006 105#define SF_PCI_REVID 0x0008 106#define SF_PCI_CLASSCODE 0x0009 107#define SF_PCI_CACHELEN 0x000C 108#define SF_PCI_LATENCY_TIMER 0x000D 109#define SF_PCI_HEADER_TYPE 0x000E 110#define SF_PCI_LOMEM 0x0010 111#define SF_PCI_LOIO 0x0014 112#define SF_PCI_SUBVEN_ID 0x002C 113#define SF_PCI_SYBSYS_ID 0x002E 114#define SF_PCI_BIOSROM 0x0030 115#define SF_PCI_INTLINE 0x003C 116#define SF_PCI_INTPIN 0x003D 117#define SF_PCI_MINGNT 0x003E 118#define SF_PCI_MINLAT 0x003F 119* 120/* 121 * PCI registers, 0x0040 to 0x006F 122 / 123#define SF_PCI_DEVCFG 0x0040 124#define SF_BACCTL 0x0044 125#define SF_PCI_MON1 0x0048 126#define SF_PCI_MON2 0x004C 127#define SF_PCI_CAPID 0x0050 / 8 bits / 128#define SF_PCI_NEXTPTR 0x0051 / 8 bits / 129#define SF_PCI_PWRMGMTCAP 0x0052 / 16 bits / 130#define SF_PCI_PWRMGMTCTRL 0x0054 / 16 bits / 131#define SF_PCI_PME_EVENT 0x0058 132#define SF_PCI_EECTL 0x0060 133#define SF_PCI_COMPLIANCE 0x0064 134#define SF_INDIRECTIO_ADDR 0x0068 135#define SF_INDIRECTIO_DATA 0x006C 136* 137#define SF_PCIDEVCFG_RESET 0x00000001 138#define SF_PCIDEVCFG_FORCE64 0x00000002 139#define SF_PCIDEVCFG_SYSTEM64 0x00000004 140#define SF_PCIDEVCFG_RSVD0 0x00000008 141#define SF_PCIDEVCFG_INCR_INB 0x00000010 142#define SF_PCIDEVCFG_ABTONPERR 0x00000020 143#define SF_PCIDEVCFG_STPONPERR 0x00000040 144#define SF_PCIDEVCFG_MR_ENB 0x00000080 145#define SF_PCIDEVCFG_FIFOTHR 0x00000F00 146#define SF_PCIDEVCFG_STPONCA 0x00001000 147#define SF_PCIDEVCFG_PCIMEN 0x00002000 /* enable PCI bus master / 148#define SF_PCIDEVCFG_LATSTP 0x00004000 149#define SF_PCIDEVCFG_BYTE_ENB 0x00008000 150#define SF_PCIDEVCFG_EECSWIDTH 0x00070000 151#define SF_PCIDEVCFG_STPMWCA 0x00080000 152#define SF_PCIDEVCFG_REGCSWIDTH 0x00700000 153#define SF_PCIDEVCFG_INTR_ENB 0x00800000 154#define SF_PCIDEVCFG_DPR_ENB 0x01000000 155#define SF_PCIDEVCFG_RSVD1 0x02000000 156#define SF_PCIDEVCFG_RSVD2 0x04000000 157#define SF_PCIDEVCFG_STA_ENB 0x08000000 158#define SF_PCIDEVCFG_RTA_ENB 0x10000000 159#define SF_PCIDEVCFG_RMA_ENB 0x20000000 160#define SF_PCIDEVCFG_SSE_ENB 0x40000000 161#define SF_PCIDEVCFG_DPE_ENB 0x80000000 162* 163#define SF_BACCTL_BACDMA_ENB 0x00000001 164#define SF_BACCTL_PREFER_RXDMA 0x00000002 165#define SF_BACCTL_PREFER_TXDMA 0x00000004 166#define SF_BACCTL_SINGLE_DMA 0x00000008 167#define SF_BACCTL_SWAPMODE_DATA 0x00000030 168#define SF_BACCTL_SWAPMODE_DESC 0x000000C0 169 170#define SF_SWAPMODE_LE 0x00000000 171#define SF_SWAPMODE_BE 0x00000010 172 173#define SF_PSTATE_MASK 0x0003 174#define SF_PSTATE_D0 0x0000 175#define SF_PSTATE_D1 0x0001 176#define SF_PSTATE_D2 0x0002 177#define SF_PSTATE_D3 0x0003 178#define SF_PME_EN 0x0010 179#define SF_PME_STATUS 0x8000 180 181 182/* 183 * Ethernet registers 0x0070 to 0x00FF 184 / 185#define SF_GEN_ETH_CTL 0x0070 186#define SF_TIMER_CTL 0x0074 187#define SF_CURTIME 0x0078 188#define SF_ISR 0x0080 189#define SF_ISR_SHADOW 0x0084 190#define SF_IMR 0x0088 191#define SF_GPIO 0x008C 192#define SF_TXDQ_CTL 0x0090 193#define SF_TXDQ_ADDR_HIPRIO 0x0094 194#define SF_TXDQ_ADDR_LOPRIO 0x0098 195#define SF_TXDQ_ADDR_HIADDR 0x009C 196#define SF_TXDQ_PRODIDX 0x00A0 197#define SF_TXDQ_CONSIDX 0x00A4 198#define SF_TXDMA_STS1 0x00A8 199#define SF_TXDMA_STS2 0x00AC 200#define SF_TX_FRAMCTL 0x00B0 201#define SF_TXCQ_ADDR_HI 0x00B4 202#define SF_TXCQ_CTL 0x00B8 203#define SF_RXCQ_CTL_1 0x00BC 204#define SF_RXCQ_CTL_2 0x00C0 205#define SF_CQ_CONSIDX 0x00C4 206#define SF_CQ_PRODIDX 0x00C8 207#define SF_CQ_RXQ2 0x00CC 208#define SF_RXDMA_CTL 0x00D0 209#define SF_RXDQ_CTL_1 0x00D4 210#define SF_RXDQ_CTL_2 0x00D8 211#define SF_RXDQ_ADDR_HIADDR 0x00DC 212#define SF_RXDQ_ADDR_Q1 0x00E0 213#define SF_RXDQ_ADDR_Q2 0x00E4 214#define SF_RXDQ_PTR_Q1 0x00E8 215#define SF_RXDQ_PTR_Q2 0x00EC 216#define SF_RXDMA_STS 0x00F0 217#define SF_RXFILT 0x00F4 218#define SF_RX_FRAMETEST_OUT 0x00F8 219* 220/* Ethernet control register / 221#define SF_ETHCTL_RX_ENB 0x00000001 222#define SF_ETHCTL_TX_ENB 0x00000002 223#define SF_ETHCTL_RXDMA_ENB 0x00000004 224#define SF_ETHCTL_TXDMA_ENB 0x00000008 225#define SF_ETHCTL_RXGFP_ENB 0x00000010 226#define SF_ETHCTL_TXGFP_ENB 0x00000020 227#define SF_ETHCTL_SOFTINTR 0x00000800 228* 229/* Timer control register / 230#define SF_TIMER_IMASK_INTERVAL 0x0000001F 231#define SF_TIMER_IMASK_MODE 0x00000060 232#define SF_TIMER_SMALLFRAME_BYP 0x00000100 233#define SF_TIMER_SMALLRX_FRAME 0x00000600 234#define SF_TIMER_TIMES_TEN 0x00000800 235#define SF_TIMER_RXHIPRIO_BYP 0x00001000 236#define SF_TIMER_TX_DMADONE_DLY 0x00002000 237#define SF_TIMER_TX_QDONE_DLY 0x00004000 238#define SF_TIMER_TX_FRDONE_DLY 0x00008000 239#define SF_TIMER_GENTIMER 0x00FF0000 240#define SF_TIMER_ONESHOT 0x01000000 241#define SF_TIMER_GENTIMER_RES 0x02000000 242#define SF_TIMER_TIMEST_RES 0x04000000 243#define SF_TIMER_RXQ2DONE_DLY 0x10000000 244#define SF_TIMER_EARLYRX2_DLY 0x20000000 245#define SF_TIMER_RXQ1DONE_DLY 0x40000000 246#define SF_TIMER_EARLYRX1_DLY 0x80000000 247* 248/* Interrupt status register / 249#define SF_ISR_PCIINT_ASSERTED 0x00000001 250#define SF_ISR_GFP_TX 0x00000002 251#define SF_ISR_GFP_RX 0x00000004 252#define SF_ISR_TX_BADID_HIPRIO 0x00000008 253#define SF_ISR_TX_BADID_LOPRIO 0x00000010 254#define SF_ISR_NO_TX_CSUM 0x00000020 255#define SF_ISR_RXDQ2_NOBUFS 0x00000040 256#define SF_ISR_RXGFP_NORESP 0x00000080 257#define SF_ISR_RXDQ1_DMADONE 0x00000100 258#define SF_ISR_RXDQ2_DMADONE 0x00000200 259#define SF_ISR_RXDQ1_EARLY 0x00000400 260#define SF_ISR_RXDQ2_EARLY 0x00000800 261#define SF_ISR_TX_QUEUEDONE 0x00001000 262#define SF_ISR_TX_DMADONE 0x00002000 263#define SF_ISR_TX_TXDONE 0x00004000 264#define SF_ISR_NORMALINTR 0x00008000 265#define SF_ISR_RXDQ1_NOBUFS 0x00010000 266#define SF_ISR_RXCQ2_NOBUFS 0x00020000 267#define SF_ISR_TX_LOFIFO 0x00040000 268#define SF_ISR_DMAERR 0x00080000 269#define SF_ISR_PCIINT 0x00100000 270#define SF_ISR_TXCQ_NOBUFS 0x00200000 271#define SF_ISR_RXCQ1_NOBUFS 0x00400000 272#define SF_ISR_SOFTINTR 0x00800000 273#define SF_ISR_GENTIMER 0x01000000 274#define SF_ISR_ABNORMALINTR 0x02000000 275#define SF_ISR_RSVD0 0x04000000 276#define SF_ISR_STATSOFLOW 0x08000000 277#define SF_ISR_GPIO 0xF0000000 278* 279/* 280 * Shadow interrupt status register. Unlike the normal IRQ register, 281 * reading bits here does not automatically cause them to reset. 282 / 283#define SF_SISR_PCIINT_ASSERTED 0x00000001 284#define SF_SISR_GFP_TX 0x00000002 285#define SF_SISR_GFP_RX 0x00000004 286#define SF_SISR_TX_BADID_HIPRIO 0x00000008 287#define SF_SISR_TX_BADID_LOPRIO 0x00000010 288#define SF_SISR_NO_TX_CSUM 0x00000020 289#define SF_SISR_RXDQ2_NOBUFS 0x00000040 290#define SF_SISR_RXGFP_NORESP 0x00000080 291#define SF_SISR_RXDQ1_DMADONE 0x00000100 292#define SF_SISR_RXDQ2_DMADONE 0x00000200 293#define SF_SISR_RXDQ1_EARLY 0x00000400 294#define SF_SISR_RXDQ2_EARLY 0x00000800 295#define SF_SISR_TX_QUEUEDONE 0x00001000 296#define SF_SISR_TX_DMADONE 0x00002000 297#define SF_SISR_TX_TXDONE 0x00004000 298#define SF_SISR_NORMALINTR 0x00008000 299#define SF_SISR_RXDQ1_NOBUFS 0x00010000 300#define SF_SISR_RXCQ2_NOBUFS 0x00020000 301#define SF_SISR_TX_LOFIFO 0x00040000 302#define SF_SISR_DMAERR 0x00080000 303#define SF_SISR_PCIINT 0x00100000 304#define SF_SISR_TXCQ_NOBUFS 0x00200000 305#define SF_SISR_RXCQ1_NOBUFS 0x00400000 306#define SF_SISR_SOFTINTR 0x00800000 307#define SF_SISR_GENTIMER 0x01000000 308#define SF_SISR_ABNORMALINTR 0x02000000 309#define SF_SISR_RSVD0 0x04000000 310#define SF_SISR_STATSOFLOW 0x08000000 311#define SF_SISR_GPIO 0xF0000000 312* 313/* Interrupt mask register / 314#define SF_IMR_PCIINT_ASSERTED 0x00000001 315#define SF_IMR_GFP_TX 0x00000002 316#define SF_IMR_GFP_RX 0x00000004 317#define SF_IMR_TX_BADID_HIPRIO 0x00000008 318#define SF_IMR_TX_BADID_LOPRIO 0x00000010 319#define SF_IMR_NO_TX_CSUM 0x00000020 320#define SF_IMR_RXDQ2_NOBUFS 0x00000040 321#define SF_IMR_RXGFP_NORESP 0x00000080 322#define SF_IMR_RXDQ1_DMADONE 0x00000100 323#define SF_IMR_RXDQ2_DMADONE 0x00000200 324#define SF_IMR_RXDQ1_EARLY 0x00000400 325#define SF_IMR_RXDQ2_EARLY 0x00000800 326#define SF_IMR_TX_QUEUEDONE 0x00001000 327#define SF_IMR_TX_DMADONE 0x00002000 328#define SF_IMR_TX_TXDONE 0x00004000 329#define SF_IMR_NORMALINTR 0x00008000 330#define SF_IMR_RXDQ1_NOBUFS 0x00010000 331#define SF_IMR_RXCQ2_NOBUFS 0x00020000 332#define SF_IMR_TX_LOFIFO 0x00040000 333#define SF_IMR_DMAERR 0x00080000 334#define SF_IMR_PCIINT 0x00100000 335#define SF_IMR_TXCQ_NOBUFS 0x00200000 336#define SF_IMR_RXCQ1_NOBUFS 0x00400000 337#define SF_IMR_SOFTINTR 0x00800000 338#define SF_IMR_GENTIMER 0x01000000 339#define SF_IMR_ABNORMALINTR 0x02000000 340#define SF_IMR_RSVD0 0x04000000 341#define SF_IMR_STATSOFLOW 0x08000000 342#define SF_IMR_GPIO 0xF0000000 343* 344#define SF_INTRS \ 345 (SF_IMR_RXDQ2_NOBUFS\|SF_IMR_RXDQ1_DMADONE\|SF_IMR_RXDQ2_DMADONE\| \ 346 SF_IMR_TX_TXDONE\|SF_IMR_RXDQ1_NOBUFS\|SF_IMR_RXDQ2_DMADONE\| \ 347 SF_IMR_NORMALINTR\|SF_IMR_ABNORMALINTR\|SF_IMR_TXCQ_NOBUFS\| \ 348 SF_IMR_RXCQ1_NOBUFS\|SF_IMR_RXCQ2_NOBUFS\|SF_IMR_STATSOFLOW) 349 350/* TX descriptor queue control registers / 351#define SF_TXDQCTL_DESCTYPE 0x00000007 352#define SF_TXDQCTL_NODMACMP 0x00000008 353#define SF_TXDQCTL_MINSPACE 0x00000070 354#define SF_TXDQCTL_64BITADDR 0x00000080 355#define SF_TXDQCTL_BURSTLEN 0x00003F00 356#define SF_TXDQCTL_SKIPLEN 0x001F0000 357#define SF_TXDQCTL_HIPRIOTHRESH 0xFF000000 358* 359#define SF_TXBUFDESC_TYPE0 0x00000000 360#define SF_TXBUFDESC_TYPE1 0x00000001 361#define SF_TXBUFDESC_TYPE2 0x00000002 362#define SF_TXBUFDESC_TYPE3 0x00000003 363#define SF_TXBUFDESC_TYPE4 0x00000004 364 365#define SF_TXMINSPACE_UNLIMIT 0x00000000 366#define SF_TXMINSPACE_32BYTES 0x00000010 367#define SF_TXMINSPACE_64BYTES 0x00000020 368#define SF_TXMINSPACE_128BYTES 0x00000030 369#define SF_TXMINSPACE_256BYTES 0x00000040 370 371#define SF_TXSKIPLEN_0BYTES 0x00000000 372#define SF_TXSKIPLEN_8BYTES 0x00010000 373#define SF_TXSKIPLEN_16BYTES 0x00020000 374#define SF_TXSKIPLEN_24BYTES 0x00030000 375#define SF_TXSKIPLEN_32BYTES 0x00040000 376 377/* TX frame control register / 378#define SF_TXFRMCTL_TXTHRESH 0x000000FF 379#define SF_TXFRMCTL_CPLAFTERTX 0x00000100 380#define SF_TXFRMCRL_DEBUG 0x0000FE00 381#define SF_TXFRMCTL_STATUS 0x01FF0000 382#define SF_TXFRMCTL_MAC_TXIF 0xFE000000 383* 384/* TX completion queue control register / 385#define SF_TXCQ_THRESH 0x0000000F 386#define SF_TXCQ_COMMON 0x00000010 387#define SF_TXCQ_SIZE 0x00000020 388#define SF_TXCQ_WRITEENB 0x00000040 389#define SF_TXCQ_USE_64BIT 0x00000080 390#define SF_TXCQ_ADDR 0xFFFFFF00 391* 392/* RX completion queue control register / 393#define SF_RXCQ_THRESH 0x0000000F 394#define SF_RXCQ_TYPE 0x00000030 395#define SF_RXCQ_WRITEENB 0x00000040 396#define SF_RXCQ_USE_64BIT 0x00000080 397#define SF_RXCQ_ADDR 0xFFFFFF00 398* 399#define SF_RXCQTYPE_0 0x00000000 400#define SF_RXCQTYPE_1 0x00000010 401#define SF_RXCQTYPE_2 0x00000020 402#define SF_RXCQTYPE_3 0x00000030 403 404/* TX descriptor queue producer index register / 405#define SF_TXDQ_PRODIDX_LOPRIO 0x000007FF 406#define SF_TXDQ_PRODIDX_HIPRIO 0x07FF0000 407* 408/* TX descriptor queue consumer index register / 409#define SF_TXDQ_CONSIDX_LOPRIO 0x000007FF 410#define SF_TXDQ_CONSIDX_HIPRIO 0x07FF0000 411* 412/* Completion queue consumer index register / 413#define SF_CQ_CONSIDX_RXQ1 0x000003FF 414#define SF_CQ_CONSIDX_RXTHRMODE 0x00008000 415#define SF_CQ_CONSIDX_TXQ 0x03FF0000 416#define SF_CQ_CONSIDX_TXTHRMODE 0x80000000 417* 418/* Completion queue producer index register / 419#define SF_CQ_PRODIDX_RXQ1 0x000003FF 420#define SF_CQ_PRODIDX_TXQ 0x03FF0000 421* 422/* RX completion queue 2 consumer/producer index register / 423#define SF_CQ_RXQ2_CONSIDX 0x000003FF 424#define SF_CQ_RXQ2_RXTHRMODE 0x00008000 425#define SF_CQ_RXQ2_PRODIDX 0x03FF0000 426* 427#define SF_CQ_RXTHRMODE_INT_ON 0x00008000 428#define SF_CQ_RXTHRMODE_INT_OFF 0x00000000 429#define SF_CQ_TXTHRMODE_INT_ON 0x80000000 430#define SF_CQ_TXTHRMODE_INT_OFF 0x00000000 431 432#define SF_IDX_LO(x) ((x) & 0x000007FF) 433#define SF_IDX_HI(x) (((x) >> 16) & 0x000007FF) 434 435/* RX DMA control register / 436#define SF_RXDMA_BURSTSIZE 0x0000007F 437#define SF_RXDMA_FPTESTMODE 0x00000080 438#define SF_RXDMA_HIPRIOTHRESH 0x00000F00 439#define SF_RXDMA_RXEARLYTHRESH 0x0001F000 440#define SF_RXDMA_DMACRC 0x00040000 441#define SF_RXDMA_USEBKUPQUEUE 0x00080000 442#define SF_RXDMA_QUEUEMODE 0x00700000 443#define SF_RXDMA_RXCQ2_ON 0x00800000 444#define SF_RXDMA_CSUMMODE 0x03000000 445#define SF_RXDMA_DMAPAUSEPKTS 0x04000000 446#define SF_RXDMA_DMACTLPKTS 0x08000000 447#define SF_RXDMA_DMACRXERRPKTS 0x10000000 448#define SF_RXDMA_DMABADPKTS 0x20000000 449#define SF_RXDMA_DMARUNTS 0x40000000 450#define SF_RXDMA_REPORTBADPKTS 0x80000000 451* 452#define SF_RXDQMODE_Q1ONLY 0x00100000 453#define SF_RXDQMODE_Q2_ON_FP 0x00200000 454#define SF_RXDQMODE_Q2_ON_SHORT 0x00300000 455#define SF_RXDQMODE_Q2_ON_PRIO 0x00400000 456#define SF_RXDQMODE_SPLITHDR 0x00500000 457 458#define SF_RXCSUMMODE_IGNORE 0x00000000 459#define SF_RXCSUMMODE_REJECT_BAD_TCP 0x01000000 460#define SF_RXCSUMMODE_REJECT_BAD_TCPUDP 0x02000000 461#define SF_RXCSUMMODE_RSVD 0x03000000 462 463/* RX descriptor queue control registers / 464#define SF_RXDQCTL_MINDESCTHR 0x0000007F 465#define SF_RXDQCTL_Q1_WE 0x00000080 466#define SF_RXDQCTL_DESCSPACE 0x00000700 467#define SF_RXDQCTL_64BITDADDR 0x00000800 468#define SF_RXDQCTL_64BITBADDR 0x00001000 469#define SF_RXDQCTL_VARIABLE 0x00002000 470#define SF_RXDQCTL_ENTRIES 0x00004000 471#define SF_RXDQCTL_PREFETCH 0x00008000 472#define SF_RXDQCTL_BUFLEN 0xFFFF0000 473* 474#define SF_DESCSPACE_4BYTES 0x00000000 475#define SF_DESCSPACE_8BYTES 0x00000100 476#define SF_DESCSPACE_16BYTES 0x00000200 477#define SF_DESCSPACE_32BYTES 0x00000300 478#define SF_DESCSPACE_64BYTES 0x00000400 479#define SF_DESCSPACE_128_BYTES 0x00000500 480 481/* RX buffer consumer/producer index registers / 482#define SF_RXDQ_PRODIDX 0x000007FF 483#define SF_RXDQ_CONSIDX 0x07FF0000 484* 485/* RX filter control register / 486#define SF_RXFILT_PROMISC 0x00000001 487#define SF_RXFILT_ALLMULTI 0x00000002 488#define SF_RXFILT_BROAD 0x00000004 489#define SF_RXFILT_HASHPRIO 0x00000008 490#define SF_RXFILT_HASHMODE 0x00000030 491#define SF_RXFILT_PERFMODE 0x000000C0 492#define SF_RXFILT_VLANMODE 0x00000300 493#define SF_RXFILT_WAKEMODE 0x00000C00 494#define SF_RXFILT_MULTI_NOBROAD 0x00001000 495#define SF_RXFILT_MIN_VLANPRIO 0x0000E000 496#define SF_RXFILT_PEFECTPRIO 0xFFFF0000 497* 498/* Hash filtering mode / 499#define SF_HASHMODE_OFF 0x00000000 500#define SF_HASHMODE_WITHVLAN 0x00000010 501#define SF_HASHMODE_ANYVLAN 0x00000020 502#define SF_HASHMODE_ANY 0x00000030 503* 504/* Perfect filtering mode / 505#define SF_PERFMODE_OFF 0x00000000 506#define SF_PERFMODE_NORMAL 0x00000040 507#define SF_PERFMODE_INVERSE 0x00000080 508#define SF_PERFMODE_VLAN 0x000000C0 509* 510/* VLAN mode / 511#define SF_VLANMODE_OFF 0x00000000 512#define SF_VLANMODE_NOSTRIP 0x00000100 513#define SF_VLANMODE_STRIP 0x00000200 514#define SF_VLANMODE_RSVD 0x00000300 515* 516/* Wakeup mode / 517#define SF_WAKEMODE_OFF 0x00000000 518#define SF_WAKEMODE_FILTER 0x00000400 519#define SF_WAKEMODE_FP 0x00000800 520#define SF_WAKEMODE_HIPRIO 0x00000C00 521* 522/* 523 * Extra PCI registers 0x0100 to 0x0FFF 524 / 525#define SF_PCI_TARGSTAT 0x0100 526#define SF_PCI_MASTSTAT1 0x0104 527#define SF_PCI_MASTSTAT2 0x0108 528#define SF_PCI_DMAHOSTADDR_LO 0x010C 529#define SF_BAC_DMADIAG0 0x0110 530#define SF_BAC_DMADIAG1 0x0114 531#define SF_BAC_DMADIAG2 0x0118 532#define SF_BAC_DMADIAG3 0x011C 533#define SF_PAR0 0x0120 534#define SF_PAR1 0x0124 535#define SF_PCICB_FUNCEVENT 0x0130 536#define SF_PCICB_FUNCEVENT_MASK 0x0134 537#define SF_PCICB_FUNCSTATE 0x0138 538#define SF_PCICB_FUNCFORCE 0x013C 539* 540/* 541 * Serial EEPROM registers 0x1000 to 0x1FFF 542 * Presumeably the EEPROM is mapped into this 8K window. 543 / 544#define SF_EEADDR_BASE 0x1000 545#define SF_EEADDR_MAX 0x1FFF 546* 547#define SF_EE_NODEADDR 14 548 549/* 550 * MII registers registers 0x2000 to 0x3FFF 551 * There are 32 sets of 32 registers, one set for each possible 552 * PHY address. Each 32 bit register is split into a 16-bit data 553 * port and a couple of status bits. 554 / 555* 556#define SF_MIIADDR_BASE 0x2000 557#define SF_MIIADDR_MAX 0x3FFF 558#define SF_MII_BLOCKS 32 559 560#define SF_MII_DATAVALID 0x80000000 561#define SF_MII_BUSY 0x40000000 562#define SF_MII_DATAPORT 0x0000FFFF 563 564#define SF_PHY_REG(phy, reg) \ 565 (SF_MIIADDR_BASE + (phy * SF_MII_BLOCKS * sizeof(u_int32_t)) + \ 566 (reg * sizeof(u_int32_t))) 567 568/* 569 * Ethernet extra registers 0x4000 to 0x4FFF 570 / 571#define SF_TESTMODE 0x4000 572#define SF_RX_FRAMEPROC_CTL 0x4004 573#define SF_TX_FRAMEPROC_CTL 0x4008 574* 575/* 576 * MAC registers 0x5000 to 0x5FFF 577 / 578#define SF_MACCFG_1 0x5000 579#define SF_MACCFG_2 0x5004 580#define SF_BKTOBKIPG 0x5008 581#define SF_NONBKTOBKIPG 0x500C 582#define SF_COLRETRY 0x5010 583#define SF_MAXLEN 0x5014 584#define SF_TXNIBBLECNT 0x5018 585#define SF_TXBYTECNT 0x501C 586#define SF_RETXCNT 0x5020 587#define SF_RANDNUM 0x5024 588#define SF_RANDNUM_MASK 0x5028 589#define SF_TOTALTXCNT 0x5034 590#define SF_RXBYTECNT 0x5040 591#define SF_TXPAUSETIMER 0x5060 592#define SF_VLANTYPE 0x5064 593#define SF_MIISTATUS 0x5070 594* 595#define SF_MACCFG1_HUGEFRAMES 0x00000001 596#define SF_MACCFG1_FULLDUPLEX 0x00000002 597#define SF_MACCFG1_AUTOPAD 0x00000004 598#define SF_MACCFG1_HDJAM 0x00000008 599#define SF_MACCFG1_DELAYCRC 0x00000010 600#define SF_MACCFG1_NOBACKOFF 0x00000020 601#define SF_MACCFG1_LENGTHCHECK 0x00000040 602#define SF_MACCFG1_PUREPREAMBLE 0x00000080 603#define SF_MACCFG1_PASSALLRX 0x00000100 604#define SF_MACCFG1_PREAM_DETCNT 0x00000200 605#define SF_MACCFG1_RX_FLOWENB 0x00000400 606#define SF_MACCFG1_TX_FLOWENB 0x00000800 607#define SF_MACCFG1_TESTMODE 0x00003000 608#define SF_MACCFG1_MIILOOPBK 0x00004000 609#define SF_MACCFG1_SOFTRESET 0x00008000 610 611/* 612 * RX filter registers 0x6000 to 0x6FFF 613 / 614#define SF_RXFILT_PERFECT_BASE 0x6000 615#define SF_RXFILT_PERFECT_MAX 0x60FF 616#define SF_RXFILT_PERFECT_SKIP 0x0010 617#define SF_RXFILT_PERFECT_CNT 0x0010 618* 619#define SF_RXFILT_HASH_BASE 0x6100 620#define SF_RXFILT_HASH_MAX 0x62FF 621#define SF_RXFILT_HASH_SKIP 0x0010 622#define SF_RXFILT_HASH_CNT 0x001F 623#define SF_RXFILT_HASH_ADDROFF 0x0000 624#define SF_RXFILT_HASH_PRIOOFF 0x0004 625#define SF_RXFILT_HASH_VLANOFF 0x0008 626 627/* 628 * Statistics registers 0x7000 to 0x7FFF 629 / 630#define SF_STATS_BASE 0x7000 631#define SF_STATS_END 0x7FFF 632* 633/* 634 * TX frame processor instruction space 0x8000 to 0x9FFF 635 / 636* 637/* 638 * RX frame processor instruction space 0xA000 to 0xBFFF 639 / 640* 641/* 642 * Ethernet FIFO access space 0xC000 to 0xDFFF 643 / 644* 645/* 646 * Reserved 0xE000 to 0xFFFF 647 / 648* 649/* 650 * Descriptor data structures. 651 / 652* 653 654/* Receive descriptor formats. / 655#define SF_RX_MINSPACING 8 656#define SF_RX_DLIST_CNT 256 657#define SF_RX_CLIST_CNT 1024 658#define SF_RX_HOSTADDR(x) (((x) >> 2) & 0x3FFFFFFF) 659* 660/* 661 * RX buffer descriptor type 0, 32-bit addressing. Note that we 662 * program the RX buffer queue control register(s) to allow a 663 * descriptor spacing of 16 bytes, which leaves room after each 664 * descriptor to store a pointer to the mbuf for each buffer. 665 / 666struct sf_rx_bufdesc_type0 { 667* u_int32_t sf_valid:1, 668 sf_end:1, 669 sf_addrlo:30; 670 u_int32_t sf_pad0; 671#ifdef __i386__ 672 u_int32_t sf_pad1; 673#endif 674 struct mbuf sf_mbuf; 675}; 676* 677/* 678 * RX buffer descriptor type 0, 64-bit addressing. 679 / 680struct sf_rx_bufdesc_type1 { 681* u_int32_t sf_valid:1, 682 sf_end:1, 683 sf_addrlo:30; 684 u_int32_t sf_addrhi; 685#ifdef __i386__ 686 u_int32_t sf_pad; 687#endif 688 struct mbuf sf_mbuf; 689}; 690* 691/* 692 * RX completion descriptor, type 0 (short). 693 / 694struct sf_rx_cmpdesc_type0 { 695* u_int32_t sf_len:16, 696 sf_endidx:11, 697 sf_status1:3, 698 sf_id:2; 699}; 700 701/* 702 * RX completion descriptor, type 1 (basic). Includes vlan ID 703 * if this is a vlan-addressed packet, plus extended status. 704 / 705struct sf_rx_cmpdesc_type1 { 706* u_int32_t sf_len:16, 707 sf_endidx:11, 708 sf_status1:3, 709 sf_id:2; 710 u_int16_t sf_status2; 711 u_int16_t sf_vlanid; 712}; 713 714/* 715 * RX completion descriptor, type 2 (checksum). Includes partial TCP/IP 716 * checksum instead of vlan tag, plus extended status. 717 / 718struct sf_rx_cmpdesc_type2 { 719* u_int32_t sf_len:16, 720 sf_endidx:11, 721 sf_status1:3, 722 sf_id:2; 723 u_int16_t sf_status2; 724 u_int16_t sf_cksum; 725}; 726 727/* 728 * RX completion descriptor type 3 (full). Includes timestamp, partial 729 * TCP/IP checksum, vlan tag plus priority, two extended status fields. 730 / 731struct sf_rx_cmpdesc_type3 { 732* u_int32_t sf_len:16, 733 sf_endidx:11, 734 sf_status1:3, 735 sf_id:2; 736 u_int32_t sf_startidx:10, 737 sf_status3:6, 738 sf_status2:16; 739 u_int16_t sf_cksum; 740 u_int16_t sf_vlanid_prio; 741 u_int32_t sf_timestamp; 742}; 743 744#define SF_RXSTAT1_QUEUE 0x1 745#define SF_RXSTAT1_FIFOFULL 0x2 746#define SF_RXSTAT1_OK 0x4 747 748 /* 0=unknown,5=unsupported / 749#define SF_RXSTAT2_FRAMETYPE 0x0007 / 1=IPv4,2=IPv2,3=IPX,4=ICMP / 750#define SF_RXSTAT2_UDP 0x0008 751#define SF_RXSTAT2_TCP 0x0010 752#define SF_RXSTAT2_FRAG 0x0020 753#define SF_RXSTAT2_PCSUM_OK 0x0040 / partial checksum ok / 754#define SF_RXSTAT2_CSUM_BAD 0x0080 / TCP/IP checksum bad / 755#define SF_RXSTAT2_CSUM_OK 0x0100 / TCP/IP checksum ok / 756#define SF_RXSTAT2_VLAN 0x0200 757#define SF_RXSTAT2_BADRXCODE 0x0400 758#define SF_RXSTAT2_DRIBBLE 0x0800 759#define SF_RXSTAT2_ISL_CRCERR 0x1000 760#define SF_RXSTAT2_CRCERR 0x2000 761#define SF_RXSTAT2_HASH 0x4000 762#define SF_RXSTAT2_PERFECT 0x8000 763* 764#define SF_RXSTAT3_TRAILER 0x01 765#define SF_RXSTAT3_HEADER 0x02 766#define SF_RXSTAT3_CONTROL 0x04 767#define SF_RXSTAT3_PAUSE 0x08 768#define SF_RXSTAT3_ISL 0x10 769 770/* 771 * Transmit descriptor formats. 772 * Each transmit descriptor type allows for a skip field at the 773 * start of each structure. The size of the skip field can vary, 774 * however we always set it for 8 bytes, which is enough to hold 775 * a pointer (32 bits on x86, 64-bits on alpha) that we can use 776 * to hold the address of the head of the mbuf chain for the 777 * frame or fragment associated with the descriptor. This saves 778 * us from having to create a separate pointer array to hold 779 * the mbuf addresses. 780 / 781#define SF_TX_BUFDESC_ID 0xB 782#define SF_MAXFRAGS 14 783#define SF_TX_MINSPACING 128 784#define SF_TX_DLIST_CNT 128 785#define SF_TX_DLIST_SIZE 16384 786#define SF_TX_SKIPLEN 1 787#define SF_TX_CLIST_CNT 1024 788* 789struct sf_frag { 790 u_int32_t sf_addr; 791 u_int16_t sf_fraglen; 792 u_int16_t sf_pktlen; 793}; 794 795struct sf_frag_msdos { 796 u_int16_t sf_pktlen; 797 u_int16_t sf_fraglen; 798 u_int32_t sf_addr; 799}; 800 801/* 802 * TX frame descriptor type 0, 32-bit addressing. One descriptor can 803 * be used to map multiple packet fragments. We use this format since 804 * BSD networking fragments packet data across mbuf chains. Note that 805 * the number of fragments can be variable depending on how the descriptor 806 * spacing is specified in the TX descriptor queue control register. 807 * We always use a spacing of 128 bytes, and a skipfield length of 8 808 * bytes: this means 16 bytes for the descriptor, including the skipfield, 809 * with 121 bytes left for fragment maps. Each fragment requires 8 bytes, 810 * which allows for 14 fragments per descriptor. The total size of the 811 * transmit buffer queue is limited to 16384 bytes, so with a spacing of 812 * 128 bytes per descriptor, we have room for 128 descriptors in the queue. 813 / 814struct sf_tx_bufdesc_type0 { 815#ifdef __i386__ 816* u_int32_t sf_pad; 817#endif 818 struct mbuf sf_mbuf; 819* u_int32_t sf_rsvd0:24, 820 sf_crcen:1, 821 sf_caltcp:1, 822 sf_end:1, 823 sf_intr:1, 824 sf_id:4; 825 u_int8_t sf_fragcnt; 826 u_int8_t sf_rsvd2; 827 u_int16_t sf_rsvd1; 828 struct sf_frag sf_frags[14]; 829}; 830 831/* 832 * TX buffer descriptor type 1, 32-bit addressing. Each descriptor 833 * maps a single fragment. 834 / 835struct sf_tx_bufdesc_type1 { 836#ifdef __i386__ 837* u_int32_t sf_pad; 838#endif 839 struct mbuf sf_mbuf; 840* u_int32_t sf_fraglen:16, 841 sf_fragcnt:8, 842 sf_crcen:1, 843 sf_caltcp:1, 844 sf_end:1, 845 sf_intr:1, 846 sf_id:4; 847 u_int32_t sf_addr; 848}; 849 850/* 851 * TX buffer descriptor type 2, 64-bit addressing. Each descriptor 852 * maps a single fragment. 853 / 854struct sf_tx_bufdesc_type2 { 855#ifdef __i386__ 856* u_int32_t sf_pad; 857#endif 858 struct mbuf sf_mbuf; 859* u_int32_t sf_fraglen:16, 860 sf_fragcnt:8, 861 sf_crcen:1, 862 sf_caltcp:1, 863 sf_end:1, 864 sf_intr:1, 865 sf_id:4; 866 u_int32_t sf_addrlo; 867 u_int32_t sf_addrhi; 868}; 869 870/* TX buffer descriptor type 3 is not defined. / 871* 872/* 873 * TX frame descriptor type 4, 32-bit addressing. This is a special 874 * case of the type 0 descriptor, identical except that the fragment 875 * address and length fields are ordered differently. This is done 876 * to optimize copies in MS-DOS and OS/2 drivers. 877 / 878struct sf_tx_bufdesc_type4 { 879#ifdef __i386__ 880* u_int32_t sf_pad; 881#endif 882 struct mbuf sf_mbuf; 883* u_int32_t sf_rsvd0:24, 884 sf_crcen:1, 885 sf_caltcp:1, 886 sf_end:1, 887 sf_intr:1, 888 sf_id:4; 889 u_int8_t sf_fragcnt; 890 u_int8_t sf_rsvd2; 891 u_int16_t sf_rsvd1; 892 struct sf_frag_msdos sf_frags[14]; 893}; 894 895/* 896 * Transmit completion queue descriptor formats. 897 / 898* 899/* 900 * Transmit DMA completion descriptor, type 0. 901 / 902#define SF_TXCMPTYPE_DMA 0x4 903struct sf_tx_cmpdesc_type0 { 904* u_int32_t sf_index:15, 905 sf_priority:1, 906 sf_timestamp:13, 907 sf_type:3; 908}; 909 910/* 911 * Transmit completion descriptor, type 1. 912 / 913#define SF_TXCMPTYPE_TX 0x5 914struct sf_tx_cmpdesc_type1 { 915* u_int32_t sf_index:15, 916 sf_priority:1, 917 sf_txstat:13, 918 sf_type:3; 919}; 920 921#define SF_TXSTAT_CRCERR 0x0001 922#define SF_TXSTAT_LENCHECKERR 0x0002 923#define SF_TXSTAT_LENRANGEERR 0x0004 924#define SF_TXSTAT_TX_OK 0x0008 925#define SF_TXSTAT_TX_DEFERED 0x0010 926#define SF_TXSTAT_EXCESS_DEFER 0x0020 927#define SF_TXSTAT_EXCESS_COLL 0x0040 928#define SF_TXSTAT_LATE_COLL 0x0080 929#define SF_TXSTAT_TOOBIG 0x0100 930#define SF_TXSTAT_TX_UNDERRUN 0x0200 931#define SF_TXSTAT_CTLFRAME_OK 0x0400 932#define SF_TXSTAT_PAUSEFRAME_OK 0x0800 933#define SF_TXSTAT_PAUSED 0x1000 934 935/* Statistics counters. / 936struct sf_stats { 937* u_int32_t sf_tx_frames; 938 u_int32_t sf_tx_single_colls; 939 u_int32_t sf_tx_multi_colls; 940 u_int32_t sf_tx_crcerrs; 941 u_int32_t sf_tx_bytes; 942 u_int32_t sf_tx_defered; 943 u_int32_t sf_tx_late_colls; 944 u_int32_t sf_tx_pause_frames; 945 u_int32_t sf_tx_control_frames; 946 u_int32_t sf_tx_excess_colls; 947 u_int32_t sf_tx_excess_defer; 948 u_int32_t sf_tx_mcast_frames; 949 u_int32_t sf_tx_bcast_frames; 950 u_int32_t sf_tx_frames_lost; 951 u_int32_t sf_rx_rx_frames; 952 u_int32_t sf_rx_crcerrs; 953 u_int32_t sf_rx_alignerrs; 954 u_int32_t sf_rx_bytes; 955 u_int32_t sf_rx_control_frames; 956 u_int32_t sf_rx_unsup_control_frames; 957 u_int32_t sf_rx_giants; 958 u_int32_t sf_rx_runts; 959 u_int32_t sf_rx_jabbererrs; 960 u_int32_t sf_rx_pkts_64; 961 u_int32_t sf_rx_pkts_65_127; 962 u_int32_t sf_rx_pkts_128_255; 963 u_int32_t sf_rx_pkts_256_511; 964 u_int32_t sf_rx_pkts_512_1023; 965 u_int32_t sf_rx_pkts_1024_1518; 966 u_int32_t sf_rx_frames_lost; 967 u_int16_t sf_tx_underruns; 968 u_int16_t sf_pad; 969}; 970 971/* 972 * register space access macros 973 / 974#define CSR_WRITE_4(sc, reg, val) \ 975* bus_space_write_4(sc->sf_btag, sc->sf_bhandle, reg, val) 976 977#define CSR_READ_4(sc, reg) \ 978 bus_space_read_4(sc->sf_btag, sc->sf_bhandle, reg) 979 980#define CSR_READ_1(sc, reg) \ 981 bus_space_read_1(sc->sf_btag, sc->sf_bhandle, reg) 982 983 984struct sf_type { 985 u_int16_t sf_vid; 986 u_int16_t sf_did; 987 char sf_name; 988}; 989* 990#define SF_INC(x, y) (x) = (x + 1) % y 991 992#define ETHER_ALIGN 2 993 994/* 995 * Note: alignment is important here: each list must be aligned to 996 * a 256-byte boundary. It turns out that each ring is some multiple 997 * of 4K in length, so we can stack them all on top of each other 998 * and just worry about aligning the whole mess. There's one transmit 999 * buffer ring and two receive buffer rings: one RX ring is for small 1000 * packets and the other is for large packets. Each buffer ring also 1001 * has a companion completion queue. 1002 / 1003struct sf_list_data { 1004* struct sf_tx_bufdesc_type0 sf_tx_dlist[SF_TX_DLIST_CNT]; 1005 struct sf_tx_cmpdesc_type1 sf_tx_clist[SF_TX_CLIST_CNT]; 1006 struct sf_rx_bufdesc_type0 sf_rx_dlist_big[SF_RX_DLIST_CNT]; 1007#ifdef notdef 1008 /* 1009 * Unfortunately, because the Starfire doesn't allow arbitrary 1010 * byte alignment, we have to copy packets in the RX handler in 1011 * order to align the payload correctly. This means that we 1012 * don't gain anything by having separate large and small descriptor 1013 * lists, so for now we don't bother with the small one. 1014 / 1015* struct sf_rx_bufdesc_type0 sf_rx_dlist_small[SF_RX_DLIST_CNT]; 1016#endif 1017 struct sf_rx_cmpdesc_type3 sf_rx_clist[SF_RX_CLIST_CNT]; 1018}; 1019 1020struct sf_softc { 1021 struct arpcom arpcom; /* interface info / 1022* bus_space_handle_t sf_bhandle; /* bus space handle / 1023* bus_space_tag_t sf_btag; /* bus space tag / 1024* void sf_intrhand; / interrupt handler cookie / 1025* struct resource sf_irq; / irq resource descriptor / 1026* struct resource sf_res; / mem/ioport resource / 1027* struct sf_type sf_info; / Starfire adapter info / 1028* device_t sf_miibus; 1029 u_int8_t sf_unit; /* interface number / 1030* struct sf_list_data sf_ldata; 1031* int sf_tx_cnt; 1032 struct callout_handle sf_stat_ch; 1033}; 1034 1035#define SF_TIMEOUT 1000 1036 1037#ifdef __alpha__ 1038#undef vtophys 1039#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1040#endif	72#define AD_SUBSYSID_62020 0x0020 /* single port 10/100baseFX 64-bit / 73#define AD_SUBSYSID_69011 0x0028 / single port 10/100baseTX 32-bit / 74 75/ 76 * Starfire internal register space map. The entire register space 77 * is available using PCI memory mapped mode. The SF_RMAP_INTREG 78 * space is available using PCI I/O mode. The entire space can be 79 * accessed using indirect I/O using the indirect I/O addr and 80 * indirect I/O data registers located within the SF_RMAP_INTREG space. 81 / 82#define SF_RMAP_ROMADDR_BASE 0x00000 / Expansion ROM space / 83#define SF_RMAP_ROMADDR_MAX 0x3FFFF 84 85#define SF_RMAP_EXGPIO_BASE 0x40000 / External general purpose regs / 86#define SF_RMAP_EXGPIO_MAX 0x3FFFF 87 88#define SF_RMAP_INTREG_BASE 0x50000 / Internal functional registers / 89#define SF_RMAP_INTREG_MAX 0x500FF 90#define SF_RMAP_GENREG_BASE 0x50100 / General purpose registers / 91#define SF_RMAP_GENREG_MAX 0x5FFFF 92 93#define SF_RMAP_FIFO_BASE 0x60000 94#define SF_RMAP_FIFO_MAX 0x6FFFF 95 96#define SF_RMAP_STS_BASE 0x70000 97#define SF_RMAP_STS_MAX 0x70083 98 99#define SF_RMAP_RSVD_BASE 0x70084 100#define SF_RMAP_RSVD_MAX 0x7FFFF 101* 102/* 103 * PCI config header registers, 0x0000 to 0x003F 104 / 105#define SF_PCI_VENDOR_ID 0x0000 106#define SF_PCI_DEVICE_ID 0x0002 107#define SF_PCI_COMMAND 0x0004 108#define SF_PCI_STATUS 0x0006 109#define SF_PCI_REVID 0x0008 110#define SF_PCI_CLASSCODE 0x0009 111#define SF_PCI_CACHELEN 0x000C 112#define SF_PCI_LATENCY_TIMER 0x000D 113#define SF_PCI_HEADER_TYPE 0x000E 114#define SF_PCI_LOMEM 0x0010 115#define SF_PCI_LOIO 0x0014 116#define SF_PCI_SUBVEN_ID 0x002C 117#define SF_PCI_SYBSYS_ID 0x002E 118#define SF_PCI_BIOSROM 0x0030 119#define SF_PCI_INTLINE 0x003C 120#define SF_PCI_INTPIN 0x003D 121#define SF_PCI_MINGNT 0x003E 122#define SF_PCI_MINLAT 0x003F 123* 124/* 125 * PCI registers, 0x0040 to 0x006F 126 / 127#define SF_PCI_DEVCFG 0x0040 128#define SF_BACCTL 0x0044 129#define SF_PCI_MON1 0x0048 130#define SF_PCI_MON2 0x004C 131#define SF_PCI_CAPID 0x0050 / 8 bits / 132#define SF_PCI_NEXTPTR 0x0051 / 8 bits / 133#define SF_PCI_PWRMGMTCAP 0x0052 / 16 bits / 134#define SF_PCI_PWRMGMTCTRL 0x0054 / 16 bits / 135#define SF_PCI_PME_EVENT 0x0058 136#define SF_PCI_EECTL 0x0060 137#define SF_PCI_COMPLIANCE 0x0064 138#define SF_INDIRECTIO_ADDR 0x0068 139#define SF_INDIRECTIO_DATA 0x006C 140* 141#define SF_PCIDEVCFG_RESET 0x00000001 142#define SF_PCIDEVCFG_FORCE64 0x00000002 143#define SF_PCIDEVCFG_SYSTEM64 0x00000004 144#define SF_PCIDEVCFG_RSVD0 0x00000008 145#define SF_PCIDEVCFG_INCR_INB 0x00000010 146#define SF_PCIDEVCFG_ABTONPERR 0x00000020 147#define SF_PCIDEVCFG_STPONPERR 0x00000040 148#define SF_PCIDEVCFG_MR_ENB 0x00000080 149#define SF_PCIDEVCFG_FIFOTHR 0x00000F00 150#define SF_PCIDEVCFG_STPONCA 0x00001000 151#define SF_PCIDEVCFG_PCIMEN 0x00002000 /* enable PCI bus master / 152#define SF_PCIDEVCFG_LATSTP 0x00004000 153#define SF_PCIDEVCFG_BYTE_ENB 0x00008000 154#define SF_PCIDEVCFG_EECSWIDTH 0x00070000 155#define SF_PCIDEVCFG_STPMWCA 0x00080000 156#define SF_PCIDEVCFG_REGCSWIDTH 0x00700000 157#define SF_PCIDEVCFG_INTR_ENB 0x00800000 158#define SF_PCIDEVCFG_DPR_ENB 0x01000000 159#define SF_PCIDEVCFG_RSVD1 0x02000000 160#define SF_PCIDEVCFG_RSVD2 0x04000000 161#define SF_PCIDEVCFG_STA_ENB 0x08000000 162#define SF_PCIDEVCFG_RTA_ENB 0x10000000 163#define SF_PCIDEVCFG_RMA_ENB 0x20000000 164#define SF_PCIDEVCFG_SSE_ENB 0x40000000 165#define SF_PCIDEVCFG_DPE_ENB 0x80000000 166* 167#define SF_BACCTL_BACDMA_ENB 0x00000001 168#define SF_BACCTL_PREFER_RXDMA 0x00000002 169#define SF_BACCTL_PREFER_TXDMA 0x00000004 170#define SF_BACCTL_SINGLE_DMA 0x00000008 171#define SF_BACCTL_SWAPMODE_DATA 0x00000030 172#define SF_BACCTL_SWAPMODE_DESC 0x000000C0 173 174#define SF_SWAPMODE_LE 0x00000000 175#define SF_SWAPMODE_BE 0x00000010 176 177#define SF_PSTATE_MASK 0x0003 178#define SF_PSTATE_D0 0x0000 179#define SF_PSTATE_D1 0x0001 180#define SF_PSTATE_D2 0x0002 181#define SF_PSTATE_D3 0x0003 182#define SF_PME_EN 0x0010 183#define SF_PME_STATUS 0x8000 184 185 186/* 187 * Ethernet registers 0x0070 to 0x00FF 188 / 189#define SF_GEN_ETH_CTL 0x0070 190#define SF_TIMER_CTL 0x0074 191#define SF_CURTIME 0x0078 192#define SF_ISR 0x0080 193#define SF_ISR_SHADOW 0x0084 194#define SF_IMR 0x0088 195#define SF_GPIO 0x008C 196#define SF_TXDQ_CTL 0x0090 197#define SF_TXDQ_ADDR_HIPRIO 0x0094 198#define SF_TXDQ_ADDR_LOPRIO 0x0098 199#define SF_TXDQ_ADDR_HIADDR 0x009C 200#define SF_TXDQ_PRODIDX 0x00A0 201#define SF_TXDQ_CONSIDX 0x00A4 202#define SF_TXDMA_STS1 0x00A8 203#define SF_TXDMA_STS2 0x00AC 204#define SF_TX_FRAMCTL 0x00B0 205#define SF_TXCQ_ADDR_HI 0x00B4 206#define SF_TXCQ_CTL 0x00B8 207#define SF_RXCQ_CTL_1 0x00BC 208#define SF_RXCQ_CTL_2 0x00C0 209#define SF_CQ_CONSIDX 0x00C4 210#define SF_CQ_PRODIDX 0x00C8 211#define SF_CQ_RXQ2 0x00CC 212#define SF_RXDMA_CTL 0x00D0 213#define SF_RXDQ_CTL_1 0x00D4 214#define SF_RXDQ_CTL_2 0x00D8 215#define SF_RXDQ_ADDR_HIADDR 0x00DC 216#define SF_RXDQ_ADDR_Q1 0x00E0 217#define SF_RXDQ_ADDR_Q2 0x00E4 218#define SF_RXDQ_PTR_Q1 0x00E8 219#define SF_RXDQ_PTR_Q2 0x00EC 220#define SF_RXDMA_STS 0x00F0 221#define SF_RXFILT 0x00F4 222#define SF_RX_FRAMETEST_OUT 0x00F8 223* 224/* Ethernet control register / 225#define SF_ETHCTL_RX_ENB 0x00000001 226#define SF_ETHCTL_TX_ENB 0x00000002 227#define SF_ETHCTL_RXDMA_ENB 0x00000004 228#define SF_ETHCTL_TXDMA_ENB 0x00000008 229#define SF_ETHCTL_RXGFP_ENB 0x00000010 230#define SF_ETHCTL_TXGFP_ENB 0x00000020 231#define SF_ETHCTL_SOFTINTR 0x00000800 232* 233/* Timer control register / 234#define SF_TIMER_IMASK_INTERVAL 0x0000001F 235#define SF_TIMER_IMASK_MODE 0x00000060 236#define SF_TIMER_SMALLFRAME_BYP 0x00000100 237#define SF_TIMER_SMALLRX_FRAME 0x00000600 238#define SF_TIMER_TIMES_TEN 0x00000800 239#define SF_TIMER_RXHIPRIO_BYP 0x00001000 240#define SF_TIMER_TX_DMADONE_DLY 0x00002000 241#define SF_TIMER_TX_QDONE_DLY 0x00004000 242#define SF_TIMER_TX_FRDONE_DLY 0x00008000 243#define SF_TIMER_GENTIMER 0x00FF0000 244#define SF_TIMER_ONESHOT 0x01000000 245#define SF_TIMER_GENTIMER_RES 0x02000000 246#define SF_TIMER_TIMEST_RES 0x04000000 247#define SF_TIMER_RXQ2DONE_DLY 0x10000000 248#define SF_TIMER_EARLYRX2_DLY 0x20000000 249#define SF_TIMER_RXQ1DONE_DLY 0x40000000 250#define SF_TIMER_EARLYRX1_DLY 0x80000000 251* 252/* Interrupt status register / 253#define SF_ISR_PCIINT_ASSERTED 0x00000001 254#define SF_ISR_GFP_TX 0x00000002 255#define SF_ISR_GFP_RX 0x00000004 256#define SF_ISR_TX_BADID_HIPRIO 0x00000008 257#define SF_ISR_TX_BADID_LOPRIO 0x00000010 258#define SF_ISR_NO_TX_CSUM 0x00000020 259#define SF_ISR_RXDQ2_NOBUFS 0x00000040 260#define SF_ISR_RXGFP_NORESP 0x00000080 261#define SF_ISR_RXDQ1_DMADONE 0x00000100 262#define SF_ISR_RXDQ2_DMADONE 0x00000200 263#define SF_ISR_RXDQ1_EARLY 0x00000400 264#define SF_ISR_RXDQ2_EARLY 0x00000800 265#define SF_ISR_TX_QUEUEDONE 0x00001000 266#define SF_ISR_TX_DMADONE 0x00002000 267#define SF_ISR_TX_TXDONE 0x00004000 268#define SF_ISR_NORMALINTR 0x00008000 269#define SF_ISR_RXDQ1_NOBUFS 0x00010000 270#define SF_ISR_RXCQ2_NOBUFS 0x00020000 271#define SF_ISR_TX_LOFIFO 0x00040000 272#define SF_ISR_DMAERR 0x00080000 273#define SF_ISR_PCIINT 0x00100000 274#define SF_ISR_TXCQ_NOBUFS 0x00200000 275#define SF_ISR_RXCQ1_NOBUFS 0x00400000 276#define SF_ISR_SOFTINTR 0x00800000 277#define SF_ISR_GENTIMER 0x01000000 278#define SF_ISR_ABNORMALINTR 0x02000000 279#define SF_ISR_RSVD0 0x04000000 280#define SF_ISR_STATSOFLOW 0x08000000 281#define SF_ISR_GPIO 0xF0000000 282* 283/* 284 * Shadow interrupt status register. Unlike the normal IRQ register, 285 * reading bits here does not automatically cause them to reset. 286 / 287#define SF_SISR_PCIINT_ASSERTED 0x00000001 288#define SF_SISR_GFP_TX 0x00000002 289#define SF_SISR_GFP_RX 0x00000004 290#define SF_SISR_TX_BADID_HIPRIO 0x00000008 291#define SF_SISR_TX_BADID_LOPRIO 0x00000010 292#define SF_SISR_NO_TX_CSUM 0x00000020 293#define SF_SISR_RXDQ2_NOBUFS 0x00000040 294#define SF_SISR_RXGFP_NORESP 0x00000080 295#define SF_SISR_RXDQ1_DMADONE 0x00000100 296#define SF_SISR_RXDQ2_DMADONE 0x00000200 297#define SF_SISR_RXDQ1_EARLY 0x00000400 298#define SF_SISR_RXDQ2_EARLY 0x00000800 299#define SF_SISR_TX_QUEUEDONE 0x00001000 300#define SF_SISR_TX_DMADONE 0x00002000 301#define SF_SISR_TX_TXDONE 0x00004000 302#define SF_SISR_NORMALINTR 0x00008000 303#define SF_SISR_RXDQ1_NOBUFS 0x00010000 304#define SF_SISR_RXCQ2_NOBUFS 0x00020000 305#define SF_SISR_TX_LOFIFO 0x00040000 306#define SF_SISR_DMAERR 0x00080000 307#define SF_SISR_PCIINT 0x00100000 308#define SF_SISR_TXCQ_NOBUFS 0x00200000 309#define SF_SISR_RXCQ1_NOBUFS 0x00400000 310#define SF_SISR_SOFTINTR 0x00800000 311#define SF_SISR_GENTIMER 0x01000000 312#define SF_SISR_ABNORMALINTR 0x02000000 313#define SF_SISR_RSVD0 0x04000000 314#define SF_SISR_STATSOFLOW 0x08000000 315#define SF_SISR_GPIO 0xF0000000 316* 317/* Interrupt mask register / 318#define SF_IMR_PCIINT_ASSERTED 0x00000001 319#define SF_IMR_GFP_TX 0x00000002 320#define SF_IMR_GFP_RX 0x00000004 321#define SF_IMR_TX_BADID_HIPRIO 0x00000008 322#define SF_IMR_TX_BADID_LOPRIO 0x00000010 323#define SF_IMR_NO_TX_CSUM 0x00000020 324#define SF_IMR_RXDQ2_NOBUFS 0x00000040 325#define SF_IMR_RXGFP_NORESP 0x00000080 326#define SF_IMR_RXDQ1_DMADONE 0x00000100 327#define SF_IMR_RXDQ2_DMADONE 0x00000200 328#define SF_IMR_RXDQ1_EARLY 0x00000400 329#define SF_IMR_RXDQ2_EARLY 0x00000800 330#define SF_IMR_TX_QUEUEDONE 0x00001000 331#define SF_IMR_TX_DMADONE 0x00002000 332#define SF_IMR_TX_TXDONE 0x00004000 333#define SF_IMR_NORMALINTR 0x00008000 334#define SF_IMR_RXDQ1_NOBUFS 0x00010000 335#define SF_IMR_RXCQ2_NOBUFS 0x00020000 336#define SF_IMR_TX_LOFIFO 0x00040000 337#define SF_IMR_DMAERR 0x00080000 338#define SF_IMR_PCIINT 0x00100000 339#define SF_IMR_TXCQ_NOBUFS 0x00200000 340#define SF_IMR_RXCQ1_NOBUFS 0x00400000 341#define SF_IMR_SOFTINTR 0x00800000 342#define SF_IMR_GENTIMER 0x01000000 343#define SF_IMR_ABNORMALINTR 0x02000000 344#define SF_IMR_RSVD0 0x04000000 345#define SF_IMR_STATSOFLOW 0x08000000 346#define SF_IMR_GPIO 0xF0000000 347* 348#define SF_INTRS \ 349 (SF_IMR_RXDQ2_NOBUFS\|SF_IMR_RXDQ1_DMADONE\|SF_IMR_RXDQ2_DMADONE\| \ 350 SF_IMR_TX_TXDONE\|SF_IMR_RXDQ1_NOBUFS\|SF_IMR_RXDQ2_DMADONE\| \ 351 SF_IMR_NORMALINTR\|SF_IMR_ABNORMALINTR\|SF_IMR_TXCQ_NOBUFS\| \ 352 SF_IMR_RXCQ1_NOBUFS\|SF_IMR_RXCQ2_NOBUFS\|SF_IMR_STATSOFLOW) 353 354/* TX descriptor queue control registers / 355#define SF_TXDQCTL_DESCTYPE 0x00000007 356#define SF_TXDQCTL_NODMACMP 0x00000008 357#define SF_TXDQCTL_MINSPACE 0x00000070 358#define SF_TXDQCTL_64BITADDR 0x00000080 359#define SF_TXDQCTL_BURSTLEN 0x00003F00 360#define SF_TXDQCTL_SKIPLEN 0x001F0000 361#define SF_TXDQCTL_HIPRIOTHRESH 0xFF000000 362* 363#define SF_TXBUFDESC_TYPE0 0x00000000 364#define SF_TXBUFDESC_TYPE1 0x00000001 365#define SF_TXBUFDESC_TYPE2 0x00000002 366#define SF_TXBUFDESC_TYPE3 0x00000003 367#define SF_TXBUFDESC_TYPE4 0x00000004 368 369#define SF_TXMINSPACE_UNLIMIT 0x00000000 370#define SF_TXMINSPACE_32BYTES 0x00000010 371#define SF_TXMINSPACE_64BYTES 0x00000020 372#define SF_TXMINSPACE_128BYTES 0x00000030 373#define SF_TXMINSPACE_256BYTES 0x00000040 374 375#define SF_TXSKIPLEN_0BYTES 0x00000000 376#define SF_TXSKIPLEN_8BYTES 0x00010000 377#define SF_TXSKIPLEN_16BYTES 0x00020000 378#define SF_TXSKIPLEN_24BYTES 0x00030000 379#define SF_TXSKIPLEN_32BYTES 0x00040000 380 381/* TX frame control register / 382#define SF_TXFRMCTL_TXTHRESH 0x000000FF 383#define SF_TXFRMCTL_CPLAFTERTX 0x00000100 384#define SF_TXFRMCRL_DEBUG 0x0000FE00 385#define SF_TXFRMCTL_STATUS 0x01FF0000 386#define SF_TXFRMCTL_MAC_TXIF 0xFE000000 387* 388/* TX completion queue control register / 389#define SF_TXCQ_THRESH 0x0000000F 390#define SF_TXCQ_COMMON 0x00000010 391#define SF_TXCQ_SIZE 0x00000020 392#define SF_TXCQ_WRITEENB 0x00000040 393#define SF_TXCQ_USE_64BIT 0x00000080 394#define SF_TXCQ_ADDR 0xFFFFFF00 395* 396/* RX completion queue control register / 397#define SF_RXCQ_THRESH 0x0000000F 398#define SF_RXCQ_TYPE 0x00000030 399#define SF_RXCQ_WRITEENB 0x00000040 400#define SF_RXCQ_USE_64BIT 0x00000080 401#define SF_RXCQ_ADDR 0xFFFFFF00 402* 403#define SF_RXCQTYPE_0 0x00000000 404#define SF_RXCQTYPE_1 0x00000010 405#define SF_RXCQTYPE_2 0x00000020 406#define SF_RXCQTYPE_3 0x00000030 407 408/* TX descriptor queue producer index register / 409#define SF_TXDQ_PRODIDX_LOPRIO 0x000007FF 410#define SF_TXDQ_PRODIDX_HIPRIO 0x07FF0000 411* 412/* TX descriptor queue consumer index register / 413#define SF_TXDQ_CONSIDX_LOPRIO 0x000007FF 414#define SF_TXDQ_CONSIDX_HIPRIO 0x07FF0000 415* 416/* Completion queue consumer index register / 417#define SF_CQ_CONSIDX_RXQ1 0x000003FF 418#define SF_CQ_CONSIDX_RXTHRMODE 0x00008000 419#define SF_CQ_CONSIDX_TXQ 0x03FF0000 420#define SF_CQ_CONSIDX_TXTHRMODE 0x80000000 421* 422/* Completion queue producer index register / 423#define SF_CQ_PRODIDX_RXQ1 0x000003FF 424#define SF_CQ_PRODIDX_TXQ 0x03FF0000 425* 426/* RX completion queue 2 consumer/producer index register / 427#define SF_CQ_RXQ2_CONSIDX 0x000003FF 428#define SF_CQ_RXQ2_RXTHRMODE 0x00008000 429#define SF_CQ_RXQ2_PRODIDX 0x03FF0000 430* 431#define SF_CQ_RXTHRMODE_INT_ON 0x00008000 432#define SF_CQ_RXTHRMODE_INT_OFF 0x00000000 433#define SF_CQ_TXTHRMODE_INT_ON 0x80000000 434#define SF_CQ_TXTHRMODE_INT_OFF 0x00000000 435 436#define SF_IDX_LO(x) ((x) & 0x000007FF) 437#define SF_IDX_HI(x) (((x) >> 16) & 0x000007FF) 438 439/* RX DMA control register / 440#define SF_RXDMA_BURSTSIZE 0x0000007F 441#define SF_RXDMA_FPTESTMODE 0x00000080 442#define SF_RXDMA_HIPRIOTHRESH 0x00000F00 443#define SF_RXDMA_RXEARLYTHRESH 0x0001F000 444#define SF_RXDMA_DMACRC 0x00040000 445#define SF_RXDMA_USEBKUPQUEUE 0x00080000 446#define SF_RXDMA_QUEUEMODE 0x00700000 447#define SF_RXDMA_RXCQ2_ON 0x00800000 448#define SF_RXDMA_CSUMMODE 0x03000000 449#define SF_RXDMA_DMAPAUSEPKTS 0x04000000 450#define SF_RXDMA_DMACTLPKTS 0x08000000 451#define SF_RXDMA_DMACRXERRPKTS 0x10000000 452#define SF_RXDMA_DMABADPKTS 0x20000000 453#define SF_RXDMA_DMARUNTS 0x40000000 454#define SF_RXDMA_REPORTBADPKTS 0x80000000 455* 456#define SF_RXDQMODE_Q1ONLY 0x00100000 457#define SF_RXDQMODE_Q2_ON_FP 0x00200000 458#define SF_RXDQMODE_Q2_ON_SHORT 0x00300000 459#define SF_RXDQMODE_Q2_ON_PRIO 0x00400000 460#define SF_RXDQMODE_SPLITHDR 0x00500000 461 462#define SF_RXCSUMMODE_IGNORE 0x00000000 463#define SF_RXCSUMMODE_REJECT_BAD_TCP 0x01000000 464#define SF_RXCSUMMODE_REJECT_BAD_TCPUDP 0x02000000 465#define SF_RXCSUMMODE_RSVD 0x03000000 466 467/* RX descriptor queue control registers / 468#define SF_RXDQCTL_MINDESCTHR 0x0000007F 469#define SF_RXDQCTL_Q1_WE 0x00000080 470#define SF_RXDQCTL_DESCSPACE 0x00000700 471#define SF_RXDQCTL_64BITDADDR 0x00000800 472#define SF_RXDQCTL_64BITBADDR 0x00001000 473#define SF_RXDQCTL_VARIABLE 0x00002000 474#define SF_RXDQCTL_ENTRIES 0x00004000 475#define SF_RXDQCTL_PREFETCH 0x00008000 476#define SF_RXDQCTL_BUFLEN 0xFFFF0000 477* 478#define SF_DESCSPACE_4BYTES 0x00000000 479#define SF_DESCSPACE_8BYTES 0x00000100 480#define SF_DESCSPACE_16BYTES 0x00000200 481#define SF_DESCSPACE_32BYTES 0x00000300 482#define SF_DESCSPACE_64BYTES 0x00000400 483#define SF_DESCSPACE_128_BYTES 0x00000500 484 485/* RX buffer consumer/producer index registers / 486#define SF_RXDQ_PRODIDX 0x000007FF 487#define SF_RXDQ_CONSIDX 0x07FF0000 488* 489/* RX filter control register / 490#define SF_RXFILT_PROMISC 0x00000001 491#define SF_RXFILT_ALLMULTI 0x00000002 492#define SF_RXFILT_BROAD 0x00000004 493#define SF_RXFILT_HASHPRIO 0x00000008 494#define SF_RXFILT_HASHMODE 0x00000030 495#define SF_RXFILT_PERFMODE 0x000000C0 496#define SF_RXFILT_VLANMODE 0x00000300 497#define SF_RXFILT_WAKEMODE 0x00000C00 498#define SF_RXFILT_MULTI_NOBROAD 0x00001000 499#define SF_RXFILT_MIN_VLANPRIO 0x0000E000 500#define SF_RXFILT_PEFECTPRIO 0xFFFF0000 501* 502/* Hash filtering mode / 503#define SF_HASHMODE_OFF 0x00000000 504#define SF_HASHMODE_WITHVLAN 0x00000010 505#define SF_HASHMODE_ANYVLAN 0x00000020 506#define SF_HASHMODE_ANY 0x00000030 507* 508/* Perfect filtering mode / 509#define SF_PERFMODE_OFF 0x00000000 510#define SF_PERFMODE_NORMAL 0x00000040 511#define SF_PERFMODE_INVERSE 0x00000080 512#define SF_PERFMODE_VLAN 0x000000C0 513* 514/* VLAN mode / 515#define SF_VLANMODE_OFF 0x00000000 516#define SF_VLANMODE_NOSTRIP 0x00000100 517#define SF_VLANMODE_STRIP 0x00000200 518#define SF_VLANMODE_RSVD 0x00000300 519* 520/* Wakeup mode / 521#define SF_WAKEMODE_OFF 0x00000000 522#define SF_WAKEMODE_FILTER 0x00000400 523#define SF_WAKEMODE_FP 0x00000800 524#define SF_WAKEMODE_HIPRIO 0x00000C00 525* 526/* 527 * Extra PCI registers 0x0100 to 0x0FFF 528 / 529#define SF_PCI_TARGSTAT 0x0100 530#define SF_PCI_MASTSTAT1 0x0104 531#define SF_PCI_MASTSTAT2 0x0108 532#define SF_PCI_DMAHOSTADDR_LO 0x010C 533#define SF_BAC_DMADIAG0 0x0110 534#define SF_BAC_DMADIAG1 0x0114 535#define SF_BAC_DMADIAG2 0x0118 536#define SF_BAC_DMADIAG3 0x011C 537#define SF_PAR0 0x0120 538#define SF_PAR1 0x0124 539#define SF_PCICB_FUNCEVENT 0x0130 540#define SF_PCICB_FUNCEVENT_MASK 0x0134 541#define SF_PCICB_FUNCSTATE 0x0138 542#define SF_PCICB_FUNCFORCE 0x013C 543* 544/* 545 * Serial EEPROM registers 0x1000 to 0x1FFF 546 * Presumeably the EEPROM is mapped into this 8K window. 547 / 548#define SF_EEADDR_BASE 0x1000 549#define SF_EEADDR_MAX 0x1FFF 550* 551#define SF_EE_NODEADDR 14 552 553/* 554 * MII registers registers 0x2000 to 0x3FFF 555 * There are 32 sets of 32 registers, one set for each possible 556 * PHY address. Each 32 bit register is split into a 16-bit data 557 * port and a couple of status bits. 558 / 559* 560#define SF_MIIADDR_BASE 0x2000 561#define SF_MIIADDR_MAX 0x3FFF 562#define SF_MII_BLOCKS 32 563 564#define SF_MII_DATAVALID 0x80000000 565#define SF_MII_BUSY 0x40000000 566#define SF_MII_DATAPORT 0x0000FFFF 567 568#define SF_PHY_REG(phy, reg) \ 569 (SF_MIIADDR_BASE + (phy * SF_MII_BLOCKS * sizeof(u_int32_t)) + \ 570 (reg * sizeof(u_int32_t))) 571 572/* 573 * Ethernet extra registers 0x4000 to 0x4FFF 574 / 575#define SF_TESTMODE 0x4000 576#define SF_RX_FRAMEPROC_CTL 0x4004 577#define SF_TX_FRAMEPROC_CTL 0x4008 578* 579/* 580 * MAC registers 0x5000 to 0x5FFF 581 / 582#define SF_MACCFG_1 0x5000 583#define SF_MACCFG_2 0x5004 584#define SF_BKTOBKIPG 0x5008 585#define SF_NONBKTOBKIPG 0x500C 586#define SF_COLRETRY 0x5010 587#define SF_MAXLEN 0x5014 588#define SF_TXNIBBLECNT 0x5018 589#define SF_TXBYTECNT 0x501C 590#define SF_RETXCNT 0x5020 591#define SF_RANDNUM 0x5024 592#define SF_RANDNUM_MASK 0x5028 593#define SF_TOTALTXCNT 0x5034 594#define SF_RXBYTECNT 0x5040 595#define SF_TXPAUSETIMER 0x5060 596#define SF_VLANTYPE 0x5064 597#define SF_MIISTATUS 0x5070 598* 599#define SF_MACCFG1_HUGEFRAMES 0x00000001 600#define SF_MACCFG1_FULLDUPLEX 0x00000002 601#define SF_MACCFG1_AUTOPAD 0x00000004 602#define SF_MACCFG1_HDJAM 0x00000008 603#define SF_MACCFG1_DELAYCRC 0x00000010 604#define SF_MACCFG1_NOBACKOFF 0x00000020 605#define SF_MACCFG1_LENGTHCHECK 0x00000040 606#define SF_MACCFG1_PUREPREAMBLE 0x00000080 607#define SF_MACCFG1_PASSALLRX 0x00000100 608#define SF_MACCFG1_PREAM_DETCNT 0x00000200 609#define SF_MACCFG1_RX_FLOWENB 0x00000400 610#define SF_MACCFG1_TX_FLOWENB 0x00000800 611#define SF_MACCFG1_TESTMODE 0x00003000 612#define SF_MACCFG1_MIILOOPBK 0x00004000 613#define SF_MACCFG1_SOFTRESET 0x00008000 614 615/* 616 * RX filter registers 0x6000 to 0x6FFF 617 / 618#define SF_RXFILT_PERFECT_BASE 0x6000 619#define SF_RXFILT_PERFECT_MAX 0x60FF 620#define SF_RXFILT_PERFECT_SKIP 0x0010 621#define SF_RXFILT_PERFECT_CNT 0x0010 622* 623#define SF_RXFILT_HASH_BASE 0x6100 624#define SF_RXFILT_HASH_MAX 0x62FF 625#define SF_RXFILT_HASH_SKIP 0x0010 626#define SF_RXFILT_HASH_CNT 0x001F 627#define SF_RXFILT_HASH_ADDROFF 0x0000 628#define SF_RXFILT_HASH_PRIOOFF 0x0004 629#define SF_RXFILT_HASH_VLANOFF 0x0008 630 631/* 632 * Statistics registers 0x7000 to 0x7FFF 633 / 634#define SF_STATS_BASE 0x7000 635#define SF_STATS_END 0x7FFF 636* 637/* 638 * TX frame processor instruction space 0x8000 to 0x9FFF 639 / 640* 641/* 642 * RX frame processor instruction space 0xA000 to 0xBFFF 643 / 644* 645/* 646 * Ethernet FIFO access space 0xC000 to 0xDFFF 647 / 648* 649/* 650 * Reserved 0xE000 to 0xFFFF 651 / 652* 653/* 654 * Descriptor data structures. 655 / 656* 657 658/* Receive descriptor formats. / 659#define SF_RX_MINSPACING 8 660#define SF_RX_DLIST_CNT 256 661#define SF_RX_CLIST_CNT 1024 662#define SF_RX_HOSTADDR(x) (((x) >> 2) & 0x3FFFFFFF) 663* 664/* 665 * RX buffer descriptor type 0, 32-bit addressing. Note that we 666 * program the RX buffer queue control register(s) to allow a 667 * descriptor spacing of 16 bytes, which leaves room after each 668 * descriptor to store a pointer to the mbuf for each buffer. 669 / 670struct sf_rx_bufdesc_type0 { 671* u_int32_t sf_valid:1, 672 sf_end:1, 673 sf_addrlo:30; 674 u_int32_t sf_pad0; 675#ifdef __i386__ 676 u_int32_t sf_pad1; 677#endif 678 struct mbuf sf_mbuf; 679}; 680* 681/* 682 * RX buffer descriptor type 0, 64-bit addressing. 683 / 684struct sf_rx_bufdesc_type1 { 685* u_int32_t sf_valid:1, 686 sf_end:1, 687 sf_addrlo:30; 688 u_int32_t sf_addrhi; 689#ifdef __i386__ 690 u_int32_t sf_pad; 691#endif 692 struct mbuf sf_mbuf; 693}; 694* 695/* 696 * RX completion descriptor, type 0 (short). 697 / 698struct sf_rx_cmpdesc_type0 { 699* u_int32_t sf_len:16, 700 sf_endidx:11, 701 sf_status1:3, 702 sf_id:2; 703}; 704 705/* 706 * RX completion descriptor, type 1 (basic). Includes vlan ID 707 * if this is a vlan-addressed packet, plus extended status. 708 / 709struct sf_rx_cmpdesc_type1 { 710* u_int32_t sf_len:16, 711 sf_endidx:11, 712 sf_status1:3, 713 sf_id:2; 714 u_int16_t sf_status2; 715 u_int16_t sf_vlanid; 716}; 717 718/* 719 * RX completion descriptor, type 2 (checksum). Includes partial TCP/IP 720 * checksum instead of vlan tag, plus extended status. 721 / 722struct sf_rx_cmpdesc_type2 { 723* u_int32_t sf_len:16, 724 sf_endidx:11, 725 sf_status1:3, 726 sf_id:2; 727 u_int16_t sf_status2; 728 u_int16_t sf_cksum; 729}; 730 731/* 732 * RX completion descriptor type 3 (full). Includes timestamp, partial 733 * TCP/IP checksum, vlan tag plus priority, two extended status fields. 734 / 735struct sf_rx_cmpdesc_type3 { 736* u_int32_t sf_len:16, 737 sf_endidx:11, 738 sf_status1:3, 739 sf_id:2; 740 u_int32_t sf_startidx:10, 741 sf_status3:6, 742 sf_status2:16; 743 u_int16_t sf_cksum; 744 u_int16_t sf_vlanid_prio; 745 u_int32_t sf_timestamp; 746}; 747 748#define SF_RXSTAT1_QUEUE 0x1 749#define SF_RXSTAT1_FIFOFULL 0x2 750#define SF_RXSTAT1_OK 0x4 751 752 /* 0=unknown,5=unsupported / 753#define SF_RXSTAT2_FRAMETYPE 0x0007 / 1=IPv4,2=IPv2,3=IPX,4=ICMP / 754#define SF_RXSTAT2_UDP 0x0008 755#define SF_RXSTAT2_TCP 0x0010 756#define SF_RXSTAT2_FRAG 0x0020 757#define SF_RXSTAT2_PCSUM_OK 0x0040 / partial checksum ok / 758#define SF_RXSTAT2_CSUM_BAD 0x0080 / TCP/IP checksum bad / 759#define SF_RXSTAT2_CSUM_OK 0x0100 / TCP/IP checksum ok / 760#define SF_RXSTAT2_VLAN 0x0200 761#define SF_RXSTAT2_BADRXCODE 0x0400 762#define SF_RXSTAT2_DRIBBLE 0x0800 763#define SF_RXSTAT2_ISL_CRCERR 0x1000 764#define SF_RXSTAT2_CRCERR 0x2000 765#define SF_RXSTAT2_HASH 0x4000 766#define SF_RXSTAT2_PERFECT 0x8000 767* 768#define SF_RXSTAT3_TRAILER 0x01 769#define SF_RXSTAT3_HEADER 0x02 770#define SF_RXSTAT3_CONTROL 0x04 771#define SF_RXSTAT3_PAUSE 0x08 772#define SF_RXSTAT3_ISL 0x10 773 774/* 775 * Transmit descriptor formats. 776 * Each transmit descriptor type allows for a skip field at the 777 * start of each structure. The size of the skip field can vary, 778 * however we always set it for 8 bytes, which is enough to hold 779 * a pointer (32 bits on x86, 64-bits on alpha) that we can use 780 * to hold the address of the head of the mbuf chain for the 781 * frame or fragment associated with the descriptor. This saves 782 * us from having to create a separate pointer array to hold 783 * the mbuf addresses. 784 / 785#define SF_TX_BUFDESC_ID 0xB 786#define SF_MAXFRAGS 14 787#define SF_TX_MINSPACING 128 788#define SF_TX_DLIST_CNT 128 789#define SF_TX_DLIST_SIZE 16384 790#define SF_TX_SKIPLEN 1 791#define SF_TX_CLIST_CNT 1024 792* 793struct sf_frag { 794 u_int32_t sf_addr; 795 u_int16_t sf_fraglen; 796 u_int16_t sf_pktlen; 797}; 798 799struct sf_frag_msdos { 800 u_int16_t sf_pktlen; 801 u_int16_t sf_fraglen; 802 u_int32_t sf_addr; 803}; 804 805/* 806 * TX frame descriptor type 0, 32-bit addressing. One descriptor can 807 * be used to map multiple packet fragments. We use this format since 808 * BSD networking fragments packet data across mbuf chains. Note that 809 * the number of fragments can be variable depending on how the descriptor 810 * spacing is specified in the TX descriptor queue control register. 811 * We always use a spacing of 128 bytes, and a skipfield length of 8 812 * bytes: this means 16 bytes for the descriptor, including the skipfield, 813 * with 121 bytes left for fragment maps. Each fragment requires 8 bytes, 814 * which allows for 14 fragments per descriptor. The total size of the 815 * transmit buffer queue is limited to 16384 bytes, so with a spacing of 816 * 128 bytes per descriptor, we have room for 128 descriptors in the queue. 817 / 818struct sf_tx_bufdesc_type0 { 819#ifdef __i386__ 820* u_int32_t sf_pad; 821#endif 822 struct mbuf sf_mbuf; 823* u_int32_t sf_rsvd0:24, 824 sf_crcen:1, 825 sf_caltcp:1, 826 sf_end:1, 827 sf_intr:1, 828 sf_id:4; 829 u_int8_t sf_fragcnt; 830 u_int8_t sf_rsvd2; 831 u_int16_t sf_rsvd1; 832 struct sf_frag sf_frags[14]; 833}; 834 835/* 836 * TX buffer descriptor type 1, 32-bit addressing. Each descriptor 837 * maps a single fragment. 838 / 839struct sf_tx_bufdesc_type1 { 840#ifdef __i386__ 841* u_int32_t sf_pad; 842#endif 843 struct mbuf sf_mbuf; 844* u_int32_t sf_fraglen:16, 845 sf_fragcnt:8, 846 sf_crcen:1, 847 sf_caltcp:1, 848 sf_end:1, 849 sf_intr:1, 850 sf_id:4; 851 u_int32_t sf_addr; 852}; 853 854/* 855 * TX buffer descriptor type 2, 64-bit addressing. Each descriptor 856 * maps a single fragment. 857 / 858struct sf_tx_bufdesc_type2 { 859#ifdef __i386__ 860* u_int32_t sf_pad; 861#endif 862 struct mbuf sf_mbuf; 863* u_int32_t sf_fraglen:16, 864 sf_fragcnt:8, 865 sf_crcen:1, 866 sf_caltcp:1, 867 sf_end:1, 868 sf_intr:1, 869 sf_id:4; 870 u_int32_t sf_addrlo; 871 u_int32_t sf_addrhi; 872}; 873 874/* TX buffer descriptor type 3 is not defined. / 875* 876/* 877 * TX frame descriptor type 4, 32-bit addressing. This is a special 878 * case of the type 0 descriptor, identical except that the fragment 879 * address and length fields are ordered differently. This is done 880 * to optimize copies in MS-DOS and OS/2 drivers. 881 / 882struct sf_tx_bufdesc_type4 { 883#ifdef __i386__ 884* u_int32_t sf_pad; 885#endif 886 struct mbuf sf_mbuf; 887* u_int32_t sf_rsvd0:24, 888 sf_crcen:1, 889 sf_caltcp:1, 890 sf_end:1, 891 sf_intr:1, 892 sf_id:4; 893 u_int8_t sf_fragcnt; 894 u_int8_t sf_rsvd2; 895 u_int16_t sf_rsvd1; 896 struct sf_frag_msdos sf_frags[14]; 897}; 898 899/* 900 * Transmit completion queue descriptor formats. 901 / 902* 903/* 904 * Transmit DMA completion descriptor, type 0. 905 / 906#define SF_TXCMPTYPE_DMA 0x4 907struct sf_tx_cmpdesc_type0 { 908* u_int32_t sf_index:15, 909 sf_priority:1, 910 sf_timestamp:13, 911 sf_type:3; 912}; 913 914/* 915 * Transmit completion descriptor, type 1. 916 / 917#define SF_TXCMPTYPE_TX 0x5 918struct sf_tx_cmpdesc_type1 { 919* u_int32_t sf_index:15, 920 sf_priority:1, 921 sf_txstat:13, 922 sf_type:3; 923}; 924 925#define SF_TXSTAT_CRCERR 0x0001 926#define SF_TXSTAT_LENCHECKERR 0x0002 927#define SF_TXSTAT_LENRANGEERR 0x0004 928#define SF_TXSTAT_TX_OK 0x0008 929#define SF_TXSTAT_TX_DEFERED 0x0010 930#define SF_TXSTAT_EXCESS_DEFER 0x0020 931#define SF_TXSTAT_EXCESS_COLL 0x0040 932#define SF_TXSTAT_LATE_COLL 0x0080 933#define SF_TXSTAT_TOOBIG 0x0100 934#define SF_TXSTAT_TX_UNDERRUN 0x0200 935#define SF_TXSTAT_CTLFRAME_OK 0x0400 936#define SF_TXSTAT_PAUSEFRAME_OK 0x0800 937#define SF_TXSTAT_PAUSED 0x1000 938 939/* Statistics counters. / 940struct sf_stats { 941* u_int32_t sf_tx_frames; 942 u_int32_t sf_tx_single_colls; 943 u_int32_t sf_tx_multi_colls; 944 u_int32_t sf_tx_crcerrs; 945 u_int32_t sf_tx_bytes; 946 u_int32_t sf_tx_defered; 947 u_int32_t sf_tx_late_colls; 948 u_int32_t sf_tx_pause_frames; 949 u_int32_t sf_tx_control_frames; 950 u_int32_t sf_tx_excess_colls; 951 u_int32_t sf_tx_excess_defer; 952 u_int32_t sf_tx_mcast_frames; 953 u_int32_t sf_tx_bcast_frames; 954 u_int32_t sf_tx_frames_lost; 955 u_int32_t sf_rx_rx_frames; 956 u_int32_t sf_rx_crcerrs; 957 u_int32_t sf_rx_alignerrs; 958 u_int32_t sf_rx_bytes; 959 u_int32_t sf_rx_control_frames; 960 u_int32_t sf_rx_unsup_control_frames; 961 u_int32_t sf_rx_giants; 962 u_int32_t sf_rx_runts; 963 u_int32_t sf_rx_jabbererrs; 964 u_int32_t sf_rx_pkts_64; 965 u_int32_t sf_rx_pkts_65_127; 966 u_int32_t sf_rx_pkts_128_255; 967 u_int32_t sf_rx_pkts_256_511; 968 u_int32_t sf_rx_pkts_512_1023; 969 u_int32_t sf_rx_pkts_1024_1518; 970 u_int32_t sf_rx_frames_lost; 971 u_int16_t sf_tx_underruns; 972 u_int16_t sf_pad; 973}; 974 975/* 976 * register space access macros 977 / 978#define CSR_WRITE_4(sc, reg, val) \ 979* bus_space_write_4(sc->sf_btag, sc->sf_bhandle, reg, val) 980 981#define CSR_READ_4(sc, reg) \ 982 bus_space_read_4(sc->sf_btag, sc->sf_bhandle, reg) 983 984#define CSR_READ_1(sc, reg) \ 985 bus_space_read_1(sc->sf_btag, sc->sf_bhandle, reg) 986 987 988struct sf_type { 989 u_int16_t sf_vid; 990 u_int16_t sf_did; 991 char sf_name; 992}; 993* 994#define SF_INC(x, y) (x) = (x + 1) % y 995 996#define ETHER_ALIGN 2 997 998/* 999 * Note: alignment is important here: each list must be aligned to 1000 * a 256-byte boundary. It turns out that each ring is some multiple 1001 * of 4K in length, so we can stack them all on top of each other 1002 * and just worry about aligning the whole mess. There's one transmit 1003 * buffer ring and two receive buffer rings: one RX ring is for small 1004 * packets and the other is for large packets. Each buffer ring also 1005 * has a companion completion queue. 1006 / 1007struct sf_list_data { 1008* struct sf_tx_bufdesc_type0 sf_tx_dlist[SF_TX_DLIST_CNT]; 1009 struct sf_tx_cmpdesc_type1 sf_tx_clist[SF_TX_CLIST_CNT]; 1010 struct sf_rx_bufdesc_type0 sf_rx_dlist_big[SF_RX_DLIST_CNT]; 1011#ifdef notdef 1012 /* 1013 * Unfortunately, because the Starfire doesn't allow arbitrary 1014 * byte alignment, we have to copy packets in the RX handler in 1015 * order to align the payload correctly. This means that we 1016 * don't gain anything by having separate large and small descriptor 1017 * lists, so for now we don't bother with the small one. 1018 / 1019* struct sf_rx_bufdesc_type0 sf_rx_dlist_small[SF_RX_DLIST_CNT]; 1020#endif 1021 struct sf_rx_cmpdesc_type3 sf_rx_clist[SF_RX_CLIST_CNT]; 1022}; 1023 1024struct sf_softc { 1025 struct arpcom arpcom; /* interface info / 1026* bus_space_handle_t sf_bhandle; /* bus space handle / 1027* bus_space_tag_t sf_btag; /* bus space tag / 1028* void sf_intrhand; / interrupt handler cookie / 1029* struct resource sf_irq; / irq resource descriptor / 1030* struct resource sf_res; / mem/ioport resource / 1031* struct sf_type sf_info; / Starfire adapter info / 1032* device_t sf_miibus; 1033 u_int8_t sf_unit; /* interface number / 1034* struct sf_list_data sf_ldata; 1035* int sf_tx_cnt; 1036 struct callout_handle sf_stat_ch; 1037}; 1038 1039#define SF_TIMEOUT 1000 1040 1041#ifdef __alpha__ 1042#undef vtophys 1043#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1044#endif