| sdhci.h (276287) | sdhci.h (278703) |
|---|---|
| 1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 8 unchanged lines hidden (view full) --- 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * | 1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 8 unchanged lines hidden (view full) --- 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * |
| 25 * $FreeBSD: stable/10/sys/dev/sdhci/sdhci.h 276287 2014-12-27 04:54:36Z ian $ | 25 * $FreeBSD: stable/10/sys/dev/sdhci/sdhci.h 278703 2015-02-13 20:38:39Z ian $ |
| 26 */ 27 28#ifndef __SDHCI_H__ 29#define __SDHCI_H__ 30 31#define DMA_BLOCK_SIZE 4096 32#define DMA_BOUNDARY 0 /* DMA reload every 4K */ 33 --- 22 unchanged lines hidden (view full) --- 56/* Timeout value is invalid, should be overriden */ 57#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<11) 58/* SDHCI_CAPABILITIES is invalid */ 59#define SDHCI_QUIRK_MISSING_CAPS (1<<12) 60/* Hardware shifts the 136-bit response, don't do it in software. */ 61#define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1<<13) 62/* Wait to see reset bit asserted before waiting for de-asserted */ 63#define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1<<14) | 26 */ 27 28#ifndef __SDHCI_H__ 29#define __SDHCI_H__ 30 31#define DMA_BLOCK_SIZE 4096 32#define DMA_BOUNDARY 0 /* DMA reload every 4K */ 33 --- 22 unchanged lines hidden (view full) --- 56/* Timeout value is invalid, should be overriden */ 57#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<11) 58/* SDHCI_CAPABILITIES is invalid */ 59#define SDHCI_QUIRK_MISSING_CAPS (1<<12) 60/* Hardware shifts the 136-bit response, don't do it in software. */ 61#define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1<<13) 62/* Wait to see reset bit asserted before waiting for de-asserted */ 63#define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1<<14) |
| 64/* Leave controller in standard mode when putting card in HS mode. */ 65#define SDHCI_QUIRK_DONT_SET_HISPD_BIT (1<<15) |
|
| 64 65/* 66 * Controller registers 67 */ 68#define SDHCI_DMA_ADDRESS 0x00 69 70#define SDHCI_BLOCK_SIZE 0x04 71#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) --- 92 unchanged lines hidden (view full) --- 164#define SDHCI_INT_DATA_END 0x00000002 165#define SDHCI_INT_BLOCK_GAP 0x00000004 166#define SDHCI_INT_DMA_END 0x00000008 167#define SDHCI_INT_SPACE_AVAIL 0x00000010 168#define SDHCI_INT_DATA_AVAIL 0x00000020 169#define SDHCI_INT_CARD_INSERT 0x00000040 170#define SDHCI_INT_CARD_REMOVE 0x00000080 171#define SDHCI_INT_CARD_INT 0x00000100 | 66 67/* 68 * Controller registers 69 */ 70#define SDHCI_DMA_ADDRESS 0x00 71 72#define SDHCI_BLOCK_SIZE 0x04 73#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) --- 92 unchanged lines hidden (view full) --- 166#define SDHCI_INT_DATA_END 0x00000002 167#define SDHCI_INT_BLOCK_GAP 0x00000004 168#define SDHCI_INT_DMA_END 0x00000008 169#define SDHCI_INT_SPACE_AVAIL 0x00000010 170#define SDHCI_INT_DATA_AVAIL 0x00000020 171#define SDHCI_INT_CARD_INSERT 0x00000040 172#define SDHCI_INT_CARD_REMOVE 0x00000080 173#define SDHCI_INT_CARD_INT 0x00000100 |
| 174#define SDHCI_INT_INT_A 0x00000200 175#define SDHCI_INT_INT_B 0x00000400 176#define SDHCI_INT_INT_C 0x00000800 177#define SDHCI_INT_RETUNE 0x00001000 |
|
| 172#define SDHCI_INT_ERROR 0x00008000 173#define SDHCI_INT_TIMEOUT 0x00010000 174#define SDHCI_INT_CRC 0x00020000 175#define SDHCI_INT_END_BIT 0x00040000 176#define SDHCI_INT_INDEX 0x00080000 177#define SDHCI_INT_DATA_TIMEOUT 0x00100000 178#define SDHCI_INT_DATA_CRC 0x00200000 179#define SDHCI_INT_DATA_END_BIT 0x00400000 180#define SDHCI_INT_BUS_POWER 0x00800000 181#define SDHCI_INT_ACMD12ERR 0x01000000 182#define SDHCI_INT_ADMAERR 0x02000000 | 178#define SDHCI_INT_ERROR 0x00008000 179#define SDHCI_INT_TIMEOUT 0x00010000 180#define SDHCI_INT_CRC 0x00020000 181#define SDHCI_INT_END_BIT 0x00040000 182#define SDHCI_INT_INDEX 0x00080000 183#define SDHCI_INT_DATA_TIMEOUT 0x00100000 184#define SDHCI_INT_DATA_CRC 0x00200000 185#define SDHCI_INT_DATA_END_BIT 0x00400000 186#define SDHCI_INT_BUS_POWER 0x00800000 187#define SDHCI_INT_ACMD12ERR 0x01000000 188#define SDHCI_INT_ADMAERR 0x02000000 |
| 189#define SDHCI_INT_TUNEERR 0x04000000 |
|
| 183 184#define SDHCI_INT_NORMAL_MASK 0x00007FFF 185#define SDHCI_INT_ERROR_MASK 0xFFFF8000 186 187#define SDHCI_INT_CMD_ERROR_MASK (SDHCI_INT_TIMEOUT | \ 188 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 189 190#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK) 191 192#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 193 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 194 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 195 SDHCI_INT_DATA_END_BIT) 196 197#define SDHCI_ACMD12_ERR 0x3C | 190 191#define SDHCI_INT_NORMAL_MASK 0x00007FFF 192#define SDHCI_INT_ERROR_MASK 0xFFFF8000 193 194#define SDHCI_INT_CMD_ERROR_MASK (SDHCI_INT_TIMEOUT | \ 195 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 196 197#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK) 198 199#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 200 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 201 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 202 SDHCI_INT_DATA_END_BIT) 203 204#define SDHCI_ACMD12_ERR 0x3C |
| 205#define SDHCI_HOST_CONTROL2 0x3E |
|
| 198 199#define SDHCI_CAPABILITIES 0x40 200#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 201#define SDHCI_TIMEOUT_CLK_SHIFT 0 202#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 203#define SDHCI_CLOCK_BASE_MASK 0x00003F00 204#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 205#define SDHCI_CLOCK_BASE_SHIFT 8 206#define SDHCI_MAX_BLOCK_MASK 0x00030000 207#define SDHCI_MAX_BLOCK_SHIFT 16 208#define SDHCI_CAN_DO_8BITBUS 0x00040000 209#define SDHCI_CAN_DO_ADMA2 0x00080000 210#define SDHCI_CAN_DO_HISPD 0x00200000 211#define SDHCI_CAN_DO_DMA 0x00400000 212#define SDHCI_CAN_DO_SUSPEND 0x00800000 213#define SDHCI_CAN_VDD_330 0x01000000 214#define SDHCI_CAN_VDD_300 0x02000000 215#define SDHCI_CAN_VDD_180 0x04000000 216#define SDHCI_CAN_DO_64BIT 0x10000000 | 206 207#define SDHCI_CAPABILITIES 0x40 208#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 209#define SDHCI_TIMEOUT_CLK_SHIFT 0 210#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 211#define SDHCI_CLOCK_BASE_MASK 0x00003F00 212#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 213#define SDHCI_CLOCK_BASE_SHIFT 8 214#define SDHCI_MAX_BLOCK_MASK 0x00030000 215#define SDHCI_MAX_BLOCK_SHIFT 16 216#define SDHCI_CAN_DO_8BITBUS 0x00040000 217#define SDHCI_CAN_DO_ADMA2 0x00080000 218#define SDHCI_CAN_DO_HISPD 0x00200000 219#define SDHCI_CAN_DO_DMA 0x00400000 220#define SDHCI_CAN_DO_SUSPEND 0x00800000 221#define SDHCI_CAN_VDD_330 0x01000000 222#define SDHCI_CAN_VDD_300 0x02000000 223#define SDHCI_CAN_VDD_180 0x04000000 224#define SDHCI_CAN_DO_64BIT 0x10000000 |
| 225#define SDHCI_CAN_ASYNC_INTR 0x20000000 |
|
| 217 | 226 |
| 227#define SDHCI_CAPABILITIES2 0x44 228#define SDHCI_CAN_SDR50 0x00000001 229#define SDHCI_CAN_SDR104 0x00000002 230#define SDHCI_CAN_DDR50 0x00000004 231#define SDHCI_CAN_DRIVE_TYPE_A 0x00000010 232#define SDHCI_CAN_DRIVE_TYPE_B 0x00000020 233#define SDHCI_CAN_DRIVE_TYPE_C 0x00000040 234#define SDHCI_RETUNE_CNT_MASK 0x00000F00 235#define SDHCI_RETUNE_CNT_SHIFT 8 236#define SDHCI_TUNE_SDR50 0x00002000 237#define SDHCI_RETUNE_MODES_MASK 0x0000C000 238#define SDHCI_RETUNE_MODES_SHIFT 14 239#define SDHCI_CLOCK_MULT_MASK 0x00FF0000 240#define SDHCI_CLOCK_MULT_SHIFT 16 241 |
|
| 218#define SDHCI_MAX_CURRENT 0x48 | 242#define SDHCI_MAX_CURRENT 0x48 |
| 243#define SDHCI_FORCE_AUTO_EVENT 0x50 244#define SDHCI_FORCE_INTR_EVENT 0x52 245#define SDHCI_ADMA_ERR 0x54 246#define SDHCI_ADMA_ADDRESS_LOW 0x58 247#define SDHCI_ADMA_ADDRESS_HI 0x5C 248#define SDHCI_PRESET_VALUE 0x60 249#define SDHCI_SHARED_BUS_CTRL 0xE0 |
|
| 219 220#define SDHCI_SLOT_INT_STATUS 0xFC 221 222#define SDHCI_HOST_VERSION 0xFE 223#define SDHCI_VENDOR_VER_MASK 0xFF00 224#define SDHCI_VENDOR_VER_SHIFT 8 225#define SDHCI_SPEC_VER_MASK 0x00FF 226#define SDHCI_SPEC_VER_SHIFT 0 --- 63 unchanged lines hidden --- | 250 251#define SDHCI_SLOT_INT_STATUS 0xFC 252 253#define SDHCI_HOST_VERSION 0xFE 254#define SDHCI_VENDOR_VER_MASK 0xFF00 255#define SDHCI_VENDOR_VER_SHIFT 8 256#define SDHCI_SPEC_VER_MASK 0x00FF 257#define SDHCI_SPEC_VER_SHIFT 0 --- 63 unchanged lines hidden --- |