| sdhci.h (241600) | sdhci.h (242320) |
|---|---|
| 1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 8 unchanged lines hidden (view full) --- 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * | 1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 8 unchanged lines hidden (view full) --- 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * |
| 25 * $FreeBSD: head/sys/dev/sdhci/sdhci.h 241600 2012-10-16 01:10:43Z gonzo $ | 25 * $FreeBSD: head/sys/dev/sdhci/sdhci.h 242320 2012-10-29 17:21:58Z gonzo $ |
| 26 */ 27 28#ifndef __SDHCI_H__ 29#define __SDHCI_H__ 30 31#define DMA_BLOCK_SIZE 4096 32#define DMA_BOUNDARY 0 /* DMA reload every 4K */ 33 --- 12 unchanged lines hidden (view full) --- 46/* Controller needs to be reset after each request to stay stable */ 47#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6) 48/* Controller has an off-by-one issue with timeout value */ 49#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7) 50/* Controller has broken read timings */ 51#define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8) 52/* Controller needs lowered frequency */ 53#define SDHCI_QUIRK_LOWER_FREQUENCY (1<<9) | 26 */ 27 28#ifndef __SDHCI_H__ 29#define __SDHCI_H__ 30 31#define DMA_BLOCK_SIZE 4096 32#define DMA_BOUNDARY 0 /* DMA reload every 4K */ 33 --- 12 unchanged lines hidden (view full) --- 46/* Controller needs to be reset after each request to stay stable */ 47#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6) 48/* Controller has an off-by-one issue with timeout value */ 49#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7) 50/* Controller has broken read timings */ 51#define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8) 52/* Controller needs lowered frequency */ 53#define SDHCI_QUIRK_LOWER_FREQUENCY (1<<9) |
| 54/* Data timeout is invalid, should use SD clock */ 55#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<10) 56/* Timeout value is invalid, should be overriden */ 57#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<11) 58/* SDHCI_CAPABILITIES is invalid */ 59#define SDHCI_QUIRK_MISSING_CAPS (1<<12) |
|
| 54 | 60 |
| 55 | |
| 56/* 57 * Controller registers 58 */ | 61/* 62 * Controller registers 63 */ |
| 59 | |
| 60#define SDHCI_DMA_ADDRESS 0x00 61 62#define SDHCI_BLOCK_SIZE 0x04 63#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 64 65#define SDHCI_BLOCK_COUNT 0x06 66 67#define SDHCI_ARGUMENT 0x08 --- 57 unchanged lines hidden (view full) --- 125#define SDHCI_POWER_300 0x0C 126#define SDHCI_POWER_330 0x0E 127 128#define SDHCI_BLOCK_GAP_CONTROL 0x2A 129 130#define SDHCI_WAKE_UP_CONTROL 0x2B 131 132#define SDHCI_CLOCK_CONTROL 0x2C | 64#define SDHCI_DMA_ADDRESS 0x00 65 66#define SDHCI_BLOCK_SIZE 0x04 67#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 68 69#define SDHCI_BLOCK_COUNT 0x06 70 71#define SDHCI_ARGUMENT 0x08 --- 57 unchanged lines hidden (view full) --- 129#define SDHCI_POWER_300 0x0C 130#define SDHCI_POWER_330 0x0E 131 132#define SDHCI_BLOCK_GAP_CONTROL 0x2A 133 134#define SDHCI_WAKE_UP_CONTROL 0x2B 135 136#define SDHCI_CLOCK_CONTROL 0x2C |
| 137#define SDHCI_DIVIDER_MASK 0xff 138#define SDHCI_DIVIDER_MASK_LEN 8 |
|
| 133#define SDHCI_DIVIDER_SHIFT 8 | 139#define SDHCI_DIVIDER_SHIFT 8 |
| 140#define SDHCI_DIVIDER_HI_MASK 3 141#define SDHCI_DIVIDER_HI_SHIFT 6 |
|
| 134#define SDHCI_CLOCK_CARD_EN 0x0004 135#define SDHCI_CLOCK_INT_STABLE 0x0002 136#define SDHCI_CLOCK_INT_EN 0x0001 137 138#define SDHCI_TIMEOUT_CONTROL 0x2E 139 140#define SDHCI_SOFTWARE_RESET 0x2F 141#define SDHCI_RESET_ALL 0x01 --- 57 unchanged lines hidden (view full) --- 199 200#define SDHCI_SLOT_INT_STATUS 0xFC 201 202#define SDHCI_HOST_VERSION 0xFE 203#define SDHCI_VENDOR_VER_MASK 0xFF00 204#define SDHCI_VENDOR_VER_SHIFT 8 205#define SDHCI_SPEC_VER_MASK 0x00FF 206#define SDHCI_SPEC_VER_SHIFT 0 | 142#define SDHCI_CLOCK_CARD_EN 0x0004 143#define SDHCI_CLOCK_INT_STABLE 0x0002 144#define SDHCI_CLOCK_INT_EN 0x0001 145 146#define SDHCI_TIMEOUT_CONTROL 0x2E 147 148#define SDHCI_SOFTWARE_RESET 0x2F 149#define SDHCI_RESET_ALL 0x01 --- 57 unchanged lines hidden (view full) --- 207 208#define SDHCI_SLOT_INT_STATUS 0xFC 209 210#define SDHCI_HOST_VERSION 0xFE 211#define SDHCI_VENDOR_VER_MASK 0xFF00 212#define SDHCI_VENDOR_VER_SHIFT 8 213#define SDHCI_SPEC_VER_MASK 0x00FF 214#define SDHCI_SPEC_VER_SHIFT 0 |
| 215#define SDHCI_SPEC_100 0 216#define SDHCI_SPEC_200 1 217#define SDHCI_SPEC_300 2 |
|
| 207 208struct sdhci_slot { 209 u_int quirks; /* Chip specific quirks */ | 218 219struct sdhci_slot { 220 u_int quirks; /* Chip specific quirks */ |
| 221 u_int caps; /* Override SDHCI_CAPABILITIES */ |
|
| 210 device_t bus; /* Bus device */ 211 device_t dev; /* Slot device */ 212 u_char num; /* Slot number */ 213 u_char opt; /* Slot options */ 214 u_char version; 215#define SDHCI_HAVE_DMA 1 216 uint32_t max_clk; /* Max possible freq */ 217 uint32_t timeout_clk; /* Timeout freq */ --- 40 unchanged lines hidden --- | 222 device_t bus; /* Bus device */ 223 device_t dev; /* Slot device */ 224 u_char num; /* Slot number */ 225 u_char opt; /* Slot options */ 226 u_char version; 227#define SDHCI_HAVE_DMA 1 228 uint32_t max_clk; /* Max possible freq */ 229 uint32_t timeout_clk; /* Timeout freq */ --- 40 unchanged lines hidden --- |