| sdhci.h (231266) | sdhci.h (241600) |
|---|---|
| 1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 8 unchanged lines hidden (view full) --- 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * | 1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 8 unchanged lines hidden (view full) --- 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * |
| 25 * $FreeBSD: head/sys/dev/sdhci/sdhci.h 231266 2012-02-09 10:20:41Z glebius $ | 25 * $FreeBSD: head/sys/dev/sdhci/sdhci.h 241600 2012-10-16 01:10:43Z gonzo $ |
| 26 */ 27 | 26 */ 27 |
| 28/* 29 * PCI registers 30 */ | 28#ifndef __SDHCI_H__ 29#define __SDHCI_H__ |
| 31 | 30 |
| 32#define PCI_SDHCI_IFPIO 0x00 33#define PCI_SDHCI_IFDMA 0x01 34#define PCI_SDHCI_IFVENDOR 0x02 | 31#define DMA_BLOCK_SIZE 4096 32#define DMA_BOUNDARY 0 /* DMA reload every 4K */ |
| 35 | 33 |
| 36#define PCI_SLOT_INFO 0x40 /* 8 bits */ 37#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 38#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) | 34/* Controller doesn't honor resets unless we touch the clock register */ 35#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 36/* Controller really supports DMA */ 37#define SDHCI_QUIRK_FORCE_DMA (1<<1) 38/* Controller has unusable DMA engine */ 39#define SDHCI_QUIRK_BROKEN_DMA (1<<2) 40/* Controller doesn't like to be reset when there is no card inserted. */ 41#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<3) 42/* Controller has flaky internal state so reset it on each ios change */ 43#define SDHCI_QUIRK_RESET_ON_IOS (1<<4) 44/* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 45#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<5) 46/* Controller needs to be reset after each request to stay stable */ 47#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6) 48/* Controller has an off-by-one issue with timeout value */ 49#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7) 50/* Controller has broken read timings */ 51#define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8) 52/* Controller needs lowered frequency */ 53#define SDHCI_QUIRK_LOWER_FREQUENCY (1<<9) |
| 39 | 54 |
| 40/* 41 * RICOH specific PCI registers 42 */ 43#define SDHC_PCI_MODE_KEY 0xf9 44#define SDHC_PCI_MODE 0x150 45#define SDHC_PCI_MODE_SD20 0x10 46#define SDHC_PCI_BASE_FREQ_KEY 0xfc 47#define SDHC_PCI_BASE_FREQ 0xe1 | |
| 48 49/* 50 * Controller registers 51 */ 52 53#define SDHCI_DMA_ADDRESS 0x00 54 55#define SDHCI_BLOCK_SIZE 0x04 --- 136 unchanged lines hidden (view full) --- 192 193#define SDHCI_SLOT_INT_STATUS 0xFC 194 195#define SDHCI_HOST_VERSION 0xFE 196#define SDHCI_VENDOR_VER_MASK 0xFF00 197#define SDHCI_VENDOR_VER_SHIFT 8 198#define SDHCI_SPEC_VER_MASK 0x00FF 199#define SDHCI_SPEC_VER_SHIFT 0 | 55 56/* 57 * Controller registers 58 */ 59 60#define SDHCI_DMA_ADDRESS 0x00 61 62#define SDHCI_BLOCK_SIZE 0x04 --- 136 unchanged lines hidden (view full) --- 199 200#define SDHCI_SLOT_INT_STATUS 0xFC 201 202#define SDHCI_HOST_VERSION 0xFE 203#define SDHCI_VENDOR_VER_MASK 0xFF00 204#define SDHCI_VENDOR_VER_SHIFT 8 205#define SDHCI_SPEC_VER_MASK 0x00FF 206#define SDHCI_SPEC_VER_SHIFT 0 |
| 207 208struct sdhci_slot { 209 u_int quirks; /* Chip specific quirks */ 210 device_t bus; /* Bus device */ 211 device_t dev; /* Slot device */ 212 u_char num; /* Slot number */ 213 u_char opt; /* Slot options */ 214 u_char version; 215#define SDHCI_HAVE_DMA 1 216 uint32_t max_clk; /* Max possible freq */ 217 uint32_t timeout_clk; /* Timeout freq */ 218 bus_dma_tag_t dmatag; 219 bus_dmamap_t dmamap; 220 u_char *dmamem; 221 bus_addr_t paddr; /* DMA buffer address */ 222 struct task card_task; /* Card presence check task */ 223 struct callout card_callout; /* Card insert delay callout */ 224 struct mmc_host host; /* Host parameters */ 225 struct mmc_request *req; /* Current request */ 226 struct mmc_command *curcmd; /* Current command of current request */ 227 228 uint32_t intmask; /* Current interrupt mask */ 229 uint32_t clock; /* Current clock freq. */ 230 size_t offset; /* Data buffer offset */ 231 uint8_t hostctrl; /* Current host control register */ 232 u_char power; /* Current power */ 233 u_char bus_busy; /* Bus busy status */ 234 u_char cmd_done; /* CMD command part done flag */ 235 u_char data_done; /* DAT command part done flag */ 236 u_char flags; /* Request execution flags */ 237#define CMD_STARTED 1 238#define STOP_STARTED 2 239#define SDHCI_USE_DMA 4 /* Use DMA for this req. */ 240 struct mtx mtx; /* Slot mutex */ 241}; 242 243int sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result); 244int sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value); 245int sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num); 246void sdhci_start_slot(struct sdhci_slot *slot); 247int sdhci_cleanup_slot(struct sdhci_slot *slot); 248int sdhci_generic_suspend(struct sdhci_slot *slot); 249int sdhci_generic_resume(struct sdhci_slot *slot); 250int sdhci_generic_update_ios(device_t brdev, device_t reqdev); 251int sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req); 252int sdhci_generic_get_ro(device_t brdev, device_t reqdev); 253int sdhci_generic_acquire_host(device_t brdev, device_t reqdev); 254int sdhci_generic_release_host(device_t brdev, device_t reqdev); 255void sdhci_generic_intr(struct sdhci_slot *slot); 256 257#endif /* __SDHCI_H__ */ |
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