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sdhci.c (238898) sdhci.c (241600)
1/*-
2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 10 unchanged lines hidden (view full) ---

19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 10 unchanged lines hidden (view full) ---

19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD: head/sys/dev/sdhci/sdhci.c 238898 2012-07-30 08:56:56Z glebius $");
27__FBSDID("$FreeBSD: head/sys/dev/sdhci/sdhci.c 241600 2012-10-16 01:10:43Z gonzo $");
28
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/bus.h>
32#include <sys/conf.h>
33#include <sys/kernel.h>
34#include <sys/lock.h>
35#include <sys/module.h>
36#include <sys/mutex.h>
37#include <sys/resource.h>
38#include <sys/rman.h>
39#include <sys/sysctl.h>
40#include <sys/taskqueue.h>
41
28
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/bus.h>
32#include <sys/conf.h>
33#include <sys/kernel.h>
34#include <sys/lock.h>
35#include <sys/module.h>
36#include <sys/mutex.h>
37#include <sys/resource.h>
38#include <sys/rman.h>
39#include <sys/sysctl.h>
40#include <sys/taskqueue.h>
41
42#include <dev/pci/pcireg.h>
43#include <dev/pci/pcivar.h>
44
45#include <machine/bus.h>
46#include <machine/resource.h>
47#include <machine/stdarg.h>
48
49#include <dev/mmc/bridge.h>
50#include <dev/mmc/mmcreg.h>
51#include <dev/mmc/mmcbrvar.h>
52
53#include "mmcbr_if.h"
54#include "sdhci.h"
42#include <machine/bus.h>
43#include <machine/resource.h>
44#include <machine/stdarg.h>
45
46#include <dev/mmc/bridge.h>
47#include <dev/mmc/mmcreg.h>
48#include <dev/mmc/mmcbrvar.h>
49
50#include "mmcbr_if.h"
51#include "sdhci.h"
52#include "sdhci_if.h"
55
53
56#define DMA_BLOCK_SIZE 4096
57#define DMA_BOUNDARY 0 /* DMA reload every 4K */
58
59/* Controller doesn't honor resets unless we touch the clock register */
60#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
61/* Controller really supports DMA */
62#define SDHCI_QUIRK_FORCE_DMA (1<<1)
63/* Controller has unusable DMA engine */
64#define SDHCI_QUIRK_BROKEN_DMA (1<<2)
65/* Controller doesn't like to be reset when there is no card inserted. */
66#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<3)
67/* Controller has flaky internal state so reset it on each ios change */
68#define SDHCI_QUIRK_RESET_ON_IOS (1<<4)
69/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
70#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<5)
71/* Controller needs to be reset after each request to stay stable */
72#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6)
73/* Controller has an off-by-one issue with timeout value */
74#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7)
75/* Controller has broken read timings */
76#define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8)
77/* Controller needs lowered frequency */
78#define SDHCI_QUIRK_LOWER_FREQUENCY (1<<9)
79
80static const struct sdhci_device {
81 uint32_t model;
82 uint16_t subvendor;
83 char *desc;
84 u_int quirks;
85} sdhci_devices[] = {
86 { 0x08221180, 0xffff, "RICOH R5C822 SD",
87 SDHCI_QUIRK_FORCE_DMA },
88 { 0xe8221180, 0xffff, "RICOH SD",
89 SDHCI_QUIRK_FORCE_DMA },
90 { 0xe8231180, 0xffff, "RICOH R5CE823 SD",
91 SDHCI_QUIRK_LOWER_FREQUENCY },
92 { 0x8034104c, 0xffff, "TI XX21/XX11 SD",
93 SDHCI_QUIRK_FORCE_DMA },
94 { 0x05501524, 0xffff, "ENE CB712 SD",
95 SDHCI_QUIRK_BROKEN_TIMINGS },
96 { 0x05511524, 0xffff, "ENE CB712 SD 2",
97 SDHCI_QUIRK_BROKEN_TIMINGS },
98 { 0x07501524, 0xffff, "ENE CB714 SD",
99 SDHCI_QUIRK_RESET_ON_IOS |
100 SDHCI_QUIRK_BROKEN_TIMINGS },
101 { 0x07511524, 0xffff, "ENE CB714 SD 2",
102 SDHCI_QUIRK_RESET_ON_IOS |
103 SDHCI_QUIRK_BROKEN_TIMINGS },
104 { 0x410111ab, 0xffff, "Marvell CaFe SD",
105 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL },
106 { 0x2381197B, 0xffff, "JMicron JMB38X SD",
107 SDHCI_QUIRK_32BIT_DMA_SIZE |
108 SDHCI_QUIRK_RESET_AFTER_REQUEST },
109 { 0, 0xffff, NULL,
110 0 }
111};
112
113struct sdhci_softc;
114
54struct sdhci_softc;
55
115struct sdhci_slot {
116 struct sdhci_softc *sc;
117 device_t dev; /* Slot device */
118 u_char num; /* Slot number */
119 u_char opt; /* Slot options */
120#define SDHCI_HAVE_DMA 1
121 uint32_t max_clk; /* Max possible freq */
122 uint32_t timeout_clk; /* Timeout freq */
123 struct resource *mem_res; /* Memory resource */
124 int mem_rid;
125 bus_dma_tag_t dmatag;
126 bus_dmamap_t dmamap;
127 u_char *dmamem;
128 bus_addr_t paddr; /* DMA buffer address */
129 struct task card_task; /* Card presence check task */
130 struct callout card_callout; /* Card insert delay callout */
131 struct mmc_host host; /* Host parameters */
132 struct mmc_request *req; /* Current request */
133 struct mmc_command *curcmd; /* Current command of current request */
134
135 uint32_t intmask; /* Current interrupt mask */
136 uint32_t clock; /* Current clock freq. */
137 size_t offset; /* Data buffer offset */
138 uint8_t hostctrl; /* Current host control register */
139 u_char power; /* Current power */
140 u_char bus_busy; /* Bus busy status */
141 u_char cmd_done; /* CMD command part done flag */
142 u_char data_done; /* DAT command part done flag */
143 u_char flags; /* Request execution flags */
144#define CMD_STARTED 1
145#define STOP_STARTED 2
146#define SDHCI_USE_DMA 4 /* Use DMA for this req. */
147 struct mtx mtx; /* Slot mutex */
148};
149
150struct sdhci_softc {
151 device_t dev; /* Controller device */
56struct sdhci_softc {
57 device_t dev; /* Controller device */
152 u_int quirks; /* Chip specific quirks */
153 struct resource *irq_res; /* IRQ resource */
154 int irq_rid;
155 void *intrhand; /* Interrupt handle */
156
157 int num_slots; /* Number of slots on this controller */
158 struct sdhci_slot slots[6];
159};
160
161static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
162
58 struct resource *irq_res; /* IRQ resource */
59 int irq_rid;
60 void *intrhand; /* Interrupt handle */
61
62 int num_slots; /* Number of slots on this controller */
63 struct sdhci_slot slots[6];
64};
65
66static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
67
163int sdhci_debug;
68int sdhci_debug = 0;
164TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
165SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level");
166
69TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
70SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level");
71
167static inline uint8_t
168RD1(struct sdhci_slot *slot, bus_size_t off)
169{
170 bus_barrier(slot->mem_res, 0, 0xFF,
171 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
172 return bus_read_1(slot->mem_res, off);
173}
72#define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
73#define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
74#define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
75#define RD_MULTI_4(slot, off, ptr, count) \
76 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
174
77
175static inline void
176WR1(struct sdhci_slot *slot, bus_size_t off, uint8_t val)
177{
178 bus_barrier(slot->mem_res, 0, 0xFF,
179 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
180 bus_write_1(slot->mem_res, off, val);
181}
78#define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
79#define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
80#define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
81#define WR_MULTI_4(slot, off, ptr, count) \
82 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
182
83
183static inline uint16_t
184RD2(struct sdhci_slot *slot, bus_size_t off)
185{
186 bus_barrier(slot->mem_res, 0, 0xFF,
187 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
188 return bus_read_2(slot->mem_res, off);
189}
190
191static inline void
192WR2(struct sdhci_slot *slot, bus_size_t off, uint16_t val)
193{
194 bus_barrier(slot->mem_res, 0, 0xFF,
195 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
196 bus_write_2(slot->mem_res, off, val);
197}
198
199static inline uint32_t
200RD4(struct sdhci_slot *slot, bus_size_t off)
201{
202 bus_barrier(slot->mem_res, 0, 0xFF,
203 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
204 return bus_read_4(slot->mem_res, off);
205}
206
207static inline void
208WR4(struct sdhci_slot *slot, bus_size_t off, uint32_t val)
209{
210 bus_barrier(slot->mem_res, 0, 0xFF,
211 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
212 bus_write_4(slot->mem_res, off, val);
213}
214
215/* bus entry points */
216static int sdhci_probe(device_t dev);
217static int sdhci_attach(device_t dev);
218static int sdhci_detach(device_t dev);
219static void sdhci_intr(void *);
220
221static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
222static void sdhci_start(struct sdhci_slot *slot);
223static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
224
225static void sdhci_card_task(void *, int);
226
227/* helper routines */
228#define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
229#define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
230#define SDHCI_LOCK_INIT(_slot) \
231 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
232#define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
233#define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
234#define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
235
84static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
85static void sdhci_start(struct sdhci_slot *slot);
86static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
87
88static void sdhci_card_task(void *, int);
89
90/* helper routines */
91#define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
92#define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
93#define SDHCI_LOCK_INIT(_slot) \
94 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
95#define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
96#define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
97#define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
98
99static void
100sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
101{
102 if (error != 0) {
103 printf("getaddr: error %d\n", error);
104 return;
105 }
106 *(bus_addr_t *)arg = segs[0].ds_addr;
107}
108
236static int
237slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
238{
239 va_list ap;
240 int retval;
241
242 retval = printf("%s-slot%d: ",
109static int
110slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
111{
112 va_list ap;
113 int retval;
114
115 retval = printf("%s-slot%d: ",
243 device_get_nameunit(slot->sc->dev), slot->num);
116 device_get_nameunit(slot->bus), slot->num);
244
245 va_start(ap, fmt);
246 retval += vprintf(fmt, ap);
247 va_end(ap);
248 return (retval);
249}
250
251static void
117
118 va_start(ap, fmt);
119 retval += vprintf(fmt, ap);
120 va_end(ap);
121 return (retval);
122}
123
124static void
252sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
253{
254 if (error != 0) {
255 printf("getaddr: error %d\n", error);
256 return;
257 }
258 *(bus_addr_t *)arg = segs[0].ds_addr;
259}
260
261static void
262sdhci_dumpregs(struct sdhci_slot *slot)
263{
264 slot_printf(slot,
265 "============== REGISTER DUMP ==============\n");
266
267 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n",
268 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
269 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",

--- 20 unchanged lines hidden (view full) ---

290}
291
292static void
293sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
294{
295 int timeout;
296 uint8_t res;
297
125sdhci_dumpregs(struct sdhci_slot *slot)
126{
127 slot_printf(slot,
128 "============== REGISTER DUMP ==============\n");
129
130 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n",
131 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
132 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",

--- 20 unchanged lines hidden (view full) ---

153}
154
155static void
156sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
157{
158 int timeout;
159 uint8_t res;
160
298 if (slot->sc->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
161 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
299 if (!(RD4(slot, SDHCI_PRESENT_STATE) &
300 SDHCI_CARD_PRESENT))
301 return;
302 }
303
304 /* Some controllers need this kick or reset won't work. */
305 if ((mask & SDHCI_RESET_ALL) == 0 &&
162 if (!(RD4(slot, SDHCI_PRESENT_STATE) &
163 SDHCI_CARD_PRESENT))
164 return;
165 }
166
167 /* Some controllers need this kick or reset won't work. */
168 if ((mask & SDHCI_RESET_ALL) == 0 &&
306 (slot->sc->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
169 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
307 uint32_t clock;
308
309 /* This is to force an update */
310 clock = slot->clock;
311 slot->clock = 0;
312 sdhci_set_clock(slot, clock);
313 }
314

--- 34 unchanged lines hidden (view full) ---

349 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
350 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
351 SDHCI_INT_ACMD12ERR;
352 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
353 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
354}
355
356static void
170 uint32_t clock;
171
172 /* This is to force an update */
173 clock = slot->clock;
174 slot->clock = 0;
175 sdhci_set_clock(slot, clock);
176 }
177

--- 34 unchanged lines hidden (view full) ---

212 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
213 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
214 SDHCI_INT_ACMD12ERR;
215 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
216 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
217}
218
219static void
357sdhci_lower_frequency(device_t dev)
358{
359
360 /* Enable SD2.0 mode. */
361 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
362 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1);
363 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
364
365 /*
366 * Some SD/MMC cards don't work with the default base
367 * clock frequency of 200MHz. Lower it to 50MHz.
368 */
369 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
370 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1);
371 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
372}
373
374static void
375sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
376{
377 uint32_t res;
378 uint16_t clk;
379 int timeout;
380
381 if (clock == slot->clock)
382 return;

--- 39 unchanged lines hidden (view full) ---

422
423static void
424sdhci_set_power(struct sdhci_slot *slot, u_char power)
425{
426 uint8_t pwr;
427
428 if (slot->power == power)
429 return;
220sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
221{
222 uint32_t res;
223 uint16_t clk;
224 int timeout;
225
226 if (clock == slot->clock)
227 return;

--- 39 unchanged lines hidden (view full) ---

267
268static void
269sdhci_set_power(struct sdhci_slot *slot, u_char power)
270{
271 uint8_t pwr;
272
273 if (slot->power == power)
274 return;
275
430 slot->power = power;
431
432 /* Turn off the power. */
433 pwr = 0;
434 WR1(slot, SDHCI_POWER_CONTROL, pwr);
435 /* If power down requested - left it so. */
436 if (power == 0)
437 return;

--- 26 unchanged lines hidden (view full) ---

464
465 buffer = slot->curcmd->data->data;
466 buffer += slot->offset;
467 /* Transfer one block at a time. */
468 left = min(512, slot->curcmd->data->len - slot->offset);
469 slot->offset += left;
470
471 /* If we are too fast, broken controllers return zeroes. */
276 slot->power = power;
277
278 /* Turn off the power. */
279 pwr = 0;
280 WR1(slot, SDHCI_POWER_CONTROL, pwr);
281 /* If power down requested - left it so. */
282 if (power == 0)
283 return;

--- 26 unchanged lines hidden (view full) ---

310
311 buffer = slot->curcmd->data->data;
312 buffer += slot->offset;
313 /* Transfer one block at a time. */
314 left = min(512, slot->curcmd->data->len - slot->offset);
315 slot->offset += left;
316
317 /* If we are too fast, broken controllers return zeroes. */
472 if (slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
318 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
473 DELAY(10);
474 /* Handle unalligned and alligned buffer cases. */
475 if ((intptr_t)buffer & 3) {
476 while (left > 3) {
477 data = RD4(slot, SDHCI_BUFFER);
478 buffer[0] = data;
479 buffer[1] = (data >> 8);
480 buffer[2] = (data >> 16);
481 buffer[3] = (data >> 24);
482 buffer += 4;
483 left -= 4;
484 }
485 } else {
319 DELAY(10);
320 /* Handle unalligned and alligned buffer cases. */
321 if ((intptr_t)buffer & 3) {
322 while (left > 3) {
323 data = RD4(slot, SDHCI_BUFFER);
324 buffer[0] = data;
325 buffer[1] = (data >> 8);
326 buffer[2] = (data >> 16);
327 buffer[3] = (data >> 24);
328 buffer += 4;
329 left -= 4;
330 }
331 } else {
486 bus_read_multi_stream_4(slot->mem_res, SDHCI_BUFFER,
332 RD_MULTI_4(slot, SDHCI_BUFFER,
487 (uint32_t *)buffer, left >> 2);
488 left &= 3;
489 }
490 /* Handle uneven size case. */
491 if (left > 0) {
492 data = RD4(slot, SDHCI_BUFFER);
493 while (left > 0) {
494 *(buffer++) = data;

--- 23 unchanged lines hidden (view full) ---

518 (buffer[1] << 8) +
519 (buffer[2] << 16) +
520 (buffer[3] << 24);
521 left -= 4;
522 buffer += 4;
523 WR4(slot, SDHCI_BUFFER, data);
524 }
525 } else {
333 (uint32_t *)buffer, left >> 2);
334 left &= 3;
335 }
336 /* Handle uneven size case. */
337 if (left > 0) {
338 data = RD4(slot, SDHCI_BUFFER);
339 while (left > 0) {
340 *(buffer++) = data;

--- 23 unchanged lines hidden (view full) ---

364 (buffer[1] << 8) +
365 (buffer[2] << 16) +
366 (buffer[3] << 24);
367 left -= 4;
368 buffer += 4;
369 WR4(slot, SDHCI_BUFFER, data);
370 }
371 } else {
526 bus_write_multi_stream_4(slot->mem_res, SDHCI_BUFFER,
372 WR_MULTI_4(slot, SDHCI_BUFFER,
527 (uint32_t *)buffer, left >> 2);
528 left &= 3;
529 }
530 /* Handle uneven size case. */
531 if (left > 0) {
532 while (left > 0) {
533 data <<= 8;
534 data += *(buffer++);

--- 37 unchanged lines hidden (view full) ---

572sdhci_card_task(void *arg, int pending)
573{
574 struct sdhci_slot *slot = arg;
575
576 SDHCI_LOCK(slot);
577 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) {
578 if (slot->dev == NULL) {
579 /* If card is present - attach mmc bus. */
373 (uint32_t *)buffer, left >> 2);
374 left &= 3;
375 }
376 /* Handle uneven size case. */
377 if (left > 0) {
378 while (left > 0) {
379 data <<= 8;
380 data += *(buffer++);

--- 37 unchanged lines hidden (view full) ---

418sdhci_card_task(void *arg, int pending)
419{
420 struct sdhci_slot *slot = arg;
421
422 SDHCI_LOCK(slot);
423 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) {
424 if (slot->dev == NULL) {
425 /* If card is present - attach mmc bus. */
580 slot->dev = device_add_child(slot->sc->dev, "mmc", -1);
426 slot->dev = device_add_child(slot->bus, "mmc", -1);
581 device_set_ivars(slot->dev, slot);
582 SDHCI_UNLOCK(slot);
583 device_probe_and_attach(slot->dev);
584 } else
585 SDHCI_UNLOCK(slot);
586 } else {
587 if (slot->dev != NULL) {
588 /* If no card present - detach mmc bus. */
589 device_t d = slot->dev;
590 slot->dev = NULL;
591 SDHCI_UNLOCK(slot);
427 device_set_ivars(slot->dev, slot);
428 SDHCI_UNLOCK(slot);
429 device_probe_and_attach(slot->dev);
430 } else
431 SDHCI_UNLOCK(slot);
432 } else {
433 if (slot->dev != NULL) {
434 /* If no card present - detach mmc bus. */
435 device_t d = slot->dev;
436 slot->dev = NULL;
437 SDHCI_UNLOCK(slot);
592 device_delete_child(slot->sc->dev, d);
438 device_delete_child(slot->bus, d);
593 } else
594 SDHCI_UNLOCK(slot);
595 }
596}
597
439 } else
440 SDHCI_UNLOCK(slot);
441 }
442}
443
598static int
599sdhci_probe(device_t dev)
444int
445sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
600{
446{
601 uint32_t model;
602 uint16_t subvendor;
603 uint8_t class, subclass;
604 int i, result;
605
606 model = (uint32_t)pci_get_device(dev) << 16;
607 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
608 subvendor = pci_get_subvendor(dev);
609 class = pci_get_class(dev);
610 subclass = pci_get_subclass(dev);
611
612 result = ENXIO;
613 for (i = 0; sdhci_devices[i].model != 0; i++) {
614 if (sdhci_devices[i].model == model &&
615 (sdhci_devices[i].subvendor == 0xffff ||
616 sdhci_devices[i].subvendor == subvendor)) {
617 device_set_desc(dev, sdhci_devices[i].desc);
618 result = BUS_PROBE_DEFAULT;
619 break;
620 }
621 }
622 if (result == ENXIO && class == PCIC_BASEPERIPH &&
623 subclass == PCIS_BASEPERIPH_SDHC) {
624 device_set_desc(dev, "Generic SD HCI");
625 result = BUS_PROBE_GENERIC;
626 }
627
628 return (result);
629}
447 uint32_t caps;
448 int err;
630
449
631static int
632sdhci_attach(device_t dev)
633{
634 struct sdhci_softc *sc = device_get_softc(dev);
635 uint32_t model;
636 uint16_t subvendor;
637 uint8_t class, subclass, progif;
638 int err, slots, bar, i;
450 SDHCI_LOCK_INIT(slot);
451 slot->num = num;
452 slot->bus = dev;
639
453
640 sc->dev = dev;
641 model = (uint32_t)pci_get_device(dev) << 16;
642 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
643 subvendor = pci_get_subvendor(dev);
644 class = pci_get_class(dev);
645 subclass = pci_get_subclass(dev);
646 progif = pci_get_progif(dev);
647 /* Apply chip specific quirks. */
648 for (i = 0; sdhci_devices[i].model != 0; i++) {
649 if (sdhci_devices[i].model == model &&
650 (sdhci_devices[i].subvendor == 0xffff ||
651 sdhci_devices[i].subvendor == subvendor)) {
652 sc->quirks = sdhci_devices[i].quirks;
653 break;
654 }
454 /* Allocate DMA tag. */
455 err = bus_dma_tag_create(bus_get_dma_tag(dev),
456 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
457 BUS_SPACE_MAXADDR, NULL, NULL,
458 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
459 BUS_DMA_ALLOCNOW, NULL, NULL,
460 &slot->dmatag);
461 if (err != 0) {
462 device_printf(dev, "Can't create DMA tag\n");
463 SDHCI_LOCK_DESTROY(slot);
464 return (err);
655 }
465 }
656 /* Some controllers need to be bumped into the right mode. */
657 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
658 sdhci_lower_frequency(dev);
659 /* Read slots info from PCI registers. */
660 slots = pci_read_config(dev, PCI_SLOT_INFO, 1);
661 bar = PCI_SLOT_INFO_FIRST_BAR(slots);
662 slots = PCI_SLOT_INFO_SLOTS(slots);
663 if (slots > 6 || bar > 5) {
664 device_printf(dev, "Incorrect slots information (%d, %d).\n",
665 slots, bar);
666 return (EINVAL);
466 /* Allocate DMA memory. */
467 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
468 BUS_DMA_NOWAIT, &slot->dmamap);
469 if (err != 0) {
470 device_printf(dev, "Can't alloc DMA memory\n");
471 SDHCI_LOCK_DESTROY(slot);
472 return (err);
667 }
473 }
668 /* Allocate IRQ. */
669 sc->irq_rid = 0;
670 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
671 RF_SHAREABLE | RF_ACTIVE);
672 if (sc->irq_res == NULL) {
673 device_printf(dev, "Can't allocate IRQ\n");
674 return (ENOMEM);
474 /* Map the memory. */
475 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
476 (void *)slot->dmamem, DMA_BLOCK_SIZE,
477 sdhci_getaddr, &slot->paddr, 0);
478 if (err != 0 || slot->paddr == 0) {
479 device_printf(dev, "Can't load DMA memory\n");
480 SDHCI_LOCK_DESTROY(slot);
481 if(err)
482 return (err);
483 else
484 return (EFAULT);
675 }
485 }
676 /* Scan all slots. */
677 for (i = 0; i < slots; i++) {
678 struct sdhci_slot *slot = &sc->slots[sc->num_slots];
679 uint32_t caps;
680
486
681 SDHCI_LOCK_INIT(slot);
682 slot->sc = sc;
683 slot->num = sc->num_slots;
684 /* Allocate memory. */
685 slot->mem_rid = PCIR_BAR(bar + i);
686 slot->mem_res = bus_alloc_resource(dev,
687 SYS_RES_MEMORY, &slot->mem_rid, 0ul, ~0ul, 0x100, RF_ACTIVE);
688 if (slot->mem_res == NULL) {
689 device_printf(dev, "Can't allocate memory\n");
690 SDHCI_LOCK_DESTROY(slot);
691 continue;
692 }
693 /* Allocate DMA tag. */
694 err = bus_dma_tag_create(bus_get_dma_tag(dev),
695 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
696 BUS_SPACE_MAXADDR, NULL, NULL,
697 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
698 BUS_DMA_ALLOCNOW, NULL, NULL,
699 &slot->dmatag);
700 if (err != 0) {
701 device_printf(dev, "Can't create DMA tag\n");
702 SDHCI_LOCK_DESTROY(slot);
703 continue;
704 }
705 /* Allocate DMA memory. */
706 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
707 BUS_DMA_NOWAIT, &slot->dmamap);
708 if (err != 0) {
709 device_printf(dev, "Can't alloc DMA memory\n");
710 SDHCI_LOCK_DESTROY(slot);
711 continue;
712 }
713 /* Map the memory. */
714 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
715 (void *)slot->dmamem, DMA_BLOCK_SIZE,
716 sdhci_getaddr, &slot->paddr, 0);
717 if (err != 0 || slot->paddr == 0) {
718 device_printf(dev, "Can't load DMA memory\n");
719 SDHCI_LOCK_DESTROY(slot);
720 continue;
721 }
722 /* Initialize slot. */
723 sdhci_init(slot);
724 caps = RD4(slot, SDHCI_CAPABILITIES);
725 /* Calculate base clock frequency. */
726 slot->max_clk =
727 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
728 if (slot->max_clk == 0) {
729 device_printf(dev, "Hardware doesn't specify base clock "
730 "frequency.\n");
731 }
732 slot->max_clk *= 1000000;
733 /* Calculate timeout clock frequency. */
734 slot->timeout_clk =
735 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
736 if (slot->timeout_clk == 0) {
737 device_printf(dev, "Hardware doesn't specify timeout clock "
738 "frequency.\n");
739 }
740 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
741 slot->timeout_clk *= 1000;
487 /* Initialize slot. */
488 sdhci_init(slot);
489 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
490 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
491 caps = RD4(slot, SDHCI_CAPABILITIES);
492 /* Calculate base clock frequency. */
493 slot->max_clk =
494 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
495 if (slot->max_clk == 0) {
496 slot->max_clk = 50;
497 device_printf(dev, "Hardware doesn't specify base clock "
498 "frequency.\n");
499 }
500 slot->max_clk *= 1000000;
501 /* Calculate timeout clock frequency. */
502 slot->timeout_clk =
503 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
504 if (slot->timeout_clk == 0) {
505 device_printf(dev, "Hardware doesn't specify timeout clock "
506 "frequency.\n");
507 }
508 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
509 slot->timeout_clk *= 1000;
742
510
743 slot->host.f_min = slot->max_clk / 256;
744 slot->host.f_max = slot->max_clk;
745 slot->host.host_ocr = 0;
746 if (caps & SDHCI_CAN_VDD_330)
747 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
748 if (caps & SDHCI_CAN_VDD_300)
749 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
750 if (caps & SDHCI_CAN_VDD_180)
751 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
752 if (slot->host.host_ocr == 0) {
753 device_printf(dev, "Hardware doesn't report any "
754 "support voltages.\n");
755 }
756 slot->host.caps = MMC_CAP_4_BIT_DATA;
757 if (caps & SDHCI_CAN_DO_HISPD)
758 slot->host.caps |= MMC_CAP_HSPEED;
759 /* Decide if we have usable DMA. */
760 if (caps & SDHCI_CAN_DO_DMA)
761 slot->opt |= SDHCI_HAVE_DMA;
762 if (class == PCIC_BASEPERIPH &&
763 subclass == PCIS_BASEPERIPH_SDHC &&
764 progif != PCI_SDHCI_IFDMA)
765 slot->opt &= ~SDHCI_HAVE_DMA;
766 if (sc->quirks & SDHCI_QUIRK_BROKEN_DMA)
767 slot->opt &= ~SDHCI_HAVE_DMA;
768 if (sc->quirks & SDHCI_QUIRK_FORCE_DMA)
769 slot->opt |= SDHCI_HAVE_DMA;
770
771 if (bootverbose || sdhci_debug) {
772 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n",
773 slot->max_clk / 1000000,
774 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
775 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
776 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
777 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",
778 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO");
779 sdhci_dumpregs(slot);
780 }
781
782 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
783 callout_init(&slot->card_callout, 1);
784 sc->num_slots++;
511 slot->host.f_min = slot->max_clk / 256;
512 slot->host.f_max = slot->max_clk;
513 slot->host.host_ocr = 0;
514 if (caps & SDHCI_CAN_VDD_330)
515 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
516 if (caps & SDHCI_CAN_VDD_300)
517 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
518 if (caps & SDHCI_CAN_VDD_180)
519 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
520 if (slot->host.host_ocr == 0) {
521 device_printf(dev, "Hardware doesn't report any "
522 "support voltages.\n");
785 }
523 }
786 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
787 /* Activate the interrupt */
788 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
789 NULL, sdhci_intr, sc, &sc->intrhand);
790 if (err)
791 device_printf(dev, "Can't setup IRQ\n");
792 pci_enable_busmaster(dev);
793 /* Process cards detection. */
794 for (i = 0; i < sc->num_slots; i++) {
795 struct sdhci_slot *slot = &sc->slots[i];
524 slot->host.caps = MMC_CAP_4_BIT_DATA;
525 if (caps & SDHCI_CAN_DO_HISPD)
526 slot->host.caps |= MMC_CAP_HSPEED;
527 /* Decide if we have usable DMA. */
528 if (caps & SDHCI_CAN_DO_DMA)
529 slot->opt |= SDHCI_HAVE_DMA;
796
530
797 sdhci_card_task(slot, 0);
531 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
532 slot->opt &= ~SDHCI_HAVE_DMA;
533 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
534 slot->opt |= SDHCI_HAVE_DMA;
535
536 if (bootverbose || sdhci_debug) {
537 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n",
538 slot->max_clk / 1000000,
539 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
540 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
541 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
542 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",
543 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO");
544 sdhci_dumpregs(slot);
798 }
545 }
799
546
547 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
548 callout_init(&slot->card_callout, 1);
800 return (0);
801}
802
549 return (0);
550}
551
803static int
804sdhci_detach(device_t dev)
552void
553sdhci_start_slot(struct sdhci_slot *slot)
805{
554{
806 struct sdhci_softc *sc = device_get_softc(dev);
807 int i;
555 sdhci_card_task(slot, 0);
556}
808
557
809 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
810 bus_release_resource(dev, SYS_RES_IRQ,
811 sc->irq_rid, sc->irq_res);
558int
559sdhci_cleanup_slot(struct sdhci_slot *slot)
560{
561 device_t d;
812
562
813 for (i = 0; i < sc->num_slots; i++) {
814 struct sdhci_slot *slot = &sc->slots[i];
815 device_t d;
563 callout_drain(&slot->card_callout);
564 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
816
565
817 callout_drain(&slot->card_callout);
818 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
566 SDHCI_LOCK(slot);
567 d = slot->dev;
568 slot->dev = NULL;
569 SDHCI_UNLOCK(slot);
570 if (d != NULL)
571 device_delete_child(slot->bus, d);
819
572
820 SDHCI_LOCK(slot);
821 d = slot->dev;
822 slot->dev = NULL;
823 SDHCI_UNLOCK(slot);
824 if (d != NULL)
825 device_delete_child(dev, d);
573 SDHCI_LOCK(slot);
574 sdhci_reset(slot, SDHCI_RESET_ALL);
575 SDHCI_UNLOCK(slot);
576 bus_dmamap_unload(slot->dmatag, slot->dmamap);
577 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
578 bus_dma_tag_destroy(slot->dmatag);
826
579
827 SDHCI_LOCK(slot);
828 sdhci_reset(slot, SDHCI_RESET_ALL);
829 SDHCI_UNLOCK(slot);
830 bus_dmamap_unload(slot->dmatag, slot->dmamap);
831 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
832 bus_dma_tag_destroy(slot->dmatag);
833 bus_release_resource(dev, SYS_RES_MEMORY,
834 slot->mem_rid, slot->mem_res);
835 SDHCI_LOCK_DESTROY(slot);
836 }
580 SDHCI_LOCK_DESTROY(slot);
581
837 return (0);
838}
839
582 return (0);
583}
584
840static int
841sdhci_suspend(device_t dev)
585int
586sdhci_generic_suspend(struct sdhci_slot *slot)
842{
587{
843 struct sdhci_softc *sc = device_get_softc(dev);
844 int i, err;
588 sdhci_reset(slot, SDHCI_RESET_ALL);
845
589
846 err = bus_generic_suspend(dev);
847 if (err)
848 return (err);
849 for (i = 0; i < sc->num_slots; i++)
850 sdhci_reset(&sc->slots[i], SDHCI_RESET_ALL);
851 return (0);
852}
853
590 return (0);
591}
592
854static int
855sdhci_resume(device_t dev)
593int
594sdhci_generic_resume(struct sdhci_slot *slot)
856{
595{
857 struct sdhci_softc *sc = device_get_softc(dev);
858 int i;
596 sdhci_init(slot);
859
597
860 for (i = 0; i < sc->num_slots; i++)
861 sdhci_init(&sc->slots[i]);
862 return (bus_generic_resume(dev));
598 return (0);
863}
864
599}
600
865static int
866sdhci_update_ios(device_t brdev, device_t reqdev)
601int
602sdhci_generic_update_ios(device_t brdev, device_t reqdev)
867{
868 struct sdhci_slot *slot = device_get_ivars(reqdev);
869 struct mmc_ios *ios = &slot->host.ios;
870
871 SDHCI_LOCK(slot);
872 /* Do full reset on bus power down to clear from any state. */
873 if (ios->power_mode == power_off) {
874 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);

--- 7 unchanged lines hidden (view full) ---

882 else
883 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
884 if (ios->timing == bus_timing_hs)
885 slot->hostctrl |= SDHCI_CTRL_HISPD;
886 else
887 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
888 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
889 /* Some controllers like reset after bus changes. */
603{
604 struct sdhci_slot *slot = device_get_ivars(reqdev);
605 struct mmc_ios *ios = &slot->host.ios;
606
607 SDHCI_LOCK(slot);
608 /* Do full reset on bus power down to clear from any state. */
609 if (ios->power_mode == power_off) {
610 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);

--- 7 unchanged lines hidden (view full) ---

618 else
619 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
620 if (ios->timing == bus_timing_hs)
621 slot->hostctrl |= SDHCI_CTRL_HISPD;
622 else
623 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
624 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
625 /* Some controllers like reset after bus changes. */
890 if(slot->sc->quirks & SDHCI_QUIRK_RESET_ON_IOS)
626 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
891 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
892
893 SDHCI_UNLOCK(slot);
894 return (0);
895}
896
897static void
898sdhci_set_transfer_mode(struct sdhci_slot *slot,

--- 105 unchanged lines hidden (view full) ---

1004 if (slot->data_done == 0) {
1005 WR4(slot, SDHCI_SIGNAL_ENABLE,
1006 slot->intmask &= ~SDHCI_INT_RESPONSE);
1007 }
1008 /* Set command argument. */
1009 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
1010 /* Set data transfer mode. */
1011 sdhci_set_transfer_mode(slot, cmd->data);
627 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
628
629 SDHCI_UNLOCK(slot);
630 return (0);
631}
632
633static void
634sdhci_set_transfer_mode(struct sdhci_slot *slot,

--- 105 unchanged lines hidden (view full) ---

740 if (slot->data_done == 0) {
741 WR4(slot, SDHCI_SIGNAL_ENABLE,
742 slot->intmask &= ~SDHCI_INT_RESPONSE);
743 }
744 /* Set command argument. */
745 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
746 /* Set data transfer mode. */
747 sdhci_set_transfer_mode(slot, cmd->data);
1012 /* Set command flags. */
1013 WR1(slot, SDHCI_COMMAND_FLAGS, flags);
1014 /* Start command. */
748 /* Start command. */
1015 WR1(slot, SDHCI_COMMAND, cmd->opcode);
749 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
1016}
1017
1018static void
1019sdhci_finish_command(struct sdhci_slot *slot)
1020{
1021 int i;
1022
1023 slot->cmd_done = 1;

--- 46 unchanged lines hidden (view full) ---

1070 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1071 while (current_timeout < target_timeout) {
1072 div++;
1073 current_timeout <<= 1;
1074 if (div >= 0xF)
1075 break;
1076 }
1077 /* Compensate for an off-by-one error in the CaFe chip.*/
750}
751
752static void
753sdhci_finish_command(struct sdhci_slot *slot)
754{
755 int i;
756
757 slot->cmd_done = 1;

--- 46 unchanged lines hidden (view full) ---

804 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
805 while (current_timeout < target_timeout) {
806 div++;
807 current_timeout <<= 1;
808 if (div >= 0xF)
809 break;
810 }
811 /* Compensate for an off-by-one error in the CaFe chip.*/
1078 if (slot->sc->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)
812 if (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)
1079 div++;
1080 if (div >= 0xF) {
1081 slot_printf(slot, "Timeout too large!\n");
1082 div = 0xE;
1083 }
1084 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
1085
1086 if (data == NULL)
1087 return;
1088
1089 /* Use DMA if possible. */
1090 if ((slot->opt & SDHCI_HAVE_DMA))
1091 slot->flags |= SDHCI_USE_DMA;
1092 /* If data is small, broken DMA may return zeroes instead of data, */
813 div++;
814 if (div >= 0xF) {
815 slot_printf(slot, "Timeout too large!\n");
816 div = 0xE;
817 }
818 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
819
820 if (data == NULL)
821 return;
822
823 /* Use DMA if possible. */
824 if ((slot->opt & SDHCI_HAVE_DMA))
825 slot->flags |= SDHCI_USE_DMA;
826 /* If data is small, broken DMA may return zeroes instead of data, */
1093 if ((slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
827 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1094 (data->len <= 512))
1095 slot->flags &= ~SDHCI_USE_DMA;
1096 /* Some controllers require even block sizes. */
828 (data->len <= 512))
829 slot->flags &= ~SDHCI_USE_DMA;
830 /* Some controllers require even block sizes. */
1097 if ((slot->sc->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
831 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1098 ((data->len) & 0x3))
1099 slot->flags &= ~SDHCI_USE_DMA;
1100 /* Load DMA buffer. */
1101 if (slot->flags & SDHCI_USE_DMA) {
1102 if (data->flags & MMC_DATA_READ)
1103 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD);
1104 else {
1105 memcpy(slot->dmamem, data->data,

--- 72 unchanged lines hidden (view full) ---

1178 slot->flags |= STOP_STARTED;
1179 sdhci_start_command(slot, req->stop);
1180 return;
1181 }
1182*/
1183 if (sdhci_debug > 1)
1184 slot_printf(slot, "result: %d\n", req->cmd->error);
1185 if (!req->cmd->error &&
832 ((data->len) & 0x3))
833 slot->flags &= ~SDHCI_USE_DMA;
834 /* Load DMA buffer. */
835 if (slot->flags & SDHCI_USE_DMA) {
836 if (data->flags & MMC_DATA_READ)
837 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD);
838 else {
839 memcpy(slot->dmamem, data->data,

--- 72 unchanged lines hidden (view full) ---

912 slot->flags |= STOP_STARTED;
913 sdhci_start_command(slot, req->stop);
914 return;
915 }
916*/
917 if (sdhci_debug > 1)
918 slot_printf(slot, "result: %d\n", req->cmd->error);
919 if (!req->cmd->error &&
1186 (slot->sc->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
920 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
1187 sdhci_reset(slot, SDHCI_RESET_CMD);
1188 sdhci_reset(slot, SDHCI_RESET_DATA);
1189 }
1190
1191 /* We must be done -- bad idea to do this while locked? */
1192 slot->req = NULL;
1193 slot->curcmd = NULL;
1194 req->done(req);
1195}
1196
921 sdhci_reset(slot, SDHCI_RESET_CMD);
922 sdhci_reset(slot, SDHCI_RESET_DATA);
923 }
924
925 /* We must be done -- bad idea to do this while locked? */
926 slot->req = NULL;
927 slot->curcmd = NULL;
928 req->done(req);
929}
930
1197static int
1198sdhci_request(device_t brdev, device_t reqdev, struct mmc_request *req)
931int
932sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req)
1199{
1200 struct sdhci_slot *slot = device_get_ivars(reqdev);
1201
1202 SDHCI_LOCK(slot);
1203 if (slot->req != NULL) {
1204 SDHCI_UNLOCK(slot);
1205 return (EBUSY);
1206 }

--- 4 unchanged lines hidden (view full) ---

1211 (req->cmd->data)?req->cmd->data->flags:0);
1212 }
1213 slot->req = req;
1214 slot->flags = 0;
1215 sdhci_start(slot);
1216 SDHCI_UNLOCK(slot);
1217 if (dumping) {
1218 while (slot->req != NULL) {
933{
934 struct sdhci_slot *slot = device_get_ivars(reqdev);
935
936 SDHCI_LOCK(slot);
937 if (slot->req != NULL) {
938 SDHCI_UNLOCK(slot);
939 return (EBUSY);
940 }

--- 4 unchanged lines hidden (view full) ---

945 (req->cmd->data)?req->cmd->data->flags:0);
946 }
947 slot->req = req;
948 slot->flags = 0;
949 sdhci_start(slot);
950 SDHCI_UNLOCK(slot);
951 if (dumping) {
952 while (slot->req != NULL) {
1219 sdhci_intr(slot->sc);
953 sdhci_generic_intr(slot);
1220 DELAY(10);
1221 }
1222 }
1223 return (0);
1224}
1225
954 DELAY(10);
955 }
956 }
957 return (0);
958}
959
1226static int
1227sdhci_get_ro(device_t brdev, device_t reqdev)
960int
961sdhci_generic_get_ro(device_t brdev, device_t reqdev)
1228{
1229 struct sdhci_slot *slot = device_get_ivars(reqdev);
1230 uint32_t val;
1231
1232 SDHCI_LOCK(slot);
1233 val = RD4(slot, SDHCI_PRESENT_STATE);
1234 SDHCI_UNLOCK(slot);
1235 return (!(val & SDHCI_WRITE_PROTECT));
1236}
1237
962{
963 struct sdhci_slot *slot = device_get_ivars(reqdev);
964 uint32_t val;
965
966 SDHCI_LOCK(slot);
967 val = RD4(slot, SDHCI_PRESENT_STATE);
968 SDHCI_UNLOCK(slot);
969 return (!(val & SDHCI_WRITE_PROTECT));
970}
971
1238static int
1239sdhci_acquire_host(device_t brdev, device_t reqdev)
972int
973sdhci_generic_acquire_host(device_t brdev, device_t reqdev)
1240{
1241 struct sdhci_slot *slot = device_get_ivars(reqdev);
1242 int err = 0;
1243
1244 SDHCI_LOCK(slot);
1245 while (slot->bus_busy)
1246 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
1247 slot->bus_busy++;
1248 /* Activate led. */
1249 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1250 SDHCI_UNLOCK(slot);
1251 return (err);
1252}
1253
974{
975 struct sdhci_slot *slot = device_get_ivars(reqdev);
976 int err = 0;
977
978 SDHCI_LOCK(slot);
979 while (slot->bus_busy)
980 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
981 slot->bus_busy++;
982 /* Activate led. */
983 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
984 SDHCI_UNLOCK(slot);
985 return (err);
986}
987
1254static int
1255sdhci_release_host(device_t brdev, device_t reqdev)
988int
989sdhci_generic_release_host(device_t brdev, device_t reqdev)
1256{
1257 struct sdhci_slot *slot = device_get_ivars(reqdev);
1258
1259 SDHCI_LOCK(slot);
1260 /* Deactivate led. */
1261 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1262 slot->bus_busy--;
1263 SDHCI_UNLOCK(slot);

--- 113 unchanged lines hidden (view full) ---

1377 "there is no active command.\n", err);
1378 sdhci_dumpregs(slot);
1379 return;
1380 }
1381 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
1382 sdhci_reset(slot, SDHCI_RESET_CMD);
1383}
1384
990{
991 struct sdhci_slot *slot = device_get_ivars(reqdev);
992
993 SDHCI_LOCK(slot);
994 /* Deactivate led. */
995 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
996 slot->bus_busy--;
997 SDHCI_UNLOCK(slot);

--- 113 unchanged lines hidden (view full) ---

1111 "there is no active command.\n", err);
1112 sdhci_dumpregs(slot);
1113 return;
1114 }
1115 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
1116 sdhci_reset(slot, SDHCI_RESET_CMD);
1117}
1118
1385static void
1386sdhci_intr(void *arg)
1119void
1120sdhci_generic_intr(struct sdhci_slot *slot)
1387{
1121{
1388 struct sdhci_softc *sc = (struct sdhci_softc *)arg;
1389 int i;
1122 uint32_t intmask;
1123
1124 SDHCI_LOCK(slot);
1125 /* Read slot interrupt status. */
1126 intmask = RD4(slot, SDHCI_INT_STATUS);
1127 if (intmask == 0 || intmask == 0xffffffff) {
1128 SDHCI_UNLOCK(slot);
1129 return;
1130 }
1131 if (sdhci_debug > 2)
1132 slot_printf(slot, "Interrupt %#x\n", intmask);
1390
1133
1391 for (i = 0; i < sc->num_slots; i++) {
1392 struct sdhci_slot *slot = &sc->slots[i];
1393 uint32_t intmask;
1394
1395 SDHCI_LOCK(slot);
1396 /* Read slot interrupt status. */
1397 intmask = RD4(slot, SDHCI_INT_STATUS);
1398 if (intmask == 0 || intmask == 0xffffffff) {
1399 SDHCI_UNLOCK(slot);
1400 continue;
1401 }
1402 if (sdhci_debug > 2)
1403 slot_printf(slot, "Interrupt %#x\n", intmask);
1134 /* Handle card presence interrupts. */
1135 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1136 WR4(slot, SDHCI_INT_STATUS, intmask &
1137 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
1404
1138
1405 /* Handle card presence interrupts. */
1406 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1407 WR4(slot, SDHCI_INT_STATUS, intmask &
1408 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
1409
1410 if (intmask & SDHCI_INT_CARD_REMOVE) {
1411 if (bootverbose || sdhci_debug)
1412 slot_printf(slot, "Card removed\n");
1413 callout_stop(&slot->card_callout);
1414 taskqueue_enqueue(taskqueue_swi_giant,
1415 &slot->card_task);
1416 }
1417 if (intmask & SDHCI_INT_CARD_INSERT) {
1418 if (bootverbose || sdhci_debug)
1419 slot_printf(slot, "Card inserted\n");
1420 callout_reset(&slot->card_callout, hz / 2,
1421 sdhci_card_delay, slot);
1422 }
1423 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1139 if (intmask & SDHCI_INT_CARD_REMOVE) {
1140 if (bootverbose || sdhci_debug)
1141 slot_printf(slot, "Card removed\n");
1142 callout_stop(&slot->card_callout);
1143 taskqueue_enqueue(taskqueue_swi_giant,
1144 &slot->card_task);
1424 }
1145 }
1425 /* Handle command interrupts. */
1426 if (intmask & SDHCI_INT_CMD_MASK) {
1427 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
1428 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
1146 if (intmask & SDHCI_INT_CARD_INSERT) {
1147 if (bootverbose || sdhci_debug)
1148 slot_printf(slot, "Card inserted\n");
1149 callout_reset(&slot->card_callout, hz / 2,
1150 sdhci_card_delay, slot);
1429 }
1151 }
1430 /* Handle data interrupts. */
1431 if (intmask & SDHCI_INT_DATA_MASK) {
1432 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
1433 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
1434 }
1435 /* Handle AutoCMD12 error interrupt. */
1436 if (intmask & SDHCI_INT_ACMD12ERR) {
1437 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
1438 sdhci_acmd_irq(slot);
1439 }
1440 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1441 intmask &= ~SDHCI_INT_ACMD12ERR;
1442 intmask &= ~SDHCI_INT_ERROR;
1443 /* Handle bus power interrupt. */
1444 if (intmask & SDHCI_INT_BUS_POWER) {
1445 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
1446 slot_printf(slot,
1447 "Card is consuming too much power!\n");
1448 intmask &= ~SDHCI_INT_BUS_POWER;
1449 }
1450 /* The rest is unknown. */
1451 if (intmask) {
1452 WR4(slot, SDHCI_INT_STATUS, intmask);
1453 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
1454 intmask);
1455 sdhci_dumpregs(slot);
1456 }
1457
1458 SDHCI_UNLOCK(slot);
1152 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1459 }
1153 }
1154 /* Handle command interrupts. */
1155 if (intmask & SDHCI_INT_CMD_MASK) {
1156 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
1157 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
1158 }
1159 /* Handle data interrupts. */
1160 if (intmask & SDHCI_INT_DATA_MASK) {
1161 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
1162 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
1163 }
1164 /* Handle AutoCMD12 error interrupt. */
1165 if (intmask & SDHCI_INT_ACMD12ERR) {
1166 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
1167 sdhci_acmd_irq(slot);
1168 }
1169 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1170 intmask &= ~SDHCI_INT_ACMD12ERR;
1171 intmask &= ~SDHCI_INT_ERROR;
1172 /* Handle bus power interrupt. */
1173 if (intmask & SDHCI_INT_BUS_POWER) {
1174 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
1175 slot_printf(slot,
1176 "Card is consuming too much power!\n");
1177 intmask &= ~SDHCI_INT_BUS_POWER;
1178 }
1179 /* The rest is unknown. */
1180 if (intmask) {
1181 WR4(slot, SDHCI_INT_STATUS, intmask);
1182 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
1183 intmask);
1184 sdhci_dumpregs(slot);
1185 }
1186
1187 SDHCI_UNLOCK(slot);
1460}
1461
1188}
1189
1462static int
1463sdhci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1190int
1191sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1464{
1465 struct sdhci_slot *slot = device_get_ivars(child);
1466
1467 switch (which) {
1468 default:
1469 return (EINVAL);
1470 case MMCBR_IVAR_BUS_MODE:
1471 *result = slot->host.ios.bus_mode;

--- 36 unchanged lines hidden (view full) ---

1508 break;
1509 case MMCBR_IVAR_MAX_DATA:
1510 *result = 65535;
1511 break;
1512 }
1513 return (0);
1514}
1515
1192{
1193 struct sdhci_slot *slot = device_get_ivars(child);
1194
1195 switch (which) {
1196 default:
1197 return (EINVAL);
1198 case MMCBR_IVAR_BUS_MODE:
1199 *result = slot->host.ios.bus_mode;

--- 36 unchanged lines hidden (view full) ---

1236 break;
1237 case MMCBR_IVAR_MAX_DATA:
1238 *result = 65535;
1239 break;
1240 }
1241 return (0);
1242}
1243
1516static int
1517sdhci_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1244int
1245sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1518{
1519 struct sdhci_slot *slot = device_get_ivars(child);
1520
1521 switch (which) {
1522 default:
1523 return (EINVAL);
1524 case MMCBR_IVAR_BUS_MODE:
1525 slot->host.ios.bus_mode = value;

--- 38 unchanged lines hidden (view full) ---

1564 case MMCBR_IVAR_F_MIN:
1565 case MMCBR_IVAR_F_MAX:
1566 case MMCBR_IVAR_MAX_DATA:
1567 return (EINVAL);
1568 }
1569 return (0);
1570}
1571
1246{
1247 struct sdhci_slot *slot = device_get_ivars(child);
1248
1249 switch (which) {
1250 default:
1251 return (EINVAL);
1252 case MMCBR_IVAR_BUS_MODE:
1253 slot->host.ios.bus_mode = value;

--- 38 unchanged lines hidden (view full) ---

1292 case MMCBR_IVAR_F_MIN:
1293 case MMCBR_IVAR_F_MAX:
1294 case MMCBR_IVAR_MAX_DATA:
1295 return (EINVAL);
1296 }
1297 return (0);
1298}
1299
1572static device_method_t sdhci_methods[] = {
1573 /* device_if */
1574 DEVMETHOD(device_probe, sdhci_probe),
1575 DEVMETHOD(device_attach, sdhci_attach),
1576 DEVMETHOD(device_detach, sdhci_detach),
1577 DEVMETHOD(device_suspend, sdhci_suspend),
1578 DEVMETHOD(device_resume, sdhci_resume),
1579
1580 /* Bus interface */
1581 DEVMETHOD(bus_read_ivar, sdhci_read_ivar),
1582 DEVMETHOD(bus_write_ivar, sdhci_write_ivar),
1583
1584 /* mmcbr_if */
1585 DEVMETHOD(mmcbr_update_ios, sdhci_update_ios),
1586 DEVMETHOD(mmcbr_request, sdhci_request),
1587 DEVMETHOD(mmcbr_get_ro, sdhci_get_ro),
1588 DEVMETHOD(mmcbr_acquire_host, sdhci_acquire_host),
1589 DEVMETHOD(mmcbr_release_host, sdhci_release_host),
1590
1591 {0, 0},
1592};
1593
1594static driver_t sdhci_driver = {
1595 "sdhci",
1596 sdhci_methods,
1597 sizeof(struct sdhci_softc),
1598};
1599static devclass_t sdhci_devclass;
1600
1601
1602DRIVER_MODULE(sdhci, pci, sdhci_driver, sdhci_devclass, 0, 0);
1300MODULE_VERSION(sdhci, 1);