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if_re.c (231622) if_re.c (232145)
1/*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 17 unchanged lines hidden (view full) ---

26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 17 unchanged lines hidden (view full) ---

26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 231622 2012-02-14 00:54:40Z yongari $");
34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 232145 2012-02-25 04:54:51Z yongari $");
35
36/*
37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
41 * Wind River Systems
42 */

--- 1429 unchanged lines hidden (view full) ---

1472 case RL_HWREV_8169S:
1473 case RL_HWREV_8110S:
1474 sc->rl_flags |= RL_FLAG_MACRESET;
1475 break;
1476 default:
1477 break;
1478 }
1479
35
36/*
37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
41 * Wind River Systems
42 */

--- 1429 unchanged lines hidden (view full) ---

1472 case RL_HWREV_8169S:
1473 case RL_HWREV_8110S:
1474 sc->rl_flags |= RL_FLAG_MACRESET;
1475 break;
1476 default:
1477 break;
1478 }
1479
1480 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) {
1481 sc->rl_cfg0 = RL_8139_CFG0;
1482 sc->rl_cfg1 = RL_8139_CFG1;
1483 sc->rl_cfg2 = 0;
1484 sc->rl_cfg3 = RL_8139_CFG3;
1485 sc->rl_cfg4 = RL_8139_CFG4;
1486 sc->rl_cfg5 = RL_8139_CFG5;
1487 } else {
1488 sc->rl_cfg0 = RL_CFG0;
1489 sc->rl_cfg1 = RL_CFG1;
1490 sc->rl_cfg2 = RL_CFG2;
1491 sc->rl_cfg3 = RL_CFG3;
1492 sc->rl_cfg4 = RL_CFG4;
1493 sc->rl_cfg5 = RL_CFG5;
1494 }
1495
1480 /* Reset the adapter. */
1481 RL_LOCK(sc);
1482 re_reset(sc);
1483 RL_UNLOCK(sc);
1484
1485 /* Enable PME. */
1486 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1496 /* Reset the adapter. */
1497 RL_LOCK(sc);
1498 re_reset(sc);
1499 RL_UNLOCK(sc);
1500
1501 /* Enable PME. */
1502 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1487 cfg = CSR_READ_1(sc, RL_CFG1);
1503 cfg = CSR_READ_1(sc, sc->rl_cfg1);
1488 cfg |= RL_CFG1_PME;
1504 cfg |= RL_CFG1_PME;
1489 CSR_WRITE_1(sc, RL_CFG1, cfg);
1490 cfg = CSR_READ_1(sc, RL_CFG5);
1505 CSR_WRITE_1(sc, sc->rl_cfg1, cfg);
1506 cfg = CSR_READ_1(sc, sc->rl_cfg5);
1491 cfg &= RL_CFG5_PME_STS;
1507 cfg &= RL_CFG5_PME_STS;
1492 CSR_WRITE_1(sc, RL_CFG5, cfg);
1508 CSR_WRITE_1(sc, sc->rl_cfg5, cfg);
1493 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1494
1495 if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
1496 /*
1497 * XXX Should have a better way to extract station
1498 * address from EEPROM.
1499 */
1500 for (i = 0; i < ETHER_ADDR_LEN; i++)

--- 1445 unchanged lines hidden (view full) ---

2946
2947 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) {
2948 pci_set_max_read_req(sc->rl_dev, 4096);
2949 return;
2950 }
2951
2952 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2953 if (jumbo != 0) {
1509 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1510
1511 if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
1512 /*
1513 * XXX Should have a better way to extract station
1514 * address from EEPROM.
1515 */
1516 for (i = 0; i < ETHER_ADDR_LEN; i++)

--- 1445 unchanged lines hidden (view full) ---

2962
2963 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) {
2964 pci_set_max_read_req(sc->rl_dev, 4096);
2965 return;
2966 }
2967
2968 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2969 if (jumbo != 0) {
2954 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) |
2970 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) |
2955 RL_CFG3_JUMBO_EN0);
2956 switch (sc->rl_hwrev->rl_rev) {
2957 case RL_HWREV_8168DP:
2958 break;
2959 case RL_HWREV_8168E:
2971 RL_CFG3_JUMBO_EN0);
2972 switch (sc->rl_hwrev->rl_rev) {
2973 case RL_HWREV_8168DP:
2974 break;
2975 case RL_HWREV_8168E:
2960 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) |
2961 0x01);
2976 CSR_WRITE_1(sc, sc->rl_cfg4,
2977 CSR_READ_1(sc, sc->rl_cfg4) | 0x01);
2962 break;
2963 default:
2978 break;
2979 default:
2964 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) |
2965 RL_CFG4_JUMBO_EN1);
2980 CSR_WRITE_1(sc, sc->rl_cfg4,
2981 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1);
2966 }
2967 } else {
2982 }
2983 } else {
2968 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) &
2984 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) &
2969 ~RL_CFG3_JUMBO_EN0);
2970 switch (sc->rl_hwrev->rl_rev) {
2971 case RL_HWREV_8168DP:
2972 break;
2973 case RL_HWREV_8168E:
2985 ~RL_CFG3_JUMBO_EN0);
2986 switch (sc->rl_hwrev->rl_rev) {
2987 case RL_HWREV_8168DP:
2988 break;
2989 case RL_HWREV_8168E:
2974 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) &
2975 ~0x01);
2990 CSR_WRITE_1(sc, sc->rl_cfg4,
2991 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01);
2976 break;
2977 default:
2992 break;
2993 default:
2978 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) &
2979 ~RL_CFG4_JUMBO_EN1);
2994 CSR_WRITE_1(sc, sc->rl_cfg4,
2995 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1);
2980 }
2981 }
2982 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2983
2984 switch (sc->rl_hwrev->rl_rev) {
2985 case RL_HWREV_8168DP:
2986 pci_set_max_read_req(sc->rl_dev, 4096);
2987 break;

--- 96 unchanged lines hidden (view full) ---

3084 /* XXX magic. */
3085 cfg |= 0x0001;
3086 } else
3087 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
3088 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
3089 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC ||
3090 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) {
3091 reg = 0x000fff00;
2996 }
2997 }
2998 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2999
3000 switch (sc->rl_hwrev->rl_rev) {
3001 case RL_HWREV_8168DP:
3002 pci_set_max_read_req(sc->rl_dev, 4096);
3003 break;

--- 96 unchanged lines hidden (view full) ---

3100 /* XXX magic. */
3101 cfg |= 0x0001;
3102 } else
3103 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
3104 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
3105 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC ||
3106 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) {
3107 reg = 0x000fff00;
3092 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0)
3108 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0)
3093 reg |= 0x000000ff;
3094 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE)
3095 reg |= 0x00f00000;
3096 CSR_WRITE_4(sc, 0x7c, reg);
3097 /* Disable interrupt mitigation. */
3098 CSR_WRITE_2(sc, 0xe2, 0);
3099 }
3100 /*

--- 148 unchanged lines hidden (view full) ---

3249 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN);
3250 } else
3251 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
3252 }
3253
3254 if (sc->rl_testmode)
3255 return;
3256
3109 reg |= 0x000000ff;
3110 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE)
3111 reg |= 0x00f00000;
3112 CSR_WRITE_4(sc, 0x7c, reg);
3113 /* Disable interrupt mitigation. */
3114 CSR_WRITE_2(sc, 0xe2, 0);
3115 }
3116 /*

--- 148 unchanged lines hidden (view full) ---

3265 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN);
3266 } else
3267 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
3268 }
3269
3270 if (sc->rl_testmode)
3271 return;
3272
3257 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD);
3273 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |
3274 RL_CFG1_DRVLOAD);
3258
3259 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3260 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3261
3262 sc->rl_flags &= ~RL_FLAG_LINK;
3263 mii_mediachg(mii);
3264
3265 sc->rl_watchdog_timer = 0;

--- 516 unchanged lines hidden (view full) ---

3782 re_set_linkspeed(sc);
3783 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
3784 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);
3785 }
3786 /* Enable config register write. */
3787 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3788
3789 /* Enable PME. */
3275
3276 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3277 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3278
3279 sc->rl_flags &= ~RL_FLAG_LINK;
3280 mii_mediachg(mii);
3281
3282 sc->rl_watchdog_timer = 0;

--- 516 unchanged lines hidden (view full) ---

3799 re_set_linkspeed(sc);
3800 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
3801 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);
3802 }
3803 /* Enable config register write. */
3804 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3805
3806 /* Enable PME. */
3790 v = CSR_READ_1(sc, RL_CFG1);
3807 v = CSR_READ_1(sc, sc->rl_cfg1);
3791 v &= ~RL_CFG1_PME;
3792 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3793 v |= RL_CFG1_PME;
3808 v &= ~RL_CFG1_PME;
3809 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3810 v |= RL_CFG1_PME;
3794 CSR_WRITE_1(sc, RL_CFG1, v);
3811 CSR_WRITE_1(sc, sc->rl_cfg1, v);
3795
3812
3796 v = CSR_READ_1(sc, RL_CFG3);
3813 v = CSR_READ_1(sc, sc->rl_cfg3);
3797 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3798 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3799 v |= RL_CFG3_WOL_MAGIC;
3814 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3815 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3816 v |= RL_CFG3_WOL_MAGIC;
3800 CSR_WRITE_1(sc, RL_CFG3, v);
3817 CSR_WRITE_1(sc, sc->rl_cfg3, v);
3801
3818
3802 v = CSR_READ_1(sc, RL_CFG5);
3819 v = CSR_READ_1(sc, sc->rl_cfg5);
3803 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST |
3804 RL_CFG5_WOL_LANWAKE);
3805 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
3806 v |= RL_CFG5_WOL_UCAST;
3807 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
3808 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
3809 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3810 v |= RL_CFG5_WOL_LANWAKE;
3820 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST |
3821 RL_CFG5_WOL_LANWAKE);
3822 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
3823 v |= RL_CFG5_WOL_UCAST;
3824 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
3825 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
3826 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3827 v |= RL_CFG5_WOL_LANWAKE;
3811 CSR_WRITE_1(sc, RL_CFG5, v);
3828 CSR_WRITE_1(sc, sc->rl_cfg5, v);
3812
3813 /* Config register write done. */
3814 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3815
3816 if ((ifp->if_capenable & IFCAP_WOL) == 0 &&
3817 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
3818 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);
3819 /*

--- 19 unchanged lines hidden (view full) ---

3839 RL_LOCK_ASSERT(sc);
3840
3841 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3842 return;
3843
3844 /* Enable config register write. */
3845 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3846
3829
3830 /* Config register write done. */
3831 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3832
3833 if ((ifp->if_capenable & IFCAP_WOL) == 0 &&
3834 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
3835 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);
3836 /*

--- 19 unchanged lines hidden (view full) ---

3856 RL_LOCK_ASSERT(sc);
3857
3858 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3859 return;
3860
3861 /* Enable config register write. */
3862 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3863
3847 v = CSR_READ_1(sc, RL_CFG3);
3864 v = CSR_READ_1(sc, sc->rl_cfg3);
3848 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3865 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3849 CSR_WRITE_1(sc, RL_CFG3, v);
3866 CSR_WRITE_1(sc, sc->rl_cfg3, v);
3850
3851 /* Config register write done. */
3852 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3853
3867
3868 /* Config register write done. */
3869 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3870
3854 v = CSR_READ_1(sc, RL_CFG5);
3871 v = CSR_READ_1(sc, sc->rl_cfg5);
3855 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
3856 v &= ~RL_CFG5_WOL_LANWAKE;
3872 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
3873 v &= ~RL_CFG5_WOL_LANWAKE;
3857 CSR_WRITE_1(sc, RL_CFG5, v);
3874 CSR_WRITE_1(sc, sc->rl_cfg5, v);
3858}
3859
3860static void
3861re_add_sysctls(struct rl_softc *sc)
3862{
3863 struct sysctl_ctx_list *ctx;
3864 struct sysctl_oid_list *children;
3865 int error;

--- 130 unchanged lines hidden --- 		3875}
3876
3877static void
3878re_add_sysctls(struct rl_softc *sc)
3879{
3880 struct sysctl_ctx_list *ctx;
3881 struct sysctl_oid_list *children;
3882 int error;

--- 130 unchanged lines hidden ---