| if_re.c (187482) | if_re.c (187483) |
|---|---|
| 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> |
| 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 187482 2009-01-20 20:04:09Z jkim $"); | 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 187483 2009-01-20 20:22:28Z jkim $"); |
| 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ --- 151 unchanged lines hidden (view full) --- 194 { RL_HWREV_8130, RL_8139, "8130" }, 195 { RL_HWREV_8139C, RL_8139, "C" }, 196 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 197 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 198 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 199 { RL_HWREV_8169, RL_8169, "8169"}, 200 { RL_HWREV_8169S, RL_8169, "8169S"}, 201 { RL_HWREV_8110S, RL_8169, "8110S"}, | 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ --- 151 unchanged lines hidden (view full) --- 194 { RL_HWREV_8130, RL_8139, "8130" }, 195 { RL_HWREV_8139C, RL_8139, "C" }, 196 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 197 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 198 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 199 { RL_HWREV_8169, RL_8169, "8169"}, 200 { RL_HWREV_8169S, RL_8169, "8169S"}, 201 { RL_HWREV_8110S, RL_8169, "8110S"}, |
| 202 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 203 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 204 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL"}, | 202 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB"}, 203 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC"}, 204 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL"}, 205 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC"}, |
| 205 { RL_HWREV_8100, RL_8139, "8100"}, 206 { RL_HWREV_8101, RL_8139, "8101"}, 207 { RL_HWREV_8100E, RL_8169, "8100E"}, 208 { RL_HWREV_8101E, RL_8169, "8101E"}, 209 { RL_HWREV_8102E, RL_8169, "8102E"}, 210 { RL_HWREV_8102EL, RL_8169, "8102EL"}, 211 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 212 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, --- 470 unchanged lines hidden (view full) --- 683 for (i = 0; i < RL_TIMEOUT; i++) { 684 DELAY(10); 685 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 686 break; 687 } 688 if (i == RL_TIMEOUT) 689 device_printf(sc->rl_dev, "reset never completed!\n"); 690 | 206 { RL_HWREV_8100, RL_8139, "8100"}, 207 { RL_HWREV_8101, RL_8139, "8101"}, 208 { RL_HWREV_8100E, RL_8169, "8100E"}, 209 { RL_HWREV_8101E, RL_8169, "8101E"}, 210 { RL_HWREV_8102E, RL_8169, "8102E"}, 211 { RL_HWREV_8102EL, RL_8169, "8102EL"}, 212 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 213 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, --- 470 unchanged lines hidden (view full) --- 684 for (i = 0; i < RL_TIMEOUT; i++) { 685 DELAY(10); 686 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 687 break; 688 } 689 if (i == RL_TIMEOUT) 690 device_printf(sc->rl_dev, "reset never completed!\n"); 691 |
| 691 if ((sc->rl_flags & RL_FLAG_PHY8169) != 0) | 692 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) |
| 692 CSR_WRITE_1(sc, 0x82, 1); | 693 CSR_WRITE_1(sc, 0x82, 1); |
| 693 if ((sc->rl_flags & RL_FLAG_PHY8110S) != 0) { 694 CSR_WRITE_1(sc, 0x82, 1); 695 re_gmii_writereg(sc->rl_dev, 1, 0x0B, 0); 696 } | 694 if (sc->rl_hwrev == RL_HWREV_8169S) 695 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); |
| 697} 698 699#ifdef RE_DIAG 700 701/* 702 * The following routine is designed to test for a defect on some 703 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 704 * lines connected to the bus, however for a 32-bit only card, they --- 499 unchanged lines hidden (view full) --- 1204 1205 /* Reset the adapter. */ 1206 RL_LOCK(sc); 1207 re_reset(sc); 1208 RL_UNLOCK(sc); 1209 1210 hw_rev = re_hwrevs; 1211 hwrev = CSR_READ_4(sc, RL_TXCFG); | 696} 697 698#ifdef RE_DIAG 699 700/* 701 * The following routine is designed to test for a defect on some 702 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 703 * lines connected to the bus, however for a 32-bit only card, they --- 499 unchanged lines hidden (view full) --- 1203 1204 /* Reset the adapter. */ 1205 RL_LOCK(sc); 1206 re_reset(sc); 1207 RL_UNLOCK(sc); 1208 1209 hw_rev = re_hwrevs; 1210 hwrev = CSR_READ_4(sc, RL_TXCFG); |
| 1212 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); | 1211 switch (hwrev & 0x70000000) { 1212 case 0x00000000: 1213 case 0x10000000: 1214 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1215 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1216 break; 1217 default: 1218 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1219 hwrev &= RL_TXCFG_HWREV; 1220 break; 1221 } |
| 1213 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); | 1222 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); |
| 1214 hwrev &= RL_TXCFG_HWREV; | |
| 1215 while (hw_rev->rl_desc != NULL) { 1216 if (hw_rev->rl_rev == hwrev) { 1217 sc->rl_type = hw_rev->rl_type; | 1223 while (hw_rev->rl_desc != NULL) { 1224 if (hw_rev->rl_rev == hwrev) { 1225 sc->rl_type = hw_rev->rl_type; |
| 1226 sc->rl_hwrev = hw_rev->rl_rev; |
|
| 1218 break; 1219 } 1220 hw_rev++; 1221 } 1222 if (hw_rev->rl_desc == NULL) { 1223 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1224 error = ENXIO; 1225 goto fail; 1226 } 1227 1228 switch (hw_rev->rl_rev) { 1229 case RL_HWREV_8139CPLUS: 1230 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_FASTETHER; 1231 break; | 1227 break; 1228 } 1229 hw_rev++; 1230 } 1231 if (hw_rev->rl_desc == NULL) { 1232 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1233 error = ENXIO; 1234 goto fail; 1235 } 1236 1237 switch (hw_rev->rl_rev) { 1238 case RL_HWREV_8139CPLUS: 1239 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_FASTETHER; 1240 break; |
| 1232 case RL_HWREV_8110S: 1233 sc->rl_flags |= RL_FLAG_PHY8110S; 1234 break; | |
| 1235 case RL_HWREV_8100E: 1236 case RL_HWREV_8101E: 1237 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1238 RL_FLAG_FASTETHER; 1239 break; 1240 case RL_HWREV_8102E: 1241 case RL_HWREV_8102EL: 1242 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | --- 25 unchanged lines hidden (view full) --- 1268 * controllers need to disable checksum offload. So 1269 * disable jumbo frame until I have better idea what 1270 * it really requires to make it support. 1271 * RTL8168C/CP : supports up to 6KB jumbo frame. 1272 * RTL8111C/CP : supports up to 9KB jumbo frame. 1273 */ 1274 sc->rl_flags |= RL_FLAG_NOJUMBO; 1275 break; | 1241 case RL_HWREV_8100E: 1242 case RL_HWREV_8101E: 1243 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1244 RL_FLAG_FASTETHER; 1245 break; 1246 case RL_HWREV_8102E: 1247 case RL_HWREV_8102EL: 1248 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | --- 25 unchanged lines hidden (view full) --- 1274 * controllers need to disable checksum offload. So 1275 * disable jumbo frame until I have better idea what 1276 * it really requires to make it support. 1277 * RTL8168C/CP : supports up to 6KB jumbo frame. 1278 * RTL8111C/CP : supports up to 9KB jumbo frame. 1279 */ 1280 sc->rl_flags |= RL_FLAG_NOJUMBO; 1281 break; |
| 1282 case RL_HWREV_8169_8110SB: 1283 case RL_HWREV_8169_8110SBL: 1284 case RL_HWREV_8169_8110SC: 1285 case RL_HWREV_8169_8110SCE: 1286 sc->rl_flags |= RL_FLAG_PHYWAKE; 1287 /* FALLTHROUGH */ |
|
| 1276 case RL_HWREV_8169: 1277 case RL_HWREV_8169S: | 1288 case RL_HWREV_8169: 1289 case RL_HWREV_8169S: |
| 1278 sc->rl_flags |= RL_FLAG_PHY8169; | 1290 case RL_HWREV_8110S: 1291 sc->rl_flags |= RL_FLAG_MACRESET; |
| 1279 break; | 1292 break; |
| 1280 case RL_HWREV_8169_8110SB: 1281 case RL_HWREV_8169_8110SC: 1282 case RL_HWREV_8169_8110SBL: 1283 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHY8169; 1284 break; | |
| 1285 default: 1286 break; 1287 } 1288 1289 /* Enable PME. */ 1290 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1291 cfg = CSR_READ_1(sc, RL_CFG1); 1292 cfg |= RL_CFG1_PME; --- 1186 unchanged lines hidden (view full) --- 2479 RL_UNLOCK(sc); 2480} 2481 2482static void 2483re_init_locked(struct rl_softc *sc) 2484{ 2485 struct ifnet *ifp = sc->rl_ifp; 2486 struct mii_data *mii; | 1293 default: 1294 break; 1295 } 1296 1297 /* Enable PME. */ 1298 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1299 cfg = CSR_READ_1(sc, RL_CFG1); 1300 cfg |= RL_CFG1_PME; --- 1186 unchanged lines hidden (view full) --- 2487 RL_UNLOCK(sc); 2488} 2489 2490static void 2491re_init_locked(struct rl_softc *sc) 2492{ 2493 struct ifnet *ifp = sc->rl_ifp; 2494 struct mii_data *mii; |
| 2495 uint32_t reg; |
|
| 2487 uint16_t cfg; 2488 union { 2489 uint32_t align_dummy; 2490 u_char eaddr[ETHER_ADDR_LEN]; 2491 } eaddr; 2492 2493 RL_LOCK_ASSERT(sc); 2494 --- 19 unchanged lines hidden (view full) --- 2514 cfg |= RL_CPLUSCMD_VLANSTRIP; 2515 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2516 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2517 /* XXX magic. */ 2518 cfg |= 0x0001; 2519 } else 2520 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2521 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); | 2496 uint16_t cfg; 2497 union { 2498 uint32_t align_dummy; 2499 u_char eaddr[ETHER_ADDR_LEN]; 2500 } eaddr; 2501 2502 RL_LOCK_ASSERT(sc); 2503 --- 19 unchanged lines hidden (view full) --- 2523 cfg |= RL_CPLUSCMD_VLANSTRIP; 2524 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2525 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2526 /* XXX magic. */ 2527 cfg |= 0x0001; 2528 } else 2529 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2530 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); |
| 2531 if (sc->rl_hwrev == RL_HWREV_8169_8110SC || 2532 sc->rl_hwrev == RL_HWREV_8169_8110SCE) { 2533 reg = 0x000fff00; 2534 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 2535 reg |= 0x000000ff; 2536 if (sc->rl_hwrev == RL_HWREV_8169_8110SCE) 2537 reg |= 0x00f00000; 2538 CSR_WRITE_4(sc, 0x7c, reg); 2539 /* Disable interrupt mitigation. */ 2540 CSR_WRITE_2(sc, 0xe2, 0); 2541 } |
|
| 2522 /* 2523 * Disable TSO if interface MTU size is greater than MSS 2524 * allowed in controller. 2525 */ 2526 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2527 ifp->if_capenable &= ~IFCAP_TSO4; 2528 ifp->if_hwassist &= ~CSUM_TSO; 2529 } --- 561 unchanged lines hidden --- | 2542 /* 2543 * Disable TSO if interface MTU size is greater than MSS 2544 * allowed in controller. 2545 */ 2546 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2547 ifp->if_capenable &= ~IFCAP_TSO4; 2548 ifp->if_hwassist &= ~CSUM_TSO; 2549 } --- 561 unchanged lines hidden --- |