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if_re.c (160008) if_re.c (160843)
1/*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 17 unchanged lines hidden (view full) ---

26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 17 unchanged lines hidden (view full) ---

26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 160008 2006-06-28 16:04:54Z wpaul $");
34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 160843 2006-07-30 23:25:21Z wpaul $");
35
36/*
37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
41 * Wind River Systems
42 */

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167 */
168static struct rl_type re_devs[] = {
169 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S,
170 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
171 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS,
172 "RealTek 8139C+ 10/100BaseTX" },
173 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E,
174 "RealTek 8101E PCIe 10/100baseTX" },
35
36/*
37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
41 * Wind River Systems
42 */

--- 124 unchanged lines hidden (view full) ---

167 */
168static struct rl_type re_devs[] = {
169 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S,
170 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
171 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS,
172 "RealTek 8139C+ 10/100BaseTX" },
173 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E,
174 "RealTek 8101E PCIe 10/100baseTX" },
175 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168,
176 "RealTek 8168B PCIe Gigabit Ethernet" },
177 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8111,
178 "RealTek 8111B PCIe Gigabit Ethernet" },
175 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN1,
176 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
177 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN2,
178 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
179 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169,
180 "RealTek 8169 Gigabit Ethernet" },
181 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S,
182 "RealTek 8169S Single-chip Gigabit Ethernet" },
183 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB,
184 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" },
179 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169,
180 "RealTek 8169 Gigabit Ethernet" },
181 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S,
182 "RealTek 8169S Single-chip Gigabit Ethernet" },
183 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB,
184 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" },
185 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SC,
185 { RT_VENDORID, RT_DEVICEID_8169SC, RL_HWREV_8169_8110SC,
186 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
187 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S,
188 "RealTek 8110S Single-chip Gigabit Ethernet" },
189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S,
190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S,
192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
193 { 0, 0, 0, NULL }
194};
195
196static struct rl_hwrev re_hwrevs[] = {
197 { RL_HWREV_8139, RL_8139, "" },
198 { RL_HWREV_8139A, RL_8139, "A" },
199 { RL_HWREV_8139AG, RL_8139, "A-G" },
200 { RL_HWREV_8139B, RL_8139, "B" },
201 { RL_HWREV_8130, RL_8139, "8130" },
202 { RL_HWREV_8139C, RL_8139, "C" },
203 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" },
204 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
186 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
187 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S,
188 "RealTek 8110S Single-chip Gigabit Ethernet" },
189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S,
190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S,
192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
193 { 0, 0, 0, NULL }
194};
195
196static struct rl_hwrev re_hwrevs[] = {
197 { RL_HWREV_8139, RL_8139, "" },
198 { RL_HWREV_8139A, RL_8139, "A" },
199 { RL_HWREV_8139AG, RL_8139, "A-G" },
200 { RL_HWREV_8139B, RL_8139, "B" },
201 { RL_HWREV_8130, RL_8139, "8130" },
202 { RL_HWREV_8139C, RL_8139, "C" },
203 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" },
204 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
205 { RL_HWREV_8168, RL_8169, "8168"},
205 { RL_HWREV_8168_SPIN1, RL_8169, "8168"},
206 { RL_HWREV_8169, RL_8169, "8169"},
207 { RL_HWREV_8169S, RL_8169, "8169S"},
208 { RL_HWREV_8110S, RL_8169, "8110S"},
209 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"},
210 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"},
211 { RL_HWREV_8100, RL_8139, "8100"},
212 { RL_HWREV_8101, RL_8139, "8101"},
213 { RL_HWREV_8100E, RL_8169, "8100E"},
214 { RL_HWREV_8101E, RL_8169, "8101E"},
206 { RL_HWREV_8169, RL_8169, "8169"},
207 { RL_HWREV_8169S, RL_8169, "8169S"},
208 { RL_HWREV_8110S, RL_8169, "8110S"},
209 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"},
210 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"},
211 { RL_HWREV_8100, RL_8139, "8100"},
212 { RL_HWREV_8101, RL_8139, "8101"},
213 { RL_HWREV_8100E, RL_8169, "8100E"},
214 { RL_HWREV_8101E, RL_8169, "8101E"},
215 { RL_HWREV_8111, RL_8169, "8111"},
215 { RL_HWREV_8168_SPIN2, RL_8169, "8168"},
216 { 0, 0, NULL }
217};
218
219static int re_probe (device_t);
220static int re_attach (device_t);
221static int re_detach (device_t);
222
223static int re_encap (struct rl_softc *, struct mbuf **, int *);

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930 bus_dma_segment_t *segs;
931 int nseg;
932 bus_size_t mapsize;
933 int error;
934{
935 struct rl_dmaload_arg *ctx;
936 struct rl_desc *d = NULL;
937 int i = 0, idx;
216 { 0, 0, NULL }
217};
218
219static int re_probe (device_t);
220static int re_attach (device_t);
221static int re_detach (device_t);
222
223static int re_encap (struct rl_softc *, struct mbuf **, int *);

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930 bus_dma_segment_t *segs;
931 int nseg;
932 bus_size_t mapsize;
933 int error;
934{
935 struct rl_dmaload_arg *ctx;
936 struct rl_desc *d = NULL;
937 int i = 0, idx;
938 u_int32_t cmdstat;
939 int totlen = 0;
938
939 if (error)
940 return;
941
942 ctx = arg;
943
944 /* Signal error to caller if there's too many segments */
945 if (nseg > ctx->rl_maxsegs) {

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955 * We also keep track of the end of the ring and set the
956 * end-of-ring bits as needed, and we set the ownership bits
957 * in all except the very first descriptor. (The caller will
958 * set this descriptor later when it start transmission or
959 * reception.)
960 */
961 idx = ctx->rl_idx;
962 for (;;) {
940
941 if (error)
942 return;
943
944 ctx = arg;
945
946 /* Signal error to caller if there's too many segments */
947 if (nseg > ctx->rl_maxsegs) {

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957 * We also keep track of the end of the ring and set the
958 * end-of-ring bits as needed, and we set the ownership bits
959 * in all except the very first descriptor. (The caller will
960 * set this descriptor later when it start transmission or
961 * reception.)
962 */
963 idx = ctx->rl_idx;
964 for (;;) {
963 u_int32_t cmdstat;
964 d = &ctx->rl_ring[idx];
965 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) {
966 ctx->rl_maxsegs = 0;
967 return;
968 }
969 cmdstat = segs[i].ds_len;
965 d = &ctx->rl_ring[idx];
966 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) {
967 ctx->rl_maxsegs = 0;
968 return;
969 }
970 cmdstat = segs[i].ds_len;
971 totlen += segs[i].ds_len;
970 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
971 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
972 if (i == 0)
973 cmdstat |= RL_TDESC_CMD_SOF;
974 else
975 cmdstat |= RL_TDESC_CMD_OWN;
976 if (idx == (RL_RX_DESC_CNT - 1))
977 cmdstat |= RL_TDESC_CMD_EOR;
978 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags);
979 i++;
980 if (i == nseg)
981 break;
982 RL_DESC_INC(idx);
983 }
984
972 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
973 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
974 if (i == 0)
975 cmdstat |= RL_TDESC_CMD_SOF;
976 else
977 cmdstat |= RL_TDESC_CMD_OWN;
978 if (idx == (RL_RX_DESC_CNT - 1))
979 cmdstat |= RL_TDESC_CMD_EOR;
980 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags);
981 i++;
982 if (i == nseg)
983 break;
984 RL_DESC_INC(idx);
985 }
986
987 /*
988 * With some of the RealTek chips, using the checksum offload
989 * support in conjunction with the autopadding feature results
990 * in the transmission of corrupt frames. For example, if we
991 * need to send a really small IP fragment that's less than 60
992 * bytes in size, and IP header checksumming is enabled, the
993 * resulting ethernet frame that appears on the wire will
994 * have garbled payload. To work around this, if TX checksum
995 * offload is enabled, we always manually pad short frames out
996 * to the minimum ethernet frame size. We do this by lying
997 * about the size of the final fragment in the DMA map.
998 */
999
1000 if (ctx->rl_flags && totlen < (ETHER_MIN_LEN - ETHER_CRC_LEN)) {
1001 i = cmdstat & 0xFFFF;
1002 i += ETHER_MIN_LEN - ETHER_CRC_LEN - totlen;
1003 cmdstat = (cmdstat & 0xFFFF) | i;
1004 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags);
1005 }
1006
985 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
986 ctx->rl_maxsegs = nseg;
987 ctx->rl_idx = idx;
988}
989
990/*
991 * Map a single buffer address.
992 */

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1126 u_int16_t re_did = 0;
1127 int error = 0, rid, i;
1128
1129 sc = device_get_softc(dev);
1130 sc->rl_dev = dev;
1131
1132 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1133 MTX_DEF);
1007 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
1008 ctx->rl_maxsegs = nseg;
1009 ctx->rl_idx = idx;
1010}
1011
1012/*
1013 * Map a single buffer address.
1014 */

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1148 u_int16_t re_did = 0;
1149 int error = 0, rid, i;
1150
1151 sc = device_get_softc(dev);
1152 sc->rl_dev = dev;
1153
1154 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1155 MTX_DEF);
1134 mtx_init(&sc->rl_intlock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1135 MTX_SPIN);
1136 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1137
1138 /*
1139 * Map control/status registers.
1140 */
1141 pci_enable_busmaster(dev);
1142
1143 rid = RL_RID;

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1244 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1245 ifp->if_mtu = ETHERMTU;
1246 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1247 ifp->if_ioctl = re_ioctl;
1248 ifp->if_capabilities = IFCAP_VLAN_MTU;
1249 ifp->if_start = re_start;
1250 ifp->if_hwassist = RE_CSUM_FEATURES;
1251 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1156 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1157
1158 /*
1159 * Map control/status registers.
1160 */
1161 pci_enable_busmaster(dev);
1162
1163 rid = RL_RID;

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1264 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1265 ifp->if_mtu = ETHERMTU;
1266 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1267 ifp->if_ioctl = re_ioctl;
1268 ifp->if_capabilities = IFCAP_VLAN_MTU;
1269 ifp->if_start = re_start;
1270 ifp->if_hwassist = RE_CSUM_FEATURES;
1271 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1252 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1272 ifp->if_capenable = ifp->if_capabilities;
1253#ifdef DEVICE_POLLING
1254 ifp->if_capabilities |= IFCAP_POLLING;
1255#endif
1256 ifp->if_watchdog = re_watchdog;
1257 ifp->if_init = re_init;
1258 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1259 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1260 IFQ_SET_READY(&ifp->if_snd);

--- 150 unchanged lines hidden (view full) ---

1411 sc->rl_ldata.rl_smap);
1412 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1413 }
1414
1415 if (sc->rl_parent_tag)
1416 bus_dma_tag_destroy(sc->rl_parent_tag);
1417
1418 mtx_destroy(&sc->rl_mtx);
1273#ifdef DEVICE_POLLING
1274 ifp->if_capabilities |= IFCAP_POLLING;
1275#endif
1276 ifp->if_watchdog = re_watchdog;
1277 ifp->if_init = re_init;
1278 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1279 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1280 IFQ_SET_READY(&ifp->if_snd);

--- 150 unchanged lines hidden (view full) ---

1431 sc->rl_ldata.rl_smap);
1432 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1433 }
1434
1435 if (sc->rl_parent_tag)
1436 bus_dma_tag_destroy(sc->rl_parent_tag);
1437
1438 mtx_destroy(&sc->rl_mtx);
1419 mtx_destroy(&sc->rl_intlock);
1420
1421 return (0);
1422}
1423
1424static int
1425re_newbuf(sc, idx, m)
1426 struct rl_softc *sc;
1427 int idx;

--- 462 unchanged lines hidden (view full) ---

1890{
1891 struct rl_softc *sc;
1892 struct ifnet *ifp;
1893 uint16_t status;
1894
1895 sc = arg;
1896 ifp = sc->rl_ifp;
1897
1439
1440 return (0);
1441}
1442
1443static int
1444re_newbuf(sc, idx, m)
1445 struct rl_softc *sc;
1446 int idx;

--- 462 unchanged lines hidden (view full) ---

1909{
1910 struct rl_softc *sc;
1911 struct ifnet *ifp;
1912 uint16_t status;
1913
1914 sc = arg;
1915 ifp = sc->rl_ifp;
1916
1898 mtx_lock_spin(&sc->rl_intlock);
1899 status = CSR_READ_2(sc, RL_ISR);
1917 status = CSR_READ_2(sc, RL_ISR);
1900 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) {
1901 mtx_unlock_spin(&sc->rl_intlock);
1918 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0)
1902 return;
1919 return;
1903 }
1904 CSR_WRITE_2(sc, RL_IMR, 0);
1920 CSR_WRITE_2(sc, RL_IMR, 0);
1905 mtx_unlock_spin(&sc->rl_intlock);
1906
1907 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
1908
1909 return;
1910}
1911
1912static void
1913re_int_task(arg, npending)

--- 51 unchanged lines hidden (view full) ---

1965
1966 RL_UNLOCK(sc);
1967
1968 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
1969 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
1970 return;
1971 }
1972
1921
1922 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
1923
1924 return;
1925}
1926
1927static void
1928re_int_task(arg, npending)

--- 51 unchanged lines hidden (view full) ---

1980
1981 RL_UNLOCK(sc);
1982
1983 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
1984 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
1985 return;
1986 }
1987
1973 mtx_lock_spin(&sc->rl_intlock);
1974 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
1988 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
1975 mtx_unlock_spin(&sc->rl_intlock);
1976
1977 return;
1978}
1979
1980static int
1981re_encap(sc, m_head, idx)
1982 struct rl_softc *sc;
1983 struct mbuf **m_head;

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2300 if (ifp->if_capenable & IFCAP_POLLING)
2301 CSR_WRITE_2(sc, RL_IMR, 0);
2302 else /* otherwise ... */
2303#endif
2304
2305 /*
2306 * Enable interrupts.
2307 */
1989
1990 return;
1991}
1992
1993static int
1994re_encap(sc, m_head, idx)
1995 struct rl_softc *sc;
1996 struct mbuf **m_head;

--- 316 unchanged lines hidden (view full) ---

2313 if (ifp->if_capenable & IFCAP_POLLING)
2314 CSR_WRITE_2(sc, RL_IMR, 0);
2315 else /* otherwise ... */
2316#endif
2317
2318 /*
2319 * Enable interrupts.
2320 */
2308 mtx_lock_spin(&sc->rl_intlock);
2309 if (sc->rl_testmode)
2310 CSR_WRITE_2(sc, RL_IMR, 0);
2311 else
2312 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2313 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
2321 if (sc->rl_testmode)
2322 CSR_WRITE_2(sc, RL_IMR, 0);
2323 else
2324 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2325 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
2314 mtx_unlock_spin(&sc->rl_intlock);
2315
2316 /* Set initial TX threshold */
2317 sc->rl_txthresh = RL_TX_THRESH_INIT;
2318
2319 /* Start RX/TX process. */
2320 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
2321#ifdef notdef
2322 /* Enable receiver and transmitter. */

--- 325 unchanged lines hidden --- 		2326
2327 /* Set initial TX threshold */
2328 sc->rl_txthresh = RL_TX_THRESH_INIT;
2329
2330 /* Start RX/TX process. */
2331 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
2332#ifdef notdef
2333 /* Enable receiver and transmitter. */

--- 325 unchanged lines hidden ---