| if_re.c (119982) | if_re.c (120043) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 92 unchanged lines hidden (view full) --- 101 * interrupt moderation using the timer interrupt registers, which 102 * significantly reduces TX interrupt load. There is also support 103 * for jumbo frames, however the 8169/8169S/8110S can not transmit 104 * jumbo frames larger than 7.5K, so the max MTU possible with this 105 * driver is 7500 bytes. 106 */ 107 108#include <sys/cdefs.h> | 1/* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 92 unchanged lines hidden (view full) --- 101 * interrupt moderation using the timer interrupt registers, which 102 * significantly reduces TX interrupt load. There is also support 103 * for jumbo frames, however the 8169/8169S/8110S can not transmit 104 * jumbo frames larger than 7.5K, so the max MTU possible with this 105 * driver is 7500 bytes. 106 */ 107 108#include <sys/cdefs.h> |
| 109__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 119982 2003-09-11 07:54:16Z wpaul $"); | 109__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 120043 2003-09-13 23:51:35Z wpaul $"); |
| 110 111#include <sys/param.h> 112#include <sys/endian.h> 113#include <sys/systm.h> 114#include <sys/sockio.h> 115#include <sys/mbuf.h> 116#include <sys/malloc.h> 117#include <sys/kernel.h> --- 1953 unchanged lines hidden (view full) --- 2071 mii = device_get_softc(sc->rl_miibus); 2072 2073 /* 2074 * Cancel pending I/O and free all RX/TX buffers. 2075 */ 2076 re_stop(sc); 2077 2078 /* | 110 111#include <sys/param.h> 112#include <sys/endian.h> 113#include <sys/systm.h> 114#include <sys/sockio.h> 115#include <sys/mbuf.h> 116#include <sys/malloc.h> 117#include <sys/kernel.h> --- 1953 unchanged lines hidden (view full) --- 2071 mii = device_get_softc(sc->rl_miibus); 2072 2073 /* 2074 * Cancel pending I/O and free all RX/TX buffers. 2075 */ 2076 re_stop(sc); 2077 2078 /* |
| 2079 * Enable C+ RX and TX mode, as well as VLAN stripping and 2080 * RX checksum offload. Only enable dual-address cycle if 2081 * we're on a 64-bit bus. We must configure the C+ register 2082 * before all others. 2083 */ 2084 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2085 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2086 (CSR_READ_1(sc, RL_CFG2) & RL_BUSWIDTH_64BITS ? 2087 RL_CPLUSCMD_PCI_DAC : 0)|RL_CPLUSCMD_VLANSTRIP| 2088 (ifp->if_capenable & IFCAP_RXCSUM ? 2089 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2090 2091 /* |
|
| 2079 * Init our MAC address. Even though the chipset 2080 * documentation doesn't mention it, we need to enter "Config 2081 * register write enable" mode to modify the ID registers. 2082 */ 2083 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2084 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2085 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 2086 CSR_WRITE_STREAM_4(sc, RL_IDR4, --- 75 unchanged lines hidden (view full) --- 2162 2163 /* Start RX/TX process. */ 2164 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2165#ifdef notdef 2166 /* Enable receiver and transmitter. */ 2167 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2168#endif 2169 /* | 2092 * Init our MAC address. Even though the chipset 2093 * documentation doesn't mention it, we need to enter "Config 2094 * register write enable" mode to modify the ID registers. 2095 */ 2096 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2097 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2098 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 2099 CSR_WRITE_STREAM_4(sc, RL_IDR4, --- 75 unchanged lines hidden (view full) --- 2175 2176 /* Start RX/TX process. */ 2177 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2178#ifdef notdef 2179 /* Enable receiver and transmitter. */ 2180 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2181#endif 2182 /* |
| 2170 * If this is a C+ capable chip, enable C+ RX and TX mode, 2171 * and load the addresses of the RX and TX lists into the chip. | 2183 * Load the addresses of the RX and TX lists into the chip. |
| 2172 */ | 2184 */ |
| 2173 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2174 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2175 RL_CPLUSCMD_VLANSTRIP| 2176 (ifp->if_capenable & IFCAP_RXCSUM ? 2177 RL_CPLUSCMD_RXCSUM_ENB : 0)); | |
| 2178 2179 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2180 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2181 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2182 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2183 2184 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2185 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); --- 295 unchanged lines hidden --- | 2185 2186 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2187 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2188 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2189 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2190 2191 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2192 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); --- 295 unchanged lines hidden --- |