| pcivar.h (42867) | pcivar.h (45720) |
|---|---|
| 1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * | 1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * |
| 26 * $Id: pcivar.h,v 1.24 1999/01/13 04:59:19 bde Exp $ | 26 * $Id: pcivar.h,v 1.25 1999/01/19 23:29:20 se Exp $ |
| 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#ifndef PCI_COMPAT 34#define PCI_COMPAT --- 27 unchanged lines hidden (view full) --- 62 u_int32_t base; 63 u_int8_t type; 64#define PCI_MAPMEM 0x01 /* memory map */ 65#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 66#define PCI_MAPPORT 0x04 /* port map */ 67 u_int8_t ln2size; 68 u_int8_t ln2range; 69 u_int8_t reg; /* offset of map register in config space */ | 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#ifndef PCI_COMPAT 34#define PCI_COMPAT --- 27 unchanged lines hidden (view full) --- 62 u_int32_t base; 63 u_int8_t type; 64#define PCI_MAPMEM 0x01 /* memory map */ 65#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 66#define PCI_MAPPORT 0x04 /* port map */ 67 u_int8_t ln2size; 68 u_int8_t ln2range; 69 u_int8_t reg; /* offset of map register in config space */ |
| 70/* u_int8_t dummy;*/ 71 struct resource *res; /* handle from resource manager */ |
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| 70} pcimap; 71 72/* config header information common to all header types */ 73 74typedef struct pcicfg { | 72} pcimap; 73 74/* config header information common to all header types */ 75 76typedef struct pcicfg { |
| 77 struct device *dev; /* device which owns this */ |
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| 75 pcimap *map; /* pointer to array of PCI maps */ 76 void *hdrspec; /* pointer to header type specific data */ | 78 pcimap *map; /* pointer to array of PCI maps */ 79 void *hdrspec; /* pointer to header type specific data */ |
| 80 struct resource *irqres; /* resource descriptor for interrupt mapping */ |
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| 77 78 u_int16_t subvendor; /* card vendor ID */ 79 u_int16_t subdevice; /* card device ID, assigned by card vendor */ 80 u_int16_t vendor; /* chip vendor ID */ 81 u_int16_t device; /* chip device ID, assigned by chip vendor */ 82 83 u_int16_t cmdreg; /* disable/enable chip and PCI options */ 84 u_int16_t statreg; /* supported PCI features and error state */ --- 92 unchanged lines hidden (view full) --- 177 178int pci_cfgopen (void); 179int pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 180void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 181#ifdef __alpha__ 182vm_offset_t pci_cvt_to_dense (vm_offset_t); 183vm_offset_t pci_cvt_to_bwx (vm_offset_t); 184#endif /* __alpha__ */ | 81 82 u_int16_t subvendor; /* card vendor ID */ 83 u_int16_t subdevice; /* card device ID, assigned by card vendor */ 84 u_int16_t vendor; /* chip vendor ID */ 85 u_int16_t device; /* chip device ID, assigned by chip vendor */ 86 87 u_int16_t cmdreg; /* disable/enable chip and PCI options */ 88 u_int16_t statreg; /* supported PCI features and error state */ --- 92 unchanged lines hidden (view full) --- 181 182int pci_cfgopen (void); 183int pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 184void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 185#ifdef __alpha__ 186vm_offset_t pci_cvt_to_dense (vm_offset_t); 187vm_offset_t pci_cvt_to_bwx (vm_offset_t); 188#endif /* __alpha__ */ |
| 189 190#ifdef _SYS_BUS_H_ 191 192#include "pci_if.h" 193 194enum pci_device_ivars { 195 PCI_IVAR_SUBVENDOR, 196 PCI_IVAR_SUBDEVICE, 197 PCI_IVAR_VENDOR, 198 PCI_IVAR_DEVICE, 199 PCI_IVAR_DEVID, 200 PCI_IVAR_CLASS, 201 PCI_IVAR_SUBCLASS, 202 PCI_IVAR_PROGIF, 203 PCI_IVAR_REVID, 204 PCI_IVAR_INTPIN, 205 PCI_IVAR_IRQ, 206 PCI_IVAR_BUS, 207 PCI_IVAR_SLOT, 208 PCI_IVAR_FUNCTION, 209 PCI_IVAR_SECONDARYBUS, 210 PCI_IVAR_SUBORDINATEBUS, 211}; 212 213/* 214 * Simplified accessors for pci devices 215 */ 216#define PCI_ACCESSOR(A, B, T) \ 217 \ 218static __inline T pci_get_ ## A(device_t dev) \ 219{ \ 220 uintptr_t v; \ 221 BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \ 222 return (T) v; \ 223} \ 224 \ 225static __inline void pci_set_ ## A(device_t dev, T t) \ 226{ \ 227 u_long v = (u_long) t; \ 228 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \ 229} 230 231PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 232PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 233PCI_ACCESSOR(vendor, VENDOR, u_int16_t) 234PCI_ACCESSOR(device, DEVICE, u_int16_t) 235PCI_ACCESSOR(devid, DEVID, u_int32_t) 236PCI_ACCESSOR(class, CLASS, u_int8_t) 237PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 238PCI_ACCESSOR(progif, PROGIF, u_int8_t) 239PCI_ACCESSOR(revid, REVID, u_int8_t) 240PCI_ACCESSOR(intpin, INTPIN, u_int8_t) 241PCI_ACCESSOR(irq, IRQ, u_int8_t) 242PCI_ACCESSOR(bus, BUS, u_int8_t) 243PCI_ACCESSOR(slot, SLOT, u_int8_t) 244PCI_ACCESSOR(function, FUNCTION, u_int8_t) 245PCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t) 246PCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t) 247 248static __inline u_int32_t 249pci_read_config(device_t dev, int reg, int width) 250{ 251 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 252} 253 254static __inline void 255pci_write_config(device_t dev, int reg, u_int32_t val, int width) 256{ 257 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 258} 259 260#endif 261 |
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| 185/* for compatibility to FreeBSD-2.2 version of PCI code */ 186 187#ifdef PCI_COMPAT 188 189typedef pcicfgregs *pcici_t; 190typedef unsigned pcidi_t; 191typedef void pci_inthand_t(void *arg); 192 --- 42 unchanged lines hidden --- | 262/* for compatibility to FreeBSD-2.2 version of PCI code */ 263 264#ifdef PCI_COMPAT 265 266typedef pcicfgregs *pcici_t; 267typedef unsigned pcidi_t; 268typedef void pci_inthand_t(void *arg); 269 --- 42 unchanged lines hidden --- |