| pcireg.h (166048) | pcireg.h (166109) |
|---|---|
| 1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/dev/pci/pcireg.h 166048 2007-01-16 17:04:42Z jhb $ | 26 * $FreeBSD: head/sys/dev/pci/pcireg.h 166109 2007-01-19 22:37:52Z jhb $ |
| 27 * 28 */ 29 30/* 31 * PCIM_xxx: mask to locate subfield in register 32 * PCIR_xxx: config register offset 33 * PCIC_xxx: device class 34 * PCIS_xxx: device subclass --- 373 unchanged lines hidden (view full) --- 408#define PCIR_MSI_ADDR 0x4 409#define PCIR_MSI_ADDR_HIGH 0x8 410#define PCIR_MSI_DATA 0x8 411#define PCIR_MSI_DATA_64BIT 0xc 412#define PCIR_MSI_MASK 0x10 413#define PCIR_MSI_PENDING 0x14 414 415/* PCI-X definitions */ | 27 * 28 */ 29 30/* 31 * PCIM_xxx: mask to locate subfield in register 32 * PCIR_xxx: config register offset 33 * PCIC_xxx: device class 34 * PCIS_xxx: device subclass --- 373 unchanged lines hidden (view full) --- 408#define PCIR_MSI_ADDR 0x4 409#define PCIR_MSI_ADDR_HIGH 0x8 410#define PCIR_MSI_DATA 0x8 411#define PCIR_MSI_DATA_64BIT 0xc 412#define PCIR_MSI_MASK 0x10 413#define PCIR_MSI_PENDING 0x14 414 415/* PCI-X definitions */ |
| 416#define PCIXR_COMMAND 0x96 417#define PCIXR_DEVADDR 0x98 418#define PCIXM_DEVADDR_FNUM 0x0003 /* Function Number */ 419#define PCIXM_DEVADDR_DNUM 0x00F8 /* Device Number */ 420#define PCIXM_DEVADDR_BNUM 0xFF00 /* Bus Number */ 421#define PCIXR_STATUS 0x9A 422#define PCIXM_STATUS_64BIT 0x0001 /* Active 64bit connection to device. */ 423#define PCIXM_STATUS_133CAP 0x0002 /* Device is 133MHz capable */ 424#define PCIXM_STATUS_SCDISC 0x0004 /* Split Completion Discarded */ 425#define PCIXM_STATUS_UNEXPSC 0x0008 /* Unexpected Split Completion */ 426#define PCIXM_STATUS_CMPLEXDEV 0x0010 /* Device Complexity (set == bridge) */ 427#define PCIXM_STATUS_MAXMRDBC 0x0060 /* Maximum Burst Read Count */ 428#define PCIXM_STATUS_MAXSPLITS 0x0380 /* Maximum Split Transactions */ 429#define PCIXM_STATUS_MAXCRDS 0x1C00 /* Maximum Cumulative Read Size */ 430#define PCIXM_STATUS_RCVDSCEM 0x2000 /* Received a Split Comp w/Error msg */ | |
| 431 | 416 |
| 417/* For header type 0 devices */ 418#define PCIXR_COMMAND 0x2 419#define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */ 420#define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ 421#define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */ 422#define PCIXM_COMMAND_MAX_READ_512 0x0000 423#define PCIXM_COMMAND_MAX_READ_1024 0x0004 424#define PCIXM_COMMAND_MAX_READ_2048 0x0008 425#define PCIXM_COMMAND_MAX_READ_4096 0x000c 426#define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */ 427#define PCIXM_COMMAND_MAX_SPLITS_1 0x0000 428#define PCIXM_COMMAND_MAX_SPLITS_2 0x0010 429#define PCIXM_COMMAND_MAX_SPLITS_3 0x0020 430#define PCIXM_COMMAND_MAX_SPLITS_4 0x0030 431#define PCIXM_COMMAND_MAX_SPLITS_8 0x0040 432#define PCIXM_COMMAND_MAX_SPLITS_12 0x0050 433#define PCIXM_COMMAND_MAX_SPLITS_16 0x0060 434#define PCIXM_COMMAND_MAX_SPLITS_32 0x0070 435#define PCIXM_COMMAND_VERSION 0x3000 436#define PCIXR_STATUS 0x4 437#define PCIXM_STATUS_DEVFN 0x000000FF 438#define PCIXM_STATUS_BUS 0x0000FF00 439#define PCIXM_STATUS_64BIT 0x00010000 440#define PCIXM_STATUS_133CAP 0x00020000 441#define PCIXM_STATUS_SC_DISCARDED 0x00040000 442#define PCIXM_STATUS_UNEXP_SC 0x00080000 443#define PCIXM_STATUS_COMPLEX_DEV 0x00100000 444#define PCIXM_STATUS_MAX_READ 0x00600000 445#define PCIXM_STATUS_MAX_READ_512 0x00000000 446#define PCIXM_STATUS_MAX_READ_1024 0x00200000 447#define PCIXM_STATUS_MAX_READ_2048 0x00400000 448#define PCIXM_STATUS_MAX_READ_4096 0x00600000 449#define PCIXM_STATUS_MAX_SPLITS 0x03800000 450#define PCIXM_STATUS_MAX_SPLITS_1 0x00000000 451#define PCIXM_STATUS_MAX_SPLITS_2 0x00800000 452#define PCIXM_STATUS_MAX_SPLITS_3 0x01000000 453#define PCIXM_STATUS_MAX_SPLITS_4 0x01800000 454#define PCIXM_STATUS_MAX_SPLITS_8 0x02000000 455#define PCIXM_STATUS_MAX_SPLITS_12 0x02800000 456#define PCIXM_STATUS_MAX_SPLITS_16 0x03000000 457#define PCIXM_STATUS_MAX_SPLITS_32 0x03800000 458#define PCIXM_STATUS_MAX_CUM_READ 0x1C000000 459#define PCIXM_STATUS_RCVD_SC_ERR 0x20000000 460#define PCIXM_STATUS_266CAP 0x40000000 461#define PCIXM_STATUS_533CAP 0x80000000 462 463/* For header type 1 devices (PCI-X bridges) */ 464#define PCIXR_SEC_STATUS 0x2 465#define PCIXM_SEC_STATUS_64BIT 0x0001 466#define PCIXM_SEC_STATUS_133CAP 0x0002 467#define PCIXM_SEC_STATUS_SC_DISC 0x0004 468#define PCIXM_SEC_STATUS_UNEXP_SC 0x0008 469#define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010 470#define PCIXM_SEC_STATUS_SR_DELAYED 0x0020 471#define PCIXM_SEC_STATUS_BUS_MODE 0x03c0 472#define PCIXM_SEC_STATUS_VERSION 0x3000 473#define PCIXM_SEC_STATUS_266CAP 0x4000 474#define PCIXM_SEC_STATUS_533CAP 0x8000 475#define PCIXR_BRIDGE_STATUS 0x4 476#define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF 477#define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00 478#define PCIXM_BRIDGE_STATUS_64BIT 0x00010000 479#define PCIXM_BRIDGE_STATUS_133CAP 0x00020000 480#define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000 481#define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000 482#define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000 483#define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000 484#define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000 485#define PCIXM_BRIDGE_STATUS_266CAP 0x40000000 486#define PCIXM_BRIDGE_STATUS_533CAP 0x80000000 487 |
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| 432/* HT (HyperTransport) Capability definitions */ 433#define PCIR_HT_COMMAND 0x2 434#define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ 435#define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ 436#define PCIM_HTCAP_HOST 0x2000 /* 001xx */ 437#define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ 438#define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ 439#define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ --- 31 unchanged lines hidden --- | 488/* HT (HyperTransport) Capability definitions */ 489#define PCIR_HT_COMMAND 0x2 490#define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ 491#define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ 492#define PCIM_HTCAP_HOST 0x2000 /* 001xx */ 493#define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ 494#define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ 495#define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ --- 31 unchanged lines hidden --- |