26c26
< * $FreeBSD: head/sys/dev/pci/pcireg.h 166048 2007-01-16 17:04:42Z jhb $
---
> * $FreeBSD: head/sys/dev/pci/pcireg.h 166109 2007-01-19 22:37:52Z jhb $
416,430d415
< #define PCIXR_COMMAND 0x96
< #define PCIXR_DEVADDR 0x98
< #define PCIXM_DEVADDR_FNUM 0x0003 /* Function Number */
< #define PCIXM_DEVADDR_DNUM 0x00F8 /* Device Number */
< #define PCIXM_DEVADDR_BNUM 0xFF00 /* Bus Number */
< #define PCIXR_STATUS 0x9A
< #define PCIXM_STATUS_64BIT 0x0001 /* Active 64bit connection to device. */
< #define PCIXM_STATUS_133CAP 0x0002 /* Device is 133MHz capable */
< #define PCIXM_STATUS_SCDISC 0x0004 /* Split Completion Discarded */
< #define PCIXM_STATUS_UNEXPSC 0x0008 /* Unexpected Split Completion */
< #define PCIXM_STATUS_CMPLEXDEV 0x0010 /* Device Complexity (set == bridge) */
< #define PCIXM_STATUS_MAXMRDBC 0x0060 /* Maximum Burst Read Count */
< #define PCIXM_STATUS_MAXSPLITS 0x0380 /* Maximum Split Transactions */
< #define PCIXM_STATUS_MAXCRDS 0x1C00 /* Maximum Cumulative Read Size */
< #define PCIXM_STATUS_RCVDSCEM 0x2000 /* Received a Split Comp w/Error msg */
431a417,487
> /* For header type 0 devices */
> #define PCIXR_COMMAND 0x2
> #define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */
> #define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
> #define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */
> #define PCIXM_COMMAND_MAX_READ_512 0x0000
> #define PCIXM_COMMAND_MAX_READ_1024 0x0004
> #define PCIXM_COMMAND_MAX_READ_2048 0x0008
> #define PCIXM_COMMAND_MAX_READ_4096 0x000c
> #define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */
> #define PCIXM_COMMAND_MAX_SPLITS_1 0x0000
> #define PCIXM_COMMAND_MAX_SPLITS_2 0x0010
> #define PCIXM_COMMAND_MAX_SPLITS_3 0x0020
> #define PCIXM_COMMAND_MAX_SPLITS_4 0x0030
> #define PCIXM_COMMAND_MAX_SPLITS_8 0x0040
> #define PCIXM_COMMAND_MAX_SPLITS_12 0x0050
> #define PCIXM_COMMAND_MAX_SPLITS_16 0x0060
> #define PCIXM_COMMAND_MAX_SPLITS_32 0x0070
> #define PCIXM_COMMAND_VERSION 0x3000
> #define PCIXR_STATUS 0x4
> #define PCIXM_STATUS_DEVFN 0x000000FF
> #define PCIXM_STATUS_BUS 0x0000FF00
> #define PCIXM_STATUS_64BIT 0x00010000
> #define PCIXM_STATUS_133CAP 0x00020000
> #define PCIXM_STATUS_SC_DISCARDED 0x00040000
> #define PCIXM_STATUS_UNEXP_SC 0x00080000
> #define PCIXM_STATUS_COMPLEX_DEV 0x00100000
> #define PCIXM_STATUS_MAX_READ 0x00600000
> #define PCIXM_STATUS_MAX_READ_512 0x00000000
> #define PCIXM_STATUS_MAX_READ_1024 0x00200000
> #define PCIXM_STATUS_MAX_READ_2048 0x00400000
> #define PCIXM_STATUS_MAX_READ_4096 0x00600000
> #define PCIXM_STATUS_MAX_SPLITS 0x03800000
> #define PCIXM_STATUS_MAX_SPLITS_1 0x00000000
> #define PCIXM_STATUS_MAX_SPLITS_2 0x00800000
> #define PCIXM_STATUS_MAX_SPLITS_3 0x01000000
> #define PCIXM_STATUS_MAX_SPLITS_4 0x01800000
> #define PCIXM_STATUS_MAX_SPLITS_8 0x02000000
> #define PCIXM_STATUS_MAX_SPLITS_12 0x02800000
> #define PCIXM_STATUS_MAX_SPLITS_16 0x03000000
> #define PCIXM_STATUS_MAX_SPLITS_32 0x03800000
> #define PCIXM_STATUS_MAX_CUM_READ 0x1C000000
> #define PCIXM_STATUS_RCVD_SC_ERR 0x20000000
> #define PCIXM_STATUS_266CAP 0x40000000
> #define PCIXM_STATUS_533CAP 0x80000000
>
> /* For header type 1 devices (PCI-X bridges) */
> #define PCIXR_SEC_STATUS 0x2
> #define PCIXM_SEC_STATUS_64BIT 0x0001
> #define PCIXM_SEC_STATUS_133CAP 0x0002
> #define PCIXM_SEC_STATUS_SC_DISC 0x0004
> #define PCIXM_SEC_STATUS_UNEXP_SC 0x0008
> #define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010
> #define PCIXM_SEC_STATUS_SR_DELAYED 0x0020
> #define PCIXM_SEC_STATUS_BUS_MODE 0x03c0
> #define PCIXM_SEC_STATUS_VERSION 0x3000
> #define PCIXM_SEC_STATUS_266CAP 0x4000
> #define PCIXM_SEC_STATUS_533CAP 0x8000
> #define PCIXR_BRIDGE_STATUS 0x4
> #define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF
> #define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00
> #define PCIXM_BRIDGE_STATUS_64BIT 0x00010000
> #define PCIXM_BRIDGE_STATUS_133CAP 0x00020000
> #define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000
> #define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000
> #define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000
> #define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000
> #define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000
> #define PCIXM_BRIDGE_STATUS_266CAP 0x40000000
> #define PCIXM_BRIDGE_STATUS_533CAP 0x80000000
>
< * $FreeBSD: head/sys/dev/pci/pcireg.h 166048 2007-01-16 17:04:42Z jhb $
---
> * $FreeBSD: head/sys/dev/pci/pcireg.h 166109 2007-01-19 22:37:52Z jhb $
416,430d415
< #define PCIXR_COMMAND 0x96
< #define PCIXR_DEVADDR 0x98
< #define PCIXM_DEVADDR_FNUM 0x0003 /* Function Number */
< #define PCIXM_DEVADDR_DNUM 0x00F8 /* Device Number */
< #define PCIXM_DEVADDR_BNUM 0xFF00 /* Bus Number */
< #define PCIXR_STATUS 0x9A
< #define PCIXM_STATUS_64BIT 0x0001 /* Active 64bit connection to device. */
< #define PCIXM_STATUS_133CAP 0x0002 /* Device is 133MHz capable */
< #define PCIXM_STATUS_SCDISC 0x0004 /* Split Completion Discarded */
< #define PCIXM_STATUS_UNEXPSC 0x0008 /* Unexpected Split Completion */
< #define PCIXM_STATUS_CMPLEXDEV 0x0010 /* Device Complexity (set == bridge) */
< #define PCIXM_STATUS_MAXMRDBC 0x0060 /* Maximum Burst Read Count */
< #define PCIXM_STATUS_MAXSPLITS 0x0380 /* Maximum Split Transactions */
< #define PCIXM_STATUS_MAXCRDS 0x1C00 /* Maximum Cumulative Read Size */
< #define PCIXM_STATUS_RCVDSCEM 0x2000 /* Received a Split Comp w/Error msg */
431a417,487
> /* For header type 0 devices */
> #define PCIXR_COMMAND 0x2
> #define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */
> #define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
> #define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */
> #define PCIXM_COMMAND_MAX_READ_512 0x0000
> #define PCIXM_COMMAND_MAX_READ_1024 0x0004
> #define PCIXM_COMMAND_MAX_READ_2048 0x0008
> #define PCIXM_COMMAND_MAX_READ_4096 0x000c
> #define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */
> #define PCIXM_COMMAND_MAX_SPLITS_1 0x0000
> #define PCIXM_COMMAND_MAX_SPLITS_2 0x0010
> #define PCIXM_COMMAND_MAX_SPLITS_3 0x0020
> #define PCIXM_COMMAND_MAX_SPLITS_4 0x0030
> #define PCIXM_COMMAND_MAX_SPLITS_8 0x0040
> #define PCIXM_COMMAND_MAX_SPLITS_12 0x0050
> #define PCIXM_COMMAND_MAX_SPLITS_16 0x0060
> #define PCIXM_COMMAND_MAX_SPLITS_32 0x0070
> #define PCIXM_COMMAND_VERSION 0x3000
> #define PCIXR_STATUS 0x4
> #define PCIXM_STATUS_DEVFN 0x000000FF
> #define PCIXM_STATUS_BUS 0x0000FF00
> #define PCIXM_STATUS_64BIT 0x00010000
> #define PCIXM_STATUS_133CAP 0x00020000
> #define PCIXM_STATUS_SC_DISCARDED 0x00040000
> #define PCIXM_STATUS_UNEXP_SC 0x00080000
> #define PCIXM_STATUS_COMPLEX_DEV 0x00100000
> #define PCIXM_STATUS_MAX_READ 0x00600000
> #define PCIXM_STATUS_MAX_READ_512 0x00000000
> #define PCIXM_STATUS_MAX_READ_1024 0x00200000
> #define PCIXM_STATUS_MAX_READ_2048 0x00400000
> #define PCIXM_STATUS_MAX_READ_4096 0x00600000
> #define PCIXM_STATUS_MAX_SPLITS 0x03800000
> #define PCIXM_STATUS_MAX_SPLITS_1 0x00000000
> #define PCIXM_STATUS_MAX_SPLITS_2 0x00800000
> #define PCIXM_STATUS_MAX_SPLITS_3 0x01000000
> #define PCIXM_STATUS_MAX_SPLITS_4 0x01800000
> #define PCIXM_STATUS_MAX_SPLITS_8 0x02000000
> #define PCIXM_STATUS_MAX_SPLITS_12 0x02800000
> #define PCIXM_STATUS_MAX_SPLITS_16 0x03000000
> #define PCIXM_STATUS_MAX_SPLITS_32 0x03800000
> #define PCIXM_STATUS_MAX_CUM_READ 0x1C000000
> #define PCIXM_STATUS_RCVD_SC_ERR 0x20000000
> #define PCIXM_STATUS_266CAP 0x40000000
> #define PCIXM_STATUS_533CAP 0x80000000
>
> /* For header type 1 devices (PCI-X bridges) */
> #define PCIXR_SEC_STATUS 0x2
> #define PCIXM_SEC_STATUS_64BIT 0x0001
> #define PCIXM_SEC_STATUS_133CAP 0x0002
> #define PCIXM_SEC_STATUS_SC_DISC 0x0004
> #define PCIXM_SEC_STATUS_UNEXP_SC 0x0008
> #define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010
> #define PCIXM_SEC_STATUS_SR_DELAYED 0x0020
> #define PCIXM_SEC_STATUS_BUS_MODE 0x03c0
> #define PCIXM_SEC_STATUS_VERSION 0x3000
> #define PCIXM_SEC_STATUS_266CAP 0x4000
> #define PCIXM_SEC_STATUS_533CAP 0x8000
> #define PCIXR_BRIDGE_STATUS 0x4
> #define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF
> #define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00
> #define PCIXM_BRIDGE_STATUS_64BIT 0x00010000
> #define PCIXM_BRIDGE_STATUS_133CAP 0x00020000
> #define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000
> #define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000
> #define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000
> #define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000
> #define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000
> #define PCIXM_BRIDGE_STATUS_266CAP 0x40000000
> #define PCIXM_BRIDGE_STATUS_533CAP 0x80000000
>