1/*-
2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
| 1/*-
2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
|
30 * $FreeBSD: head/sys/dev/pci/pci_pci.c 103016 2002-09-06 16:09:07Z jhb $
| 30 * $FreeBSD: head/sys/dev/pci/pci_pci.c 103042 2002-09-06 22:14:00Z jhb $
|
31 */
32
33/*
34 * PCI:PCI bridge support.
35 */
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/kernel.h>
40#include <sys/bus.h>
41
42#include <machine/resource.h>
43
44#include <pci/pcivar.h>
45#include <pci/pcireg.h>
46#include <pci/pcib_private.h>
47
48#include "pcib_if.h"
49#include "opt_pci.h"
50
51static int pcib_probe(device_t dev);
| 31 */
32
33/*
34 * PCI:PCI bridge support.
35 */
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/kernel.h>
40#include <sys/bus.h>
41
42#include <machine/resource.h>
43
44#include <pci/pcivar.h>
45#include <pci/pcireg.h>
46#include <pci/pcib_private.h>
47
48#include "pcib_if.h"
49#include "opt_pci.h"
50
51static int pcib_probe(device_t dev);
|
52static int pcib_attach(device_t dev);
| |
53static int pcib_route_interrupt(device_t pcib, device_t dev, int pin);
54
55static device_method_t pcib_methods[] = {
56 /* Device interface */
57 DEVMETHOD(device_probe, pcib_probe),
58 DEVMETHOD(device_attach, pcib_attach),
59 DEVMETHOD(device_shutdown, bus_generic_shutdown),
60 DEVMETHOD(device_suspend, bus_generic_suspend),
61 DEVMETHOD(device_resume, bus_generic_resume),
62
63 /* Bus interface */
64 DEVMETHOD(bus_print_child, bus_generic_print_child),
65 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
66 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
67 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
68 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
69 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
70 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
71 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
72 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
73
74 /* pcib interface */
75 DEVMETHOD(pcib_maxslots, pcib_maxslots),
76 DEVMETHOD(pcib_read_config, pcib_read_config),
77 DEVMETHOD(pcib_write_config, pcib_write_config),
78 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
79
80 { 0, 0 }
81};
82
83static driver_t pcib_driver = {
84 "pcib",
85 pcib_methods,
86 sizeof(struct pcib_softc),
87};
88
89devclass_t pcib_devclass;
90
91DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
92
93/*
94 * Generic device interface
95 */
96static int
97pcib_probe(device_t dev)
98{
99 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
100 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
101 device_set_desc(dev, "PCI-PCI bridge");
102 return(-10000);
103 }
104 return(ENXIO);
105}
106
107void
108pcib_attach_common(device_t dev)
109{
110 struct pcib_softc *sc;
111 u_int8_t iolow;
112
113 sc = device_get_softc(dev);
114 sc->dev = dev;
115
116 /*
117 * Get current bridge configuration.
118 */
119 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
120 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
121 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
122 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
123 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
124 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
125
126 /*
127 * Determine current I/O decode.
128 */
129 if (sc->command & PCIM_CMD_PORTEN) {
130 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
131 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
132 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
133 pci_read_config(dev, PCIR_IOBASEL_1, 1));
134 } else {
135 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
136 }
137
138 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
139 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
140 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
141 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
142 } else {
143 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
144 }
145 }
146
147 /*
148 * Determine current memory decode.
149 */
150 if (sc->command & PCIM_CMD_MEMEN) {
151 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
152 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
153 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
154 pci_read_config(dev, PCIR_PMBASEL_1, 2));
155 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
156 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
157 }
158
159 /*
160 * Quirk handling.
161 */
162 switch (pci_get_devid(dev)) {
163 case 0x12258086: /* Intel 82454KX/GX (Orion) */
164 {
165 u_int8_t supbus;
166
167 supbus = pci_read_config(dev, 0x41, 1);
168 if (supbus != 0xff) {
169 sc->secbus = supbus + 1;
170 sc->subbus = supbus + 1;
171 }
172 }
173 break;
174 }
175
176 if (bootverbose) {
177 device_printf(dev, " secondary bus %d\n", sc->secbus);
178 device_printf(dev, " subordinate bus %d\n", sc->subbus);
179 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
180 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
181 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
182 }
183
184 /*
185 * XXX If the secondary bus number is zero, we should assign a bus number
186 * since the BIOS hasn't, then initialise the bridge.
187 */
188
189 /*
190 * XXX If the subordinate bus number is less than the secondary bus number,
191 * we should pick a better value. One sensible alternative would be to
192 * pick 255; the only tradeoff here is that configuration transactions
193 * would be more widely routed than absolutely necessary.
194 */
195}
196
| 52static int pcib_route_interrupt(device_t pcib, device_t dev, int pin);
53
54static device_method_t pcib_methods[] = {
55 /* Device interface */
56 DEVMETHOD(device_probe, pcib_probe),
57 DEVMETHOD(device_attach, pcib_attach),
58 DEVMETHOD(device_shutdown, bus_generic_shutdown),
59 DEVMETHOD(device_suspend, bus_generic_suspend),
60 DEVMETHOD(device_resume, bus_generic_resume),
61
62 /* Bus interface */
63 DEVMETHOD(bus_print_child, bus_generic_print_child),
64 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
65 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
66 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
67 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
68 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
69 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
70 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
71 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
72
73 /* pcib interface */
74 DEVMETHOD(pcib_maxslots, pcib_maxslots),
75 DEVMETHOD(pcib_read_config, pcib_read_config),
76 DEVMETHOD(pcib_write_config, pcib_write_config),
77 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
78
79 { 0, 0 }
80};
81
82static driver_t pcib_driver = {
83 "pcib",
84 pcib_methods,
85 sizeof(struct pcib_softc),
86};
87
88devclass_t pcib_devclass;
89
90DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
91
92/*
93 * Generic device interface
94 */
95static int
96pcib_probe(device_t dev)
97{
98 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
99 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
100 device_set_desc(dev, "PCI-PCI bridge");
101 return(-10000);
102 }
103 return(ENXIO);
104}
105
106void
107pcib_attach_common(device_t dev)
108{
109 struct pcib_softc *sc;
110 u_int8_t iolow;
111
112 sc = device_get_softc(dev);
113 sc->dev = dev;
114
115 /*
116 * Get current bridge configuration.
117 */
118 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
119 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
120 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
121 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
122 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
123 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
124
125 /*
126 * Determine current I/O decode.
127 */
128 if (sc->command & PCIM_CMD_PORTEN) {
129 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
130 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
131 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
132 pci_read_config(dev, PCIR_IOBASEL_1, 1));
133 } else {
134 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
135 }
136
137 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
138 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
139 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
140 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
141 } else {
142 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
143 }
144 }
145
146 /*
147 * Determine current memory decode.
148 */
149 if (sc->command & PCIM_CMD_MEMEN) {
150 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
151 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
152 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
153 pci_read_config(dev, PCIR_PMBASEL_1, 2));
154 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
155 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
156 }
157
158 /*
159 * Quirk handling.
160 */
161 switch (pci_get_devid(dev)) {
162 case 0x12258086: /* Intel 82454KX/GX (Orion) */
163 {
164 u_int8_t supbus;
165
166 supbus = pci_read_config(dev, 0x41, 1);
167 if (supbus != 0xff) {
168 sc->secbus = supbus + 1;
169 sc->subbus = supbus + 1;
170 }
171 }
172 break;
173 }
174
175 if (bootverbose) {
176 device_printf(dev, " secondary bus %d\n", sc->secbus);
177 device_printf(dev, " subordinate bus %d\n", sc->subbus);
178 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
179 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
180 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
181 }
182
183 /*
184 * XXX If the secondary bus number is zero, we should assign a bus number
185 * since the BIOS hasn't, then initialise the bridge.
186 */
187
188 /*
189 * XXX If the subordinate bus number is less than the secondary bus number,
190 * we should pick a better value. One sensible alternative would be to
191 * pick 255; the only tradeoff here is that configuration transactions
192 * would be more widely routed than absolutely necessary.
193 */
194}
195
|
197static int
| 196int
|
198pcib_attach(device_t dev)
199{
200 struct pcib_softc *sc;
201 device_t child;
202
203 pcib_attach_common(dev);
204 sc = device_get_softc(dev);
205 if (sc->secbus != 0) {
206 child = device_add_child(dev, "pci", sc->secbus);
207 if (child != NULL)
208 return(bus_generic_attach(dev));
209 }
210
211 /* no secondary bus; we should have fixed this */
212 return(0);
213}
214
215int
216pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
217{
218 struct pcib_softc *sc = device_get_softc(dev);
219
220 switch (which) {
221 case PCIB_IVAR_BUS:
222 *result = sc->secbus;
223 return(0);
224 }
225 return(ENOENT);
226}
227
228int
229pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
230{
231 struct pcib_softc *sc = device_get_softc(dev);
232
233 switch (which) {
234 case PCIB_IVAR_BUS:
235 sc->secbus = value;
236 break;
237 }
238 return(ENOENT);
239}
240
241/*
242 * Is this a decoded ISA I/O port address? Note, we need to do the mask that
243 * we do below because of the ISA alias addresses. I'm not 100% sure that
244 * this is correct.
245 */
246static int
247pcib_is_isa_io(u_long start)
248{
249 if ((start & 0xfffUL) > 0x3ffUL || start == 0)
250 return (0);
251 return (1);
252}
253
254/*
255 * Is this a decoded ISA memory address?
256 */
257static int
258pcib_is_isa_mem(u_long start)
259{
260 if (start > 0xfffffUL || start == 0)
261 return (0);
262 return (1);
263}
264
265/*
266 * We have to trap resource allocation requests and ensure that the bridge
267 * is set up to, or capable of handling them.
268 */
269struct resource *
270pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
271 u_long start, u_long end, u_long count, u_int flags)
272{
273 struct pcib_softc *sc = device_get_softc(dev);
274
275 /*
276 * If this is a "default" allocation against this rid, we can't work
277 * out where it's coming from (we should actually never see these) so we
278 * just have to punt.
279 */
280 if ((start == 0) && (end == ~0)) {
281 device_printf(dev, "can't decode default resource id %d for %s%d, bypassing\n",
282 *rid, device_get_name(child), device_get_unit(child));
283 } else {
284 /*
285 * Fail the allocation for this range if it's not supported.
286 *
287 * XXX we should probably just fix up the bridge decode and soldier on.
288 */
289 switch (type) {
290 case SYS_RES_IOPORT:
291 if (!pcib_is_isa_io(start)) {
292#ifndef PCI_ALLOW_UNSUPPORTED_IO_RANGE
293 if (start < sc->iobase)
294 start = sc->iobase;
295 if (end > sc->iolimit)
296 end = sc->iolimit;
297 if (end < start)
298 start = 0;
299#else
300 if (start < sc->iobase)
301 printf("start (%lx) < sc->iobase (%x)\n", start, sc->iobase);
302 if (end > sc->iolimit)
303 printf("end (%lx) > sc->iolimit (%x)\n", end, sc->iolimit);
304 if (end < start)
305 printf("end (%lx) < start (%lx)\n", end, start);
306#endif
307 }
308 if (!pcib_is_isa_io(start) &&
309 ((start < sc->iobase) || (end > sc->iolimit))) {
310 device_printf(dev, "device %s%d requested unsupported I/O range 0x%lx-0x%lx"
311 " (decoding 0x%x-0x%x)\n",
312 device_get_name(child), device_get_unit(child), start, end,
313 sc->iobase, sc->iolimit);
314 return (NULL);
315 }
316 if (bootverbose)
317 device_printf(sc->dev, "device %s%d requested decoded I/O range 0x%lx-0x%lx\n",
318 device_get_name(child), device_get_unit(child), start, end);
319 break;
320
321 /*
322 * XXX will have to decide whether the device making the request is asking
323 * for prefetchable memory or not. If it's coming from another bridge
324 * down the line, do we assume not, or ask the bridge to pass in another
325 * flag as the request bubbles up?
326 */
327 case SYS_RES_MEMORY:
328 if (!pcib_is_isa_mem(start)) {
329#ifndef PCI_ALLOW_UNSUPPORTED_IO_RANGE
330 if (start < sc->membase && end >= sc->membase)
331 start = sc->membase;
332 if (end > sc->memlimit)
333 end = sc->memlimit;
334 if (end < start)
335 start = 0;
336#else
337 if (start < sc->membase && end > sc->membase)
338 printf("start (%lx) < sc->membase (%x)\n", start, sc->membase);
339 if (end > sc->memlimit)
340 printf("end (%lx) > sc->memlimit (%x)\n", end, sc->memlimit);
341 if (end < start)
342 printf("end (%lx) < start (%lx)\n", end, start);
343#endif
344 }
345 if (!pcib_is_isa_mem(start) &&
346 (((start < sc->membase) || (end > sc->memlimit)) &&
347 ((start < sc->pmembase) || (end > sc->pmemlimit)))) {
348 if (bootverbose)
349 device_printf(dev,
350 "device %s%d requested unsupported memory range "
351 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
352 device_get_name(child), device_get_unit(child), start,
353 end, sc->membase, sc->memlimit, sc->pmembase,
354 sc->pmemlimit);
355#ifndef PCI_ALLOW_UNSUPPORTED_IO_RANGE
356 return(NULL);
357#endif
358 }
359 if (bootverbose)
360 device_printf(sc->dev, "device %s%d requested decoded memory range 0x%lx-0x%lx\n",
361 device_get_name(child), device_get_unit(child), start, end);
362 break;
363
364 default:
365 break;
366 }
367 }
368
369 /*
370 * Bridge is OK decoding this resource, so pass it up.
371 */
372 return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags));
373}
374
375/*
376 * PCIB interface.
377 */
378int
379pcib_maxslots(device_t dev)
380{
381 return(PCI_SLOTMAX);
382}
383
384/*
385 * Since we are a child of a PCI bus, its parent must support the pcib interface.
386 */
387u_int32_t
388pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
389{
390 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
391}
392
393void
394pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width)
395{
396 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
397}
398
399/*
400 * Route an interrupt across a PCI bridge.
401 */
402static int
403pcib_route_interrupt(device_t pcib, device_t dev, int pin)
404{
405 device_t bus;
406 int parent_intpin;
407 int intnum;
408
409 /*
410 *
411 * The PCI standard defines a swizzle of the child-side device/intpin to
412 * the parent-side intpin as follows.
413 *
414 * device = device on child bus
415 * child_intpin = intpin on child bus slot (0-3)
416 * parent_intpin = intpin on parent bus slot (0-3)
417 *
418 * parent_intpin = (device + child_intpin) % 4
419 */
420 parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4;
421
422 /*
423 * Our parent is a PCI bus. Its parent must export the pcib interface
424 * which includes the ability to route interrupts.
425 */
426 bus = device_get_parent(pcib);
427 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
428 if (PCI_INTERRUPT_VALID(intnum)) {
429 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
430 pci_get_slot(dev), 'A' + pin - 1, intnum);
431 }
432 return(intnum);
433}
| 197pcib_attach(device_t dev)
198{
199 struct pcib_softc *sc;
200 device_t child;
201
202 pcib_attach_common(dev);
203 sc = device_get_softc(dev);
204 if (sc->secbus != 0) {
205 child = device_add_child(dev, "pci", sc->secbus);
206 if (child != NULL)
207 return(bus_generic_attach(dev));
208 }
209
210 /* no secondary bus; we should have fixed this */
211 return(0);
212}
213
214int
215pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
216{
217 struct pcib_softc *sc = device_get_softc(dev);
218
219 switch (which) {
220 case PCIB_IVAR_BUS:
221 *result = sc->secbus;
222 return(0);
223 }
224 return(ENOENT);
225}
226
227int
228pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
229{
230 struct pcib_softc *sc = device_get_softc(dev);
231
232 switch (which) {
233 case PCIB_IVAR_BUS:
234 sc->secbus = value;
235 break;
236 }
237 return(ENOENT);
238}
239
240/*
241 * Is this a decoded ISA I/O port address? Note, we need to do the mask that
242 * we do below because of the ISA alias addresses. I'm not 100% sure that
243 * this is correct.
244 */
245static int
246pcib_is_isa_io(u_long start)
247{
248 if ((start & 0xfffUL) > 0x3ffUL || start == 0)
249 return (0);
250 return (1);
251}
252
253/*
254 * Is this a decoded ISA memory address?
255 */
256static int
257pcib_is_isa_mem(u_long start)
258{
259 if (start > 0xfffffUL || start == 0)
260 return (0);
261 return (1);
262}
263
264/*
265 * We have to trap resource allocation requests and ensure that the bridge
266 * is set up to, or capable of handling them.
267 */
268struct resource *
269pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
270 u_long start, u_long end, u_long count, u_int flags)
271{
272 struct pcib_softc *sc = device_get_softc(dev);
273
274 /*
275 * If this is a "default" allocation against this rid, we can't work
276 * out where it's coming from (we should actually never see these) so we
277 * just have to punt.
278 */
279 if ((start == 0) && (end == ~0)) {
280 device_printf(dev, "can't decode default resource id %d for %s%d, bypassing\n",
281 *rid, device_get_name(child), device_get_unit(child));
282 } else {
283 /*
284 * Fail the allocation for this range if it's not supported.
285 *
286 * XXX we should probably just fix up the bridge decode and soldier on.
287 */
288 switch (type) {
289 case SYS_RES_IOPORT:
290 if (!pcib_is_isa_io(start)) {
291#ifndef PCI_ALLOW_UNSUPPORTED_IO_RANGE
292 if (start < sc->iobase)
293 start = sc->iobase;
294 if (end > sc->iolimit)
295 end = sc->iolimit;
296 if (end < start)
297 start = 0;
298#else
299 if (start < sc->iobase)
300 printf("start (%lx) < sc->iobase (%x)\n", start, sc->iobase);
301 if (end > sc->iolimit)
302 printf("end (%lx) > sc->iolimit (%x)\n", end, sc->iolimit);
303 if (end < start)
304 printf("end (%lx) < start (%lx)\n", end, start);
305#endif
306 }
307 if (!pcib_is_isa_io(start) &&
308 ((start < sc->iobase) || (end > sc->iolimit))) {
309 device_printf(dev, "device %s%d requested unsupported I/O range 0x%lx-0x%lx"
310 " (decoding 0x%x-0x%x)\n",
311 device_get_name(child), device_get_unit(child), start, end,
312 sc->iobase, sc->iolimit);
313 return (NULL);
314 }
315 if (bootverbose)
316 device_printf(sc->dev, "device %s%d requested decoded I/O range 0x%lx-0x%lx\n",
317 device_get_name(child), device_get_unit(child), start, end);
318 break;
319
320 /*
321 * XXX will have to decide whether the device making the request is asking
322 * for prefetchable memory or not. If it's coming from another bridge
323 * down the line, do we assume not, or ask the bridge to pass in another
324 * flag as the request bubbles up?
325 */
326 case SYS_RES_MEMORY:
327 if (!pcib_is_isa_mem(start)) {
328#ifndef PCI_ALLOW_UNSUPPORTED_IO_RANGE
329 if (start < sc->membase && end >= sc->membase)
330 start = sc->membase;
331 if (end > sc->memlimit)
332 end = sc->memlimit;
333 if (end < start)
334 start = 0;
335#else
336 if (start < sc->membase && end > sc->membase)
337 printf("start (%lx) < sc->membase (%x)\n", start, sc->membase);
338 if (end > sc->memlimit)
339 printf("end (%lx) > sc->memlimit (%x)\n", end, sc->memlimit);
340 if (end < start)
341 printf("end (%lx) < start (%lx)\n", end, start);
342#endif
343 }
344 if (!pcib_is_isa_mem(start) &&
345 (((start < sc->membase) || (end > sc->memlimit)) &&
346 ((start < sc->pmembase) || (end > sc->pmemlimit)))) {
347 if (bootverbose)
348 device_printf(dev,
349 "device %s%d requested unsupported memory range "
350 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
351 device_get_name(child), device_get_unit(child), start,
352 end, sc->membase, sc->memlimit, sc->pmembase,
353 sc->pmemlimit);
354#ifndef PCI_ALLOW_UNSUPPORTED_IO_RANGE
355 return(NULL);
356#endif
357 }
358 if (bootverbose)
359 device_printf(sc->dev, "device %s%d requested decoded memory range 0x%lx-0x%lx\n",
360 device_get_name(child), device_get_unit(child), start, end);
361 break;
362
363 default:
364 break;
365 }
366 }
367
368 /*
369 * Bridge is OK decoding this resource, so pass it up.
370 */
371 return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags));
372}
373
374/*
375 * PCIB interface.
376 */
377int
378pcib_maxslots(device_t dev)
379{
380 return(PCI_SLOTMAX);
381}
382
383/*
384 * Since we are a child of a PCI bus, its parent must support the pcib interface.
385 */
386u_int32_t
387pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
388{
389 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
390}
391
392void
393pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width)
394{
395 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
396}
397
398/*
399 * Route an interrupt across a PCI bridge.
400 */
401static int
402pcib_route_interrupt(device_t pcib, device_t dev, int pin)
403{
404 device_t bus;
405 int parent_intpin;
406 int intnum;
407
408 /*
409 *
410 * The PCI standard defines a swizzle of the child-side device/intpin to
411 * the parent-side intpin as follows.
412 *
413 * device = device on child bus
414 * child_intpin = intpin on child bus slot (0-3)
415 * parent_intpin = intpin on parent bus slot (0-3)
416 *
417 * parent_intpin = (device + child_intpin) % 4
418 */
419 parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4;
420
421 /*
422 * Our parent is a PCI bus. Its parent must export the pcib interface
423 * which includes the ability to route interrupts.
424 */
425 bus = device_get_parent(pcib);
426 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
427 if (PCI_INTERRUPT_VALID(intnum)) {
428 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
429 pci_get_slot(dev), 'A' + pin - 1, intnum);
430 }
431 return(intnum);
432}
|