1/*-
2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
|
32__FBSDID("$FreeBSD: head/sys/dev/pci/pci_pci.c 121307 2003-10-21 18:28:36Z silby $");
| 32__FBSDID("$FreeBSD: head/sys/dev/pci/pci_pci.c 124365 2004-01-11 06:52:31Z imp $");
|
33
34/*
35 * PCI:PCI bridge support.
36 */
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/kernel.h>
41#include <sys/bus.h>
42#include <machine/bus.h>
43#include <sys/rman.h>
44#include <sys/sysctl.h>
45
46#include <machine/resource.h>
47
48#include <dev/pci/pcivar.h>
49#include <dev/pci/pcireg.h>
50#include <dev/pci/pcib_private.h>
51
52#include "pcib_if.h"
53
54static int pcib_probe(device_t dev);
55
56static device_method_t pcib_methods[] = {
57 /* Device interface */
58 DEVMETHOD(device_probe, pcib_probe),
59 DEVMETHOD(device_attach, pcib_attach),
60 DEVMETHOD(device_shutdown, bus_generic_shutdown),
61 DEVMETHOD(device_suspend, bus_generic_suspend),
62 DEVMETHOD(device_resume, bus_generic_resume),
63
64 /* Bus interface */
65 DEVMETHOD(bus_print_child, bus_generic_print_child),
66 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
67 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
68 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
69 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
70 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
71 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
72 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
73 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
74
75 /* pcib interface */
76 DEVMETHOD(pcib_maxslots, pcib_maxslots),
77 DEVMETHOD(pcib_read_config, pcib_read_config),
78 DEVMETHOD(pcib_write_config, pcib_write_config),
79 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
80
81 { 0, 0 }
82};
83
84static driver_t pcib_driver = {
85 "pcib",
86 pcib_methods,
87 sizeof(struct pcib_softc),
88};
89
90devclass_t pcib_devclass;
91
92DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
93
94/*
| 33
34/*
35 * PCI:PCI bridge support.
36 */
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/kernel.h>
41#include <sys/bus.h>
42#include <machine/bus.h>
43#include <sys/rman.h>
44#include <sys/sysctl.h>
45
46#include <machine/resource.h>
47
48#include <dev/pci/pcivar.h>
49#include <dev/pci/pcireg.h>
50#include <dev/pci/pcib_private.h>
51
52#include "pcib_if.h"
53
54static int pcib_probe(device_t dev);
55
56static device_method_t pcib_methods[] = {
57 /* Device interface */
58 DEVMETHOD(device_probe, pcib_probe),
59 DEVMETHOD(device_attach, pcib_attach),
60 DEVMETHOD(device_shutdown, bus_generic_shutdown),
61 DEVMETHOD(device_suspend, bus_generic_suspend),
62 DEVMETHOD(device_resume, bus_generic_resume),
63
64 /* Bus interface */
65 DEVMETHOD(bus_print_child, bus_generic_print_child),
66 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
67 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
68 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
69 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
70 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
71 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
72 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
73 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
74
75 /* pcib interface */
76 DEVMETHOD(pcib_maxslots, pcib_maxslots),
77 DEVMETHOD(pcib_read_config, pcib_read_config),
78 DEVMETHOD(pcib_write_config, pcib_write_config),
79 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
80
81 { 0, 0 }
82};
83
84static driver_t pcib_driver = {
85 "pcib",
86 pcib_methods,
87 sizeof(struct pcib_softc),
88};
89
90devclass_t pcib_devclass;
91
92DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
93
94/*
|
95 * sysctl and tunable vars
96 */
97static int pci_allow_unsupported_io_range = 0;
98TUNABLE_INT("hw.pci.allow_unsupported_io_range",
99 (int *)&pci_allow_unsupported_io_range);
100SYSCTL_DECL(_hw_pci);
101SYSCTL_INT(_hw_pci, OID_AUTO, allow_unsupported_io_range, CTLFLAG_RDTUN,
102 &pci_allow_unsupported_io_range, 0,
103 "Allows the PCI Bridge to pass through an unsupported memory range "
104 "assigned by the BIOS.");
105
106/*
| |
107 * Generic device interface
108 */
109static int
110pcib_probe(device_t dev)
111{
112 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
113 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
114 device_set_desc(dev, "PCI-PCI bridge");
115 return(-10000);
116 }
117 return(ENXIO);
118}
119
120void
121pcib_attach_common(device_t dev)
122{
123 struct pcib_softc *sc;
124 uint8_t iolow;
125
126 sc = device_get_softc(dev);
127 sc->dev = dev;
128
129 /*
130 * Get current bridge configuration.
131 */
132 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
133 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
134 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
135 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
136 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
137 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
138
139 /*
140 * Determine current I/O decode.
141 */
142 if (sc->command & PCIM_CMD_PORTEN) {
143 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
144 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
145 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
146 pci_read_config(dev, PCIR_IOBASEL_1, 1));
147 } else {
148 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
149 }
150
151 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
152 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
153 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
154 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
155 } else {
156 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
157 }
158 }
159
160 /*
161 * Determine current memory decode.
162 */
163 if (sc->command & PCIM_CMD_MEMEN) {
164 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
165 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
166 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
167 pci_read_config(dev, PCIR_PMBASEL_1, 2));
168 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
169 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
170 }
171
172 /*
173 * Quirk handling.
174 */
175 switch (pci_get_devid(dev)) {
| 95 * Generic device interface
96 */
97static int
98pcib_probe(device_t dev)
99{
100 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
101 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
102 device_set_desc(dev, "PCI-PCI bridge");
103 return(-10000);
104 }
105 return(ENXIO);
106}
107
108void
109pcib_attach_common(device_t dev)
110{
111 struct pcib_softc *sc;
112 uint8_t iolow;
113
114 sc = device_get_softc(dev);
115 sc->dev = dev;
116
117 /*
118 * Get current bridge configuration.
119 */
120 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
121 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
122 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
123 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
124 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
125 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
126
127 /*
128 * Determine current I/O decode.
129 */
130 if (sc->command & PCIM_CMD_PORTEN) {
131 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
132 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
133 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
134 pci_read_config(dev, PCIR_IOBASEL_1, 1));
135 } else {
136 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
137 }
138
139 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
140 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
141 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
142 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
143 } else {
144 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
145 }
146 }
147
148 /*
149 * Determine current memory decode.
150 */
151 if (sc->command & PCIM_CMD_MEMEN) {
152 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
153 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
154 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
155 pci_read_config(dev, PCIR_PMBASEL_1, 2));
156 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
157 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
158 }
159
160 /*
161 * Quirk handling.
162 */
163 switch (pci_get_devid(dev)) {
|
176 case 0x12258086: /* Intel 82454KX/GX (Orion) */
| 164 case 0x12258086: /* Intel 82454KX/GX (Orion) */
|
177 {
178 uint8_t supbus;
179
180 supbus = pci_read_config(dev, 0x41, 1);
181 if (supbus != 0xff) {
182 sc->secbus = supbus + 1;
183 sc->subbus = supbus + 1;
184 }
| 165 {
166 uint8_t supbus;
167
168 supbus = pci_read_config(dev, 0x41, 1);
169 if (supbus != 0xff) {
170 sc->secbus = supbus + 1;
171 sc->subbus = supbus + 1;
172 }
|
| 173 break;
|
185 }
| 174 }
|
| 175
176 /*
177 * The i82380FB mobile docking controller is a PCI-PCI bridge,
178 * and it is a subtractive bridge. However, the ProgIf is wrong
179 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
180 * happen. There's also a Toshiba bridge that behaves this
181 * way.
182 */
183 case 0x124b8086: /* Intel 82380FB Mobile */
184 case 0x060513d7: /* Toshiba ???? */
185 sc->flags |= PCIB_SUBTRACTIVE;
|
186 break;
187 }
188
| 186 break;
187 }
188
|
| 189 /*
190 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
191 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
192 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
193 * This means they act as if they were subtractively decoding
194 * bridges and pass all transactions. Mark them and real ProgIf 1
195 * parts as subtractive.
196 */
197 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
198 pci_read_config(dev, PCIR_PROGIF, 1) == 1)
199 sc->flags |= PCIB_SUBTRACTIVE;
200
|
189 if (bootverbose) {
190 device_printf(dev, " secondary bus %d\n", sc->secbus);
191 device_printf(dev, " subordinate bus %d\n", sc->subbus);
192 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
193 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
194 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
| 201 if (bootverbose) {
202 device_printf(dev, " secondary bus %d\n", sc->secbus);
203 device_printf(dev, " subordinate bus %d\n", sc->subbus);
204 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
205 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
206 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
|
| 207 if (sc->flags & PCIB_SUBTRACTIVE)
208 device_printf(dev, " Subtractively decoded bridge.\n");
|
195 }
196
197 /*
198 * XXX If the secondary bus number is zero, we should assign a bus number
199 * since the BIOS hasn't, then initialise the bridge.
200 */
201
202 /*
203 * XXX If the subordinate bus number is less than the secondary bus number,
204 * we should pick a better value. One sensible alternative would be to
205 * pick 255; the only tradeoff here is that configuration transactions
206 * would be more widely routed than absolutely necessary.
207 */
208}
209
210int
211pcib_attach(device_t dev)
212{
213 struct pcib_softc *sc;
214 device_t child;
215
216 pcib_attach_common(dev);
217 sc = device_get_softc(dev);
218 if (sc->secbus != 0) {
219 child = device_add_child(dev, "pci", sc->secbus);
220 if (child != NULL)
221 return(bus_generic_attach(dev));
222 }
223
224 /* no secondary bus; we should have fixed this */
225 return(0);
226}
227
228int
229pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
230{
231 struct pcib_softc *sc = device_get_softc(dev);
232
233 switch (which) {
234 case PCIB_IVAR_BUS:
235 *result = sc->secbus;
236 return(0);
237 }
238 return(ENOENT);
239}
240
241int
242pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
243{
244 struct pcib_softc *sc = device_get_softc(dev);
245
246 switch (which) {
247 case PCIB_IVAR_BUS:
248 sc->secbus = value;
249 break;
250 }
251 return(ENOENT);
252}
253
254/*
| 209 }
210
211 /*
212 * XXX If the secondary bus number is zero, we should assign a bus number
213 * since the BIOS hasn't, then initialise the bridge.
214 */
215
216 /*
217 * XXX If the subordinate bus number is less than the secondary bus number,
218 * we should pick a better value. One sensible alternative would be to
219 * pick 255; the only tradeoff here is that configuration transactions
220 * would be more widely routed than absolutely necessary.
221 */
222}
223
224int
225pcib_attach(device_t dev)
226{
227 struct pcib_softc *sc;
228 device_t child;
229
230 pcib_attach_common(dev);
231 sc = device_get_softc(dev);
232 if (sc->secbus != 0) {
233 child = device_add_child(dev, "pci", sc->secbus);
234 if (child != NULL)
235 return(bus_generic_attach(dev));
236 }
237
238 /* no secondary bus; we should have fixed this */
239 return(0);
240}
241
242int
243pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
244{
245 struct pcib_softc *sc = device_get_softc(dev);
246
247 switch (which) {
248 case PCIB_IVAR_BUS:
249 *result = sc->secbus;
250 return(0);
251 }
252 return(ENOENT);
253}
254
255int
256pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
257{
258 struct pcib_softc *sc = device_get_softc(dev);
259
260 switch (which) {
261 case PCIB_IVAR_BUS:
262 sc->secbus = value;
263 break;
264 }
265 return(ENOENT);
266}
267
268/*
|
255 * Is this a decoded ISA I/O port address? Note, we need to do the mask that
256 * we do below because of the ISA alias addresses. I'm not 100% sure that
257 * this is correct. Maybe the bridge needs to be subtractive decode for
258 * this to work?
259 */
260static int
261pcib_is_isa_io(u_long start)
262{
263 if ((start & 0xfffUL) > 0x3ffUL || start == 0)
264 return (0);
265 return (1);
266}
267
268/*
269 * Is this a decoded ISA memory address?
270 */
271static int
272pcib_is_isa_mem(u_long start)
273{
274 if (start > 0xfffffUL || start == 0)
275 return (0);
276 return (1);
277}
278
279/*
| |
280 * Is the prefetch window open (eg, can we allocate memory in it?)
281 */
282static int
283pcib_is_prefetch_open(struct pcib_softc *sc)
284{
| 269 * Is the prefetch window open (eg, can we allocate memory in it?)
270 */
271static int
272pcib_is_prefetch_open(struct pcib_softc *sc)
273{
|
285 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
| 274 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
|
286}
287
288/*
289 * Is the nonprefetch window open (eg, can we allocate memory in it?)
290 */
291static int
292pcib_is_nonprefetch_open(struct pcib_softc *sc)
293{
| 275}
276
277/*
278 * Is the nonprefetch window open (eg, can we allocate memory in it?)
279 */
280static int
281pcib_is_nonprefetch_open(struct pcib_softc *sc)
282{
|
294 return (sc->membase > 0 && sc->membase < sc->memlimit);
| 283 return (sc->membase > 0 && sc->membase < sc->memlimit);
|
295}
296
297/*
298 * Is the io window open (eg, can we allocate ports in it?)
299 */
300static int
301pcib_is_io_open(struct pcib_softc *sc)
302{
| 284}
285
286/*
287 * Is the io window open (eg, can we allocate ports in it?)
288 */
289static int
290pcib_is_io_open(struct pcib_softc *sc)
291{
|
303 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
| 292 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
|
304}
305
306/*
307 * We have to trap resource allocation requests and ensure that the bridge
308 * is set up to, or capable of handling them.
309 */
310struct resource *
311pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
312 u_long start, u_long end, u_long count, u_int flags)
313{
| 293}
294
295/*
296 * We have to trap resource allocation requests and ensure that the bridge
297 * is set up to, or capable of handling them.
298 */
299struct resource *
300pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
301 u_long start, u_long end, u_long count, u_int flags)
302{
|
314 struct pcib_softc *sc = device_get_softc(dev);
315 int ok;
| 303 struct pcib_softc *sc = device_get_softc(dev);
304 int ok;
|
316
| 305
|
317 /*
318 * If this is a "default" allocation against this rid, we can't work
319 * out where it's coming from (we should actually never see these) so we
320 * just have to punt.
321 */
322 if ((start == 0) && (end == ~0)) {
323 device_printf(dev, "can't decode default resource id %d for %s%d, bypassing\n",
324 *rid, device_get_name(child), device_get_unit(child));
325 } else {
| |
326 /*
327 * Fail the allocation for this range if it's not supported.
328 */
329 switch (type) {
330 case SYS_RES_IOPORT:
| 306 /*
307 * Fail the allocation for this range if it's not supported.
308 */
309 switch (type) {
310 case SYS_RES_IOPORT:
|
331 ok = 1;
332 if (!pcib_is_isa_io(start)) {
| |
333 ok = 0;
| 311 ok = 0;
|
334 if (pcib_is_io_open(sc))
335 ok = (start >= sc->iobase && end <= sc->iolimit);
336 if (!pci_allow_unsupported_io_range) {
337 if (!ok) {
338 if (start < sc->iobase)
339 start = sc->iobase;
340 if (end > sc->iolimit)
341 end = sc->iolimit;
342 }
| 312 if (!pcib_is_io_open(sc))
313 break;
314 ok = (start >= sc->iobase && end <= sc->iolimit);
315 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
316 if (!ok) {
317 if (start < sc->iobase)
318 start = sc->iobase;
319 if (end > sc->iolimit)
320 end = sc->iolimit;
321 }
|
343 } else {
| 322 } else {
|
344 if (start < sc->iobase)
345 printf("start (%lx) < sc->iobase (%x)\n", start,
346 sc->iobase);
347 if (end > sc->iolimit)
348 printf("end (%lx) > sc->iolimit (%x)\n",
349 end, sc->iolimit);
350 if (end < start)
351 printf("end (%lx) < start (%lx)\n", end, start);
| 323 ok = 1;
324 if (start < sc->iobase && end > sc->iolimit) {
325 start = sc->iobase;
326 end = sc->iolimit;
327 }
328
|
352 }
| 329 }
|
353 }
354 if (end < start) {
355 start = 0;
356 end = 0;
357 ok = 0;
358 }
359 if (!ok) {
360 device_printf(dev, "device %s%d requested unsupported I/O "
361 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
362 device_get_name(child), device_get_unit(child), start, end,
363 sc->iobase, sc->iolimit);
364 return (NULL);
365 }
366 if (bootverbose)
367 device_printf(sc->dev, "device %s%d requested decoded I/O range 0x%lx-0x%lx\n",
368 device_get_name(child), device_get_unit(child), start, end);
369 break;
| 330 if (end < start) {
331 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", end, start);
332 start = 0;
333 end = 0;
334 ok = 0;
335 }
336 if (!ok) {
337 device_printf(dev, "device %s requested unsupported I/O "
338 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
339 device_get_nameunit(child), start, end,
340 sc->iobase, sc->iolimit);
341 return (NULL);
342 }
343 if (bootverbose)
344 device_printf(dev, "device %s requested decoded I/O range 0x%lx-0x%lx\n",
345 device_get_nameunit(child), start, end);
346 break;
|
370
371 case SYS_RES_MEMORY:
| 347
348 case SYS_RES_MEMORY:
|
372 ok = 1;
373 if (!pcib_is_isa_mem(start)) {
| |
374 ok = 0;
375 if (pcib_is_nonprefetch_open(sc))
| 349 ok = 0;
350 if (pcib_is_nonprefetch_open(sc))
|
376 ok = ok || (start >= sc->membase && end <= sc->memlimit);
| 351 ok = ok || (start >= sc->membase && end <= sc->memlimit);
|
377 if (pcib_is_prefetch_open(sc))
| 352 if (pcib_is_prefetch_open(sc))
|
378 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
379 if (!pci_allow_unsupported_io_range) {
380 if (!ok) {
381 ok = 1;
382 if (flags & RF_PREFETCHABLE) {
383 if (pcib_is_prefetch_open(sc)) {
384 if (start < sc->pmembase)
385 start = sc->pmembase;
386 if (end > sc->pmemlimit)
387 end = sc->pmemlimit;
388 } else {
389 ok = 0;
390 }
391 } else { /* non-prefetchable */
392 if (pcib_is_nonprefetch_open(sc)) {
393 if (start < sc->membase)
394 start = sc->membase;
395 if (end > sc->memlimit)
396 end = sc->memlimit;
397 } else {
398 ok = 0;
399 }
| 353 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
354 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
355 if (!ok) {
356 ok = 1;
357 if (flags & RF_PREFETCHABLE) {
358 if (pcib_is_prefetch_open(sc)) {
359 if (start < sc->pmembase)
360 start = sc->pmembase;
361 if (end > sc->pmemlimit)
362 end = sc->pmemlimit;
363 } else {
364 ok = 0;
365 }
366 } else { /* non-prefetchable */
367 if (pcib_is_nonprefetch_open(sc)) {
368 if (start < sc->membase)
369 start = sc->membase;
370 if (end > sc->memlimit)
371 end = sc->memlimit;
372 } else {
373 ok = 0;
374 }
375 }
|
400 }
| 376 }
|
401 }
| |
402 } else if (!ok) {
| 377 } else if (!ok) {
|
403 ok = 1; /* pci_allow_unsupported_ranges -> always ok */
404 if (pcib_is_nonprefetch_open(sc)) {
405 if (start < sc->membase)
406 printf("start (%lx) < sc->membase (%x)\n",
407 start, sc->membase);
408 if (end > sc->memlimit)
409 printf("end (%lx) > sc->memlimit (%x)\n",
410 end, sc->memlimit);
411 }
412 if (pcib_is_prefetch_open(sc)) {
413 if (start < sc->pmembase)
414 printf("start (%lx) < sc->pmembase (%x)\n",
415 start, sc->pmembase);
416 if (end > sc->pmemlimit)
417 printf("end (%lx) > sc->pmemlimit (%x)\n",
418 end, sc->memlimit);
419 }
420 if (end < start)
421 printf("end (%lx) < start (%lx)\n", end, start);
| 378 ok = 1; /* subtractive bridge: always ok */
379 if (pcib_is_nonprefetch_open(sc)) {
380 if (start < sc->membase && end > sc->memlimit) {
381 start = sc->membase;
382 end = sc->memlimit;
383 }
384 }
385 if (pcib_is_prefetch_open(sc)) {
386 if (start < sc->pmembase && end > sc->pmemlimit) {
387 start = sc->pmembase;
388 end = sc->pmemlimit;
389 }
390 }
|
422 }
| 391 }
|
423 }
424 if (end < start) {
425 start = 0;
426 end = 0;
427 ok = 0;
428 }
429 if (!ok && bootverbose)
430 device_printf(dev,
431 "device %s%d requested unsupported memory range "
432 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
433 device_get_name(child), device_get_unit(child), start,
434 end, sc->membase, sc->memlimit, sc->pmembase,
435 sc->pmemlimit);
436 if (!ok)
437 return (NULL);
438 if (bootverbose)
439 device_printf(sc->dev, "device %s%d requested decoded memory range 0x%lx-0x%lx\n",
440 device_get_name(child), device_get_unit(child), start, end);
441 break;
| 392 if (end < start) {
393 device_printf(dev, "memory: end (%lx) < start (%lx)\n", end, start);
394 start = 0;
395 end = 0;
396 ok = 0;
397 }
398 if (!ok && bootverbose)
399 device_printf(dev,
400 "device %s requested unsupported memory range "
401 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
402 device_get_nameunit(child), start, end,
403 sc->membase, sc->memlimit, sc->pmembase,
404 sc->pmemlimit);
405 if (!ok)
406 return (NULL);
407 if (bootverbose)
408 device_printf(dev,"device %s requested decoded memory range 0x%lx-0x%lx\n",
409 device_get_nameunit(child), start, end);
410 break;
|
442
443 default:
| 411
412 default:
|
444 break;
| 413 break;
|
445 }
| 414 }
|
446 }
447
448 /*
449 * Bridge is OK decoding this resource, so pass it up.
450 */
451 return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags));
| 415 /*
416 * Bridge is OK decoding this resource, so pass it up.
417 */
418 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags));
|
452}
453
454/*
455 * PCIB interface.
456 */
457int
458pcib_maxslots(device_t dev)
459{
460 return(PCI_SLOTMAX);
461}
462
463/*
464 * Since we are a child of a PCI bus, its parent must support the pcib interface.
465 */
466uint32_t
467pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
468{
469 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
470}
471
472void
473pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width)
474{
475 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
476}
477
478/*
479 * Route an interrupt across a PCI bridge.
480 */
481int
482pcib_route_interrupt(device_t pcib, device_t dev, int pin)
483{
484 device_t bus;
485 int parent_intpin;
486 int intnum;
487
488 /*
489 *
490 * The PCI standard defines a swizzle of the child-side device/intpin to
491 * the parent-side intpin as follows.
492 *
493 * device = device on child bus
494 * child_intpin = intpin on child bus slot (0-3)
495 * parent_intpin = intpin on parent bus slot (0-3)
496 *
497 * parent_intpin = (device + child_intpin) % 4
498 */
499 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
500
501 /*
502 * Our parent is a PCI bus. Its parent must export the pcib interface
503 * which includes the ability to route interrupts.
504 */
505 bus = device_get_parent(pcib);
506 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
507 if (PCI_INTERRUPT_VALID(intnum)) {
508 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
509 pci_get_slot(dev), 'A' + pin - 1, intnum);
510 }
511 return(intnum);
512}
513
514/*
515 * Try to read the bus number of a host-PCI bridge using appropriate config
516 * registers.
517 */
518int
519host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
520 uint8_t *busnum)
521{
522 uint32_t id;
523
524 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
525 if (id == 0xffffffff)
526 return (0);
527
528 switch (id) {
529 case 0x12258086:
530 /* Intel 824?? */
531 /* XXX This is a guess */
532 /* *busnum = read_config(bus, slot, func, 0x41, 1); */
533 *busnum = bus;
534 break;
535 case 0x84c48086:
536 /* Intel 82454KX/GX (Orion) */
537 *busnum = read_config(bus, slot, func, 0x4a, 1);
538 break;
539 case 0x84ca8086:
540 /*
541 * For the 450nx chipset, there is a whole bundle of
542 * things pretending to be host bridges. The MIOC will
543 * be seen first and isn't really a pci bridge (the
544 * actual busses are attached to the PXB's). We need to
545 * read the registers of the MIOC to figure out the
546 * bus numbers for the PXB channels.
547 *
548 * Since the MIOC doesn't have a pci bus attached, we
549 * pretend it wasn't there.
550 */
551 return (0);
552 case 0x84cb8086:
553 switch (slot) {
554 case 0x12:
555 /* Intel 82454NX PXB#0, Bus#A */
556 *busnum = read_config(bus, 0x10, func, 0xd0, 1);
557 break;
558 case 0x13:
559 /* Intel 82454NX PXB#0, Bus#B */
560 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
561 break;
562 case 0x14:
563 /* Intel 82454NX PXB#1, Bus#A */
564 *busnum = read_config(bus, 0x10, func, 0xd3, 1);
565 break;
566 case 0x15:
567 /* Intel 82454NX PXB#1, Bus#B */
568 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
569 break;
570 }
571 break;
572
573 /* ServerWorks -- vendor 0x1166 */
574 case 0x00051166:
575 case 0x00061166:
576 case 0x00081166:
577 case 0x00091166:
578 case 0x00101166:
579 case 0x00111166:
580 case 0x00171166:
581 case 0x01011166:
582 case 0x010f1014:
583 case 0x02011166:
584 case 0x03021014:
585 *busnum = read_config(bus, slot, func, 0x44, 1);
586 break;
587 default:
588 /* Don't know how to read bus number. */
589 return 0;
590 }
591
592 return 1;
593}
| 419}
420
421/*
422 * PCIB interface.
423 */
424int
425pcib_maxslots(device_t dev)
426{
427 return(PCI_SLOTMAX);
428}
429
430/*
431 * Since we are a child of a PCI bus, its parent must support the pcib interface.
432 */
433uint32_t
434pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
435{
436 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
437}
438
439void
440pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width)
441{
442 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
443}
444
445/*
446 * Route an interrupt across a PCI bridge.
447 */
448int
449pcib_route_interrupt(device_t pcib, device_t dev, int pin)
450{
451 device_t bus;
452 int parent_intpin;
453 int intnum;
454
455 /*
456 *
457 * The PCI standard defines a swizzle of the child-side device/intpin to
458 * the parent-side intpin as follows.
459 *
460 * device = device on child bus
461 * child_intpin = intpin on child bus slot (0-3)
462 * parent_intpin = intpin on parent bus slot (0-3)
463 *
464 * parent_intpin = (device + child_intpin) % 4
465 */
466 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
467
468 /*
469 * Our parent is a PCI bus. Its parent must export the pcib interface
470 * which includes the ability to route interrupts.
471 */
472 bus = device_get_parent(pcib);
473 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
474 if (PCI_INTERRUPT_VALID(intnum)) {
475 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
476 pci_get_slot(dev), 'A' + pin - 1, intnum);
477 }
478 return(intnum);
479}
480
481/*
482 * Try to read the bus number of a host-PCI bridge using appropriate config
483 * registers.
484 */
485int
486host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
487 uint8_t *busnum)
488{
489 uint32_t id;
490
491 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
492 if (id == 0xffffffff)
493 return (0);
494
495 switch (id) {
496 case 0x12258086:
497 /* Intel 824?? */
498 /* XXX This is a guess */
499 /* *busnum = read_config(bus, slot, func, 0x41, 1); */
500 *busnum = bus;
501 break;
502 case 0x84c48086:
503 /* Intel 82454KX/GX (Orion) */
504 *busnum = read_config(bus, slot, func, 0x4a, 1);
505 break;
506 case 0x84ca8086:
507 /*
508 * For the 450nx chipset, there is a whole bundle of
509 * things pretending to be host bridges. The MIOC will
510 * be seen first and isn't really a pci bridge (the
511 * actual busses are attached to the PXB's). We need to
512 * read the registers of the MIOC to figure out the
513 * bus numbers for the PXB channels.
514 *
515 * Since the MIOC doesn't have a pci bus attached, we
516 * pretend it wasn't there.
517 */
518 return (0);
519 case 0x84cb8086:
520 switch (slot) {
521 case 0x12:
522 /* Intel 82454NX PXB#0, Bus#A */
523 *busnum = read_config(bus, 0x10, func, 0xd0, 1);
524 break;
525 case 0x13:
526 /* Intel 82454NX PXB#0, Bus#B */
527 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
528 break;
529 case 0x14:
530 /* Intel 82454NX PXB#1, Bus#A */
531 *busnum = read_config(bus, 0x10, func, 0xd3, 1);
532 break;
533 case 0x15:
534 /* Intel 82454NX PXB#1, Bus#B */
535 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
536 break;
537 }
538 break;
539
540 /* ServerWorks -- vendor 0x1166 */
541 case 0x00051166:
542 case 0x00061166:
543 case 0x00081166:
544 case 0x00091166:
545 case 0x00101166:
546 case 0x00111166:
547 case 0x00171166:
548 case 0x01011166:
549 case 0x010f1014:
550 case 0x02011166:
551 case 0x03021014:
552 *busnum = read_config(bus, slot, func, 0x44, 1);
553 break;
554 default:
555 /* Don't know how to read bus number. */
556 return 0;
557 }
558
559 return 1;
560}
|