1/*-
2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
--- 13 unchanged lines hidden (view full) ---
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD: head/sys/dev/pci/pci_pci.c 94573 2002-04-13 05:52:35Z imp $
31 */
32
33/*
34 * PCI:PCI bridge support.
35 */
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/kernel.h>
40#include <sys/bus.h>
41
42#include <machine/resource.h>
43
44#include <pci/pcivar.h>
45#include <pci/pcireg.h>
46
47#include "pcib_if.h"
48#include "opt_pci.h"
49
50/*
51 * Bridge-specific data.
52 */
53struct pcib_softc
54{
55 device_t dev;
56 u_int16_t command; /* command register */
57 u_int8_t secbus; /* secondary bus number */
58 u_int8_t subbus; /* subordinate bus number */
59 pci_addr_t pmembase; /* base address of prefetchable memory */
60 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
61 pci_addr_t membase; /* base address of memory window */
62 pci_addr_t memlimit; /* topmost address of memory window */
63 u_int32_t iobase; /* base address of port window */
64 u_int32_t iolimit; /* topmost address of port window */
65 u_int16_t secstat; /* secondary bus status register */
66 u_int16_t bridgectl; /* bridge control register */
67 u_int8_t seclat; /* secondary bus latency timer */
68};
69
70static int pcib_probe(device_t dev);
71static int pcib_attach(device_t dev);
72static int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result);
73static int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value);
74static struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
75 u_long start, u_long end, u_long count, u_int flags);
76static int pcib_maxslots(device_t dev);
77static u_int32_t pcib_read_config(device_t dev, int b, int s, int f, int reg, int width);
78static void pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width);
79static int pcib_route_interrupt(device_t pcib, device_t dev, int pin);
80
81static device_method_t pcib_methods[] = {
82 /* Device interface */
83 DEVMETHOD(device_probe, pcib_probe),
84 DEVMETHOD(device_attach, pcib_attach),
85 DEVMETHOD(device_shutdown, bus_generic_shutdown),
86 DEVMETHOD(device_suspend, bus_generic_suspend),
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107};
108
109static driver_t pcib_driver = {
110 "pcib",
111 pcib_methods,
112 sizeof(struct pcib_softc),
113};
114
115static devclass_t pcib_devclass;
116
117DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
118
119/*
120 * Generic device interface
121 */
122static int
123pcib_probe(device_t dev)
124{
125 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
126 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
127 device_set_desc(dev, "PCI-PCI bridge");
128 return(-10000);
129 }
130 return(ENXIO);
131}
132
133static int
134pcib_attach(device_t dev)
135{
136 struct pcib_softc *sc;
137 device_t child;
138 u_int8_t iolow;
139
140 sc = device_get_softc(dev);
141 sc->dev = dev;
142
143 /*
144 * Get current bridge configuration.
145 */
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214 */
215
216 /*
217 * XXX If the subordinate bus number is less than the secondary bus number,
218 * we should pick a better value. One sensible alternative would be to
219 * pick 255; the only tradeoff here is that configuration transactions
220 * would be more widely routed than absolutely necessary.
221 */
222
223 if (sc->secbus != 0) {
224 child = device_add_child(dev, "pci", -1);
225 if (child != NULL)
226 return(bus_generic_attach(dev));
227 }
228
229 /* no secondary bus; we should have fixed this */
230 return(0);
231}
232
233static int
234pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
235{
236 struct pcib_softc *sc = device_get_softc(dev);
237
238 switch (which) {
239 case PCIB_IVAR_BUS:
240 *result = sc->secbus;
241 return(0);
242 }
243 return(ENOENT);
244}
245
246static int
247pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
248{
249 struct pcib_softc *sc = device_get_softc(dev);
250
251 switch (which) {
252 case PCIB_IVAR_BUS:
253 sc->secbus = value;
254 break;
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279 return (0);
280 return (1);
281}
282
283/*
284 * We have to trap resource allocation requests and ensure that the bridge
285 * is set up to, or capable of handling them.
286 */
287static struct resource *
288pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
289 u_long start, u_long end, u_long count, u_int flags)
290{
291 struct pcib_softc *sc = device_get_softc(dev);
292
293 /*
294 * If this is a "default" allocation against this rid, we can't work
295 * out where it's coming from (we should actually never see these) so we
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388 * Bridge is OK decoding this resource, so pass it up.
389 */
390 return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags));
391}
392
393/*
394 * PCIB interface.
395 */
396static int
397pcib_maxslots(device_t dev)
398{
399 return(PCI_SLOTMAX);
400}
401
402/*
403 * Since we are a child of a PCI bus, its parent must support the pcib interface.
404 */
405static u_int32_t
406pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
407{
408 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
409}
410
411static void
412pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width)
413{
414 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
415}
416
417/*
418 * Route an interrupt across a PCI bridge.
419 */
--- 32 unchanged lines hidden ---
2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
--- 13 unchanged lines hidden (view full) ---
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD: head/sys/dev/pci/pci_pci.c 94573 2002-04-13 05:52:35Z imp $
31 */
32
33/*
34 * PCI:PCI bridge support.
35 */
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/kernel.h>
40#include <sys/bus.h>
41
42#include <machine/resource.h>
43
44#include <pci/pcivar.h>
45#include <pci/pcireg.h>
46
47#include "pcib_if.h"
48#include "opt_pci.h"
49
50/*
51 * Bridge-specific data.
52 */
53struct pcib_softc
54{
55 device_t dev;
56 u_int16_t command; /* command register */
57 u_int8_t secbus; /* secondary bus number */
58 u_int8_t subbus; /* subordinate bus number */
59 pci_addr_t pmembase; /* base address of prefetchable memory */
60 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
61 pci_addr_t membase; /* base address of memory window */
62 pci_addr_t memlimit; /* topmost address of memory window */
63 u_int32_t iobase; /* base address of port window */
64 u_int32_t iolimit; /* topmost address of port window */
65 u_int16_t secstat; /* secondary bus status register */
66 u_int16_t bridgectl; /* bridge control register */
67 u_int8_t seclat; /* secondary bus latency timer */
68};
69
70static int pcib_probe(device_t dev);
71static int pcib_attach(device_t dev);
72static int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result);
73static int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value);
74static struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
75 u_long start, u_long end, u_long count, u_int flags);
76static int pcib_maxslots(device_t dev);
77static u_int32_t pcib_read_config(device_t dev, int b, int s, int f, int reg, int width);
78static void pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width);
79static int pcib_route_interrupt(device_t pcib, device_t dev, int pin);
80
81static device_method_t pcib_methods[] = {
82 /* Device interface */
83 DEVMETHOD(device_probe, pcib_probe),
84 DEVMETHOD(device_attach, pcib_attach),
85 DEVMETHOD(device_shutdown, bus_generic_shutdown),
86 DEVMETHOD(device_suspend, bus_generic_suspend),
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107};
108
109static driver_t pcib_driver = {
110 "pcib",
111 pcib_methods,
112 sizeof(struct pcib_softc),
113};
114
115static devclass_t pcib_devclass;
116
117DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
118
119/*
120 * Generic device interface
121 */
122static int
123pcib_probe(device_t dev)
124{
125 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
126 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
127 device_set_desc(dev, "PCI-PCI bridge");
128 return(-10000);
129 }
130 return(ENXIO);
131}
132
133static int
134pcib_attach(device_t dev)
135{
136 struct pcib_softc *sc;
137 device_t child;
138 u_int8_t iolow;
139
140 sc = device_get_softc(dev);
141 sc->dev = dev;
142
143 /*
144 * Get current bridge configuration.
145 */
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214 */
215
216 /*
217 * XXX If the subordinate bus number is less than the secondary bus number,
218 * we should pick a better value. One sensible alternative would be to
219 * pick 255; the only tradeoff here is that configuration transactions
220 * would be more widely routed than absolutely necessary.
221 */
222
223 if (sc->secbus != 0) {
224 child = device_add_child(dev, "pci", -1);
225 if (child != NULL)
226 return(bus_generic_attach(dev));
227 }
228
229 /* no secondary bus; we should have fixed this */
230 return(0);
231}
232
233static int
234pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
235{
236 struct pcib_softc *sc = device_get_softc(dev);
237
238 switch (which) {
239 case PCIB_IVAR_BUS:
240 *result = sc->secbus;
241 return(0);
242 }
243 return(ENOENT);
244}
245
246static int
247pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
248{
249 struct pcib_softc *sc = device_get_softc(dev);
250
251 switch (which) {
252 case PCIB_IVAR_BUS:
253 sc->secbus = value;
254 break;
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279 return (0);
280 return (1);
281}
282
283/*
284 * We have to trap resource allocation requests and ensure that the bridge
285 * is set up to, or capable of handling them.
286 */
287static struct resource *
288pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
289 u_long start, u_long end, u_long count, u_int flags)
290{
291 struct pcib_softc *sc = device_get_softc(dev);
292
293 /*
294 * If this is a "default" allocation against this rid, we can't work
295 * out where it's coming from (we should actually never see these) so we
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388 * Bridge is OK decoding this resource, so pass it up.
389 */
390 return(bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags));
391}
392
393/*
394 * PCIB interface.
395 */
396static int
397pcib_maxslots(device_t dev)
398{
399 return(PCI_SLOTMAX);
400}
401
402/*
403 * Since we are a child of a PCI bus, its parent must support the pcib interface.
404 */
405static u_int32_t
406pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
407{
408 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
409}
410
411static void
412pcib_write_config(device_t dev, int b, int s, int f, int reg, u_int32_t val, int width)
413{
414 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
415}
416
417/*
418 * Route an interrupt across a PCI bridge.
419 */
--- 32 unchanged lines hidden ---