337/* Find a device_t by bus/slot/function in domain 0 */
338
339device_t
340pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
341{
342
343 return (pci_find_dbsf(0, bus, slot, func));
344}
345
346/* Find a device_t by domain/bus/slot/function */
347
348device_t
349pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
350{
351 struct pci_devinfo *dinfo;
352
353 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
354 if ((dinfo->cfg.domain == domain) &&
355 (dinfo->cfg.bus == bus) &&
356 (dinfo->cfg.slot == slot) &&
357 (dinfo->cfg.func == func)) {
358 return (dinfo->cfg.dev);
359 }
360 }
361
362 return (NULL);
363}
364
365/* Find a device_t by vendor/device ID */
366
367device_t
368pci_find_device(uint16_t vendor, uint16_t device)
369{
370 struct pci_devinfo *dinfo;
371
372 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
373 if ((dinfo->cfg.vendor == vendor) &&
374 (dinfo->cfg.device == device)) {
375 return (dinfo->cfg.dev);
376 }
377 }
378
379 return (NULL);
380}
381
382device_t
383pci_find_class(uint8_t class, uint8_t subclass)
384{
385 struct pci_devinfo *dinfo;
386
387 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
388 if (dinfo->cfg.baseclass == class &&
389 dinfo->cfg.subclass == subclass) {
390 return (dinfo->cfg.dev);
391 }
392 }
393
394 return (NULL);
395}
396
397static int
398pci_printf(pcicfgregs *cfg, const char *fmt, ...)
399{
400 va_list ap;
401 int retval;
402
403 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot,
404 cfg->func);
405 va_start(ap, fmt);
406 retval += vprintf(fmt, ap);
407 va_end(ap);
408 return (retval);
409}
410
411/* return base address of memory or port map */
412
413static pci_addr_t
414pci_mapbase(uint64_t mapreg)
415{
416
417 if (PCI_BAR_MEM(mapreg))
418 return (mapreg & PCIM_BAR_MEM_BASE);
419 else
420 return (mapreg & PCIM_BAR_IO_BASE);
421}
422
423/* return map type of memory or port map */
424
425static const char *
426pci_maptype(uint64_t mapreg)
427{
428
429 if (PCI_BAR_IO(mapreg))
430 return ("I/O Port");
431 if (mapreg & PCIM_BAR_MEM_PREFETCH)
432 return ("Prefetchable Memory");
433 return ("Memory");
434}
435
436/* return log2 of map size decoded for memory or port map */
437
438static int
439pci_mapsize(uint64_t testval)
440{
441 int ln2size;
442
443 testval = pci_mapbase(testval);
444 ln2size = 0;
445 if (testval != 0) {
446 while ((testval & 1) == 0)
447 {
448 ln2size++;
449 testval >>= 1;
450 }
451 }
452 return (ln2size);
453}
454
455/* return base address of device ROM */
456
457static pci_addr_t
458pci_rombase(uint64_t mapreg)
459{
460
461 return (mapreg & PCIM_BIOS_ADDR_MASK);
462}
463
464/* return log2 of map size decided for device ROM */
465
466static int
467pci_romsize(uint64_t testval)
468{
469 int ln2size;
470
471 testval = pci_rombase(testval);
472 ln2size = 0;
473 if (testval != 0) {
474 while ((testval & 1) == 0)
475 {
476 ln2size++;
477 testval >>= 1;
478 }
479 }
480 return (ln2size);
481}
482
483/* return log2 of address range supported by map register */
484
485static int
486pci_maprange(uint64_t mapreg)
487{
488 int ln2range = 0;
489
490 if (PCI_BAR_IO(mapreg))
491 ln2range = 32;
492 else
493 switch (mapreg & PCIM_BAR_MEM_TYPE) {
494 case PCIM_BAR_MEM_32:
495 ln2range = 32;
496 break;
497 case PCIM_BAR_MEM_1MB:
498 ln2range = 20;
499 break;
500 case PCIM_BAR_MEM_64:
501 ln2range = 64;
502 break;
503 }
504 return (ln2range);
505}
506
507/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
508
509static void
510pci_fixancient(pcicfgregs *cfg)
511{
512 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
513 return;
514
515 /* PCI to PCI bridges use header type 1 */
516 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
517 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
518}
519
520/* extract header type specific config data */
521
522static void
523pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
524{
525#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
526 switch (cfg->hdrtype & PCIM_HDRTYPE) {
527 case PCIM_HDRTYPE_NORMAL:
528 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
529 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
530 cfg->nummaps = PCI_MAXMAPS_0;
531 break;
532 case PCIM_HDRTYPE_BRIDGE:
533 cfg->nummaps = PCI_MAXMAPS_1;
534 break;
535 case PCIM_HDRTYPE_CARDBUS:
536 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
537 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
538 cfg->nummaps = PCI_MAXMAPS_2;
539 break;
540 }
541#undef REG
542}
543
544/* read configuration header into pcicfgregs structure */
545struct pci_devinfo *
546pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
547{
548#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
549 pcicfgregs *cfg = NULL;
550 struct pci_devinfo *devlist_entry;
551 struct devlist *devlist_head;
552
553 devlist_head = &pci_devq;
554
555 devlist_entry = NULL;
556
557 if (REG(PCIR_DEVVENDOR, 4) != 0xfffffffful) {
558 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
559 if (devlist_entry == NULL)
560 return (NULL);
561
562 cfg = &devlist_entry->cfg;
563
564 cfg->domain = d;
565 cfg->bus = b;
566 cfg->slot = s;
567 cfg->func = f;
568 cfg->vendor = REG(PCIR_VENDOR, 2);
569 cfg->device = REG(PCIR_DEVICE, 2);
570 cfg->cmdreg = REG(PCIR_COMMAND, 2);
571 cfg->statreg = REG(PCIR_STATUS, 2);
572 cfg->baseclass = REG(PCIR_CLASS, 1);
573 cfg->subclass = REG(PCIR_SUBCLASS, 1);
574 cfg->progif = REG(PCIR_PROGIF, 1);
575 cfg->revid = REG(PCIR_REVID, 1);
576 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
577 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
578 cfg->lattimer = REG(PCIR_LATTIMER, 1);
579 cfg->intpin = REG(PCIR_INTPIN, 1);
580 cfg->intline = REG(PCIR_INTLINE, 1);
581
582 cfg->mingnt = REG(PCIR_MINGNT, 1);
583 cfg->maxlat = REG(PCIR_MAXLAT, 1);
584
585 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
586 cfg->hdrtype &= ~PCIM_MFDEV;
587 STAILQ_INIT(&cfg->maps);
588
589 pci_fixancient(cfg);
590 pci_hdrtypedata(pcib, b, s, f, cfg);
591
592 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
593 pci_read_cap(pcib, cfg);
594
595 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
596
597 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
598 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
599 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
600 devlist_entry->conf.pc_sel.pc_func = cfg->func;
601 devlist_entry->conf.pc_hdr = cfg->hdrtype;
602
603 devlist_entry->conf.pc_subvendor = cfg->subvendor;
604 devlist_entry->conf.pc_subdevice = cfg->subdevice;
605 devlist_entry->conf.pc_vendor = cfg->vendor;
606 devlist_entry->conf.pc_device = cfg->device;
607
608 devlist_entry->conf.pc_class = cfg->baseclass;
609 devlist_entry->conf.pc_subclass = cfg->subclass;
610 devlist_entry->conf.pc_progif = cfg->progif;
611 devlist_entry->conf.pc_revid = cfg->revid;
612
613 pci_numdevs++;
614 pci_generation++;
615 }
616 return (devlist_entry);
617#undef REG
618}
619
620static void
621pci_read_cap(device_t pcib, pcicfgregs *cfg)
622{
623#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
624#define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
625#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
626 uint64_t addr;
627#endif
628 uint32_t val;
629 int ptr, nextptr, ptrptr;
630
631 switch (cfg->hdrtype & PCIM_HDRTYPE) {
632 case PCIM_HDRTYPE_NORMAL:
633 case PCIM_HDRTYPE_BRIDGE:
634 ptrptr = PCIR_CAP_PTR;
635 break;
636 case PCIM_HDRTYPE_CARDBUS:
637 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
638 break;
639 default:
640 return; /* no extended capabilities support */
641 }
642 nextptr = REG(ptrptr, 1); /* sanity check? */
643
644 /*
645 * Read capability entries.
646 */
647 while (nextptr != 0) {
648 /* Sanity check */
649 if (nextptr > 255) {
650 printf("illegal PCI extended capability offset %d\n",
651 nextptr);
652 return;
653 }
654 /* Find the next entry */
655 ptr = nextptr;
656 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
657
658 /* Process this entry */
659 switch (REG(ptr + PCICAP_ID, 1)) {
660 case PCIY_PMG: /* PCI power management */
661 if (cfg->pp.pp_cap == 0) {
662 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
663 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
664 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE;
665 if ((nextptr - ptr) > PCIR_POWER_DATA)
666 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
667 }
668 break;
669 case PCIY_HT: /* HyperTransport */
670 /* Determine HT-specific capability type. */
671 val = REG(ptr + PCIR_HT_COMMAND, 2);
672
673 if ((val & 0xe000) == PCIM_HTCAP_SLAVE)
674 cfg->ht.ht_slave = ptr;
675
676#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
677 switch (val & PCIM_HTCMD_CAP_MASK) {
678 case PCIM_HTCAP_MSI_MAPPING:
679 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
680 /* Sanity check the mapping window. */
681 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
682 4);
683 addr <<= 32;
684 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
685 4);
686 if (addr != MSI_INTEL_ADDR_BASE)
687 device_printf(pcib,
688 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
689 cfg->domain, cfg->bus,
690 cfg->slot, cfg->func,
691 (long long)addr);
692 } else
693 addr = MSI_INTEL_ADDR_BASE;
694
695 cfg->ht.ht_msimap = ptr;
696 cfg->ht.ht_msictrl = val;
697 cfg->ht.ht_msiaddr = addr;
698 break;
699 }
700#endif
701 break;
702 case PCIY_MSI: /* PCI MSI */
703 cfg->msi.msi_location = ptr;
704 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
705 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
706 PCIM_MSICTRL_MMC_MASK)>>1);
707 break;
708 case PCIY_MSIX: /* PCI MSI-X */
709 cfg->msix.msix_location = ptr;
710 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
711 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
712 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
713 val = REG(ptr + PCIR_MSIX_TABLE, 4);
714 cfg->msix.msix_table_bar = PCIR_BAR(val &
715 PCIM_MSIX_BIR_MASK);
716 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
717 val = REG(ptr + PCIR_MSIX_PBA, 4);
718 cfg->msix.msix_pba_bar = PCIR_BAR(val &
719 PCIM_MSIX_BIR_MASK);
720 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
721 break;
722 case PCIY_VPD: /* PCI Vital Product Data */
723 cfg->vpd.vpd_reg = ptr;
724 break;
725 case PCIY_SUBVENDOR:
726 /* Should always be true. */
727 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
728 PCIM_HDRTYPE_BRIDGE) {
729 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
730 cfg->subvendor = val & 0xffff;
731 cfg->subdevice = val >> 16;
732 }
733 break;
734 case PCIY_PCIX: /* PCI-X */
735 /*
736 * Assume we have a PCI-X chipset if we have
737 * at least one PCI-PCI bridge with a PCI-X
738 * capability. Note that some systems with
739 * PCI-express or HT chipsets might match on
740 * this check as well.
741 */
742 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
743 PCIM_HDRTYPE_BRIDGE)
744 pcix_chipset = 1;
745 cfg->pcix.pcix_location = ptr;
746 break;
747 case PCIY_EXPRESS: /* PCI-express */
748 /*
749 * Assume we have a PCI-express chipset if we have
750 * at least one PCI-express device.
751 */
752 pcie_chipset = 1;
753 cfg->pcie.pcie_location = ptr;
754 val = REG(ptr + PCIER_FLAGS, 2);
755 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE;
756 break;
757 default:
758 break;
759 }
760 }
761
762#if defined(__powerpc__)
763 /*
764 * Enable the MSI mapping window for all HyperTransport
765 * slaves. PCI-PCI bridges have their windows enabled via
766 * PCIB_MAP_MSI().
767 */
768 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
769 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
770 device_printf(pcib,
771 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n",
772 cfg->domain, cfg->bus, cfg->slot, cfg->func);
773 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
774 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
775 2);
776 }
777#endif
778/* REG and WREG use carry through to next functions */
779}
780
781/*
782 * PCI Vital Product Data
783 */
784
785#define PCI_VPD_TIMEOUT 1000000
786
787static int
788pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
789{
790 int count = PCI_VPD_TIMEOUT;
791
792 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
793
794 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
795
796 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
797 if (--count < 0)
798 return (ENXIO);
799 DELAY(1); /* limit looping */
800 }
801 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
802
803 return (0);
804}
805
806#if 0
807static int
808pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
809{
810 int count = PCI_VPD_TIMEOUT;
811
812 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
813
814 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
815 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
816 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
817 if (--count < 0)
818 return (ENXIO);
819 DELAY(1); /* limit looping */
820 }
821
822 return (0);
823}
824#endif
825
826#undef PCI_VPD_TIMEOUT
827
828struct vpd_readstate {
829 device_t pcib;
830 pcicfgregs *cfg;
831 uint32_t val;
832 int bytesinval;
833 int off;
834 uint8_t cksum;
835};
836
837static int
838vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
839{
840 uint32_t reg;
841 uint8_t byte;
842
843 if (vrs->bytesinval == 0) {
844 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
845 return (ENXIO);
846 vrs->val = le32toh(reg);
847 vrs->off += 4;
848 byte = vrs->val & 0xff;
849 vrs->bytesinval = 3;
850 } else {
851 vrs->val = vrs->val >> 8;
852 byte = vrs->val & 0xff;
853 vrs->bytesinval--;
854 }
855
856 vrs->cksum += byte;
857 *data = byte;
858 return (0);
859}
860
861static void
862pci_read_vpd(device_t pcib, pcicfgregs *cfg)
863{
864 struct vpd_readstate vrs;
865 int state;
866 int name;
867 int remain;
868 int i;
869 int alloc, off; /* alloc/off for RO/W arrays */
870 int cksumvalid;
871 int dflen;
872 uint8_t byte;
873 uint8_t byte2;
874
875 /* init vpd reader */
876 vrs.bytesinval = 0;
877 vrs.off = 0;
878 vrs.pcib = pcib;
879 vrs.cfg = cfg;
880 vrs.cksum = 0;
881
882 state = 0;
883 name = remain = i = 0; /* shut up stupid gcc */
884 alloc = off = 0; /* shut up stupid gcc */
885 dflen = 0; /* shut up stupid gcc */
886 cksumvalid = -1;
887 while (state >= 0) {
888 if (vpd_nextbyte(&vrs, &byte)) {
889 state = -2;
890 break;
891 }
892#if 0
893 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
894 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
895 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
896#endif
897 switch (state) {
898 case 0: /* item name */
899 if (byte & 0x80) {
900 if (vpd_nextbyte(&vrs, &byte2)) {
901 state = -2;
902 break;
903 }
904 remain = byte2;
905 if (vpd_nextbyte(&vrs, &byte2)) {
906 state = -2;
907 break;
908 }
909 remain |= byte2 << 8;
910 if (remain > (0x7f*4 - vrs.off)) {
911 state = -1;
912 pci_printf(cfg,
913 "invalid VPD data, remain %#x\n",
914 remain);
915 }
916 name = byte & 0x7f;
917 } else {
918 remain = byte & 0x7;
919 name = (byte >> 3) & 0xf;
920 }
921 switch (name) {
922 case 0x2: /* String */
923 cfg->vpd.vpd_ident = malloc(remain + 1,
924 M_DEVBUF, M_WAITOK);
925 i = 0;
926 state = 1;
927 break;
928 case 0xf: /* End */
929 state = -1;
930 break;
931 case 0x10: /* VPD-R */
932 alloc = 8;
933 off = 0;
934 cfg->vpd.vpd_ros = malloc(alloc *
935 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
936 M_WAITOK | M_ZERO);
937 state = 2;
938 break;
939 case 0x11: /* VPD-W */
940 alloc = 8;
941 off = 0;
942 cfg->vpd.vpd_w = malloc(alloc *
943 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
944 M_WAITOK | M_ZERO);
945 state = 5;
946 break;
947 default: /* Invalid data, abort */
948 state = -1;
949 break;
950 }
951 break;
952
953 case 1: /* Identifier String */
954 cfg->vpd.vpd_ident[i++] = byte;
955 remain--;
956 if (remain == 0) {
957 cfg->vpd.vpd_ident[i] = '\0';
958 state = 0;
959 }
960 break;
961
962 case 2: /* VPD-R Keyword Header */
963 if (off == alloc) {
964 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
965 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
966 M_DEVBUF, M_WAITOK | M_ZERO);
967 }
968 cfg->vpd.vpd_ros[off].keyword[0] = byte;
969 if (vpd_nextbyte(&vrs, &byte2)) {
970 state = -2;
971 break;
972 }
973 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
974 if (vpd_nextbyte(&vrs, &byte2)) {
975 state = -2;
976 break;
977 }
978 dflen = byte2;
979 if (dflen == 0 &&
980 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
981 2) == 0) {
982 /*
983 * if this happens, we can't trust the rest
984 * of the VPD.
985 */
986 pci_printf(cfg, "bad keyword length: %d\n",
987 dflen);
988 cksumvalid = 0;
989 state = -1;
990 break;
991 } else if (dflen == 0) {
992 cfg->vpd.vpd_ros[off].value = malloc(1 *
993 sizeof(*cfg->vpd.vpd_ros[off].value),
994 M_DEVBUF, M_WAITOK);
995 cfg->vpd.vpd_ros[off].value[0] = '\x00';
996 } else
997 cfg->vpd.vpd_ros[off].value = malloc(
998 (dflen + 1) *
999 sizeof(*cfg->vpd.vpd_ros[off].value),
1000 M_DEVBUF, M_WAITOK);
1001 remain -= 3;
1002 i = 0;
1003 /* keep in sync w/ state 3's transistions */
1004 if (dflen == 0 && remain == 0)
1005 state = 0;
1006 else if (dflen == 0)
1007 state = 2;
1008 else
1009 state = 3;
1010 break;
1011
1012 case 3: /* VPD-R Keyword Value */
1013 cfg->vpd.vpd_ros[off].value[i++] = byte;
1014 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1015 "RV", 2) == 0 && cksumvalid == -1) {
1016 if (vrs.cksum == 0)
1017 cksumvalid = 1;
1018 else {
1019 if (bootverbose)
1020 pci_printf(cfg,
1021 "bad VPD cksum, remain %hhu\n",
1022 vrs.cksum);
1023 cksumvalid = 0;
1024 state = -1;
1025 break;
1026 }
1027 }
1028 dflen--;
1029 remain--;
1030 /* keep in sync w/ state 2's transistions */
1031 if (dflen == 0)
1032 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1033 if (dflen == 0 && remain == 0) {
1034 cfg->vpd.vpd_rocnt = off;
1035 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
1036 off * sizeof(*cfg->vpd.vpd_ros),
1037 M_DEVBUF, M_WAITOK | M_ZERO);
1038 state = 0;
1039 } else if (dflen == 0)
1040 state = 2;
1041 break;
1042
1043 case 4:
1044 remain--;
1045 if (remain == 0)
1046 state = 0;
1047 break;
1048
1049 case 5: /* VPD-W Keyword Header */
1050 if (off == alloc) {
1051 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1052 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1053 M_DEVBUF, M_WAITOK | M_ZERO);
1054 }
1055 cfg->vpd.vpd_w[off].keyword[0] = byte;
1056 if (vpd_nextbyte(&vrs, &byte2)) {
1057 state = -2;
1058 break;
1059 }
1060 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1061 if (vpd_nextbyte(&vrs, &byte2)) {
1062 state = -2;
1063 break;
1064 }
1065 cfg->vpd.vpd_w[off].len = dflen = byte2;
1066 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1067 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) *
1068 sizeof(*cfg->vpd.vpd_w[off].value),
1069 M_DEVBUF, M_WAITOK);
1070 remain -= 3;
1071 i = 0;
1072 /* keep in sync w/ state 6's transistions */
1073 if (dflen == 0 && remain == 0)
1074 state = 0;
1075 else if (dflen == 0)
1076 state = 5;
1077 else
1078 state = 6;
1079 break;
1080
1081 case 6: /* VPD-W Keyword Value */
1082 cfg->vpd.vpd_w[off].value[i++] = byte;
1083 dflen--;
1084 remain--;
1085 /* keep in sync w/ state 5's transistions */
1086 if (dflen == 0)
1087 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1088 if (dflen == 0 && remain == 0) {
1089 cfg->vpd.vpd_wcnt = off;
1090 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1091 off * sizeof(*cfg->vpd.vpd_w),
1092 M_DEVBUF, M_WAITOK | M_ZERO);
1093 state = 0;
1094 } else if (dflen == 0)
1095 state = 5;
1096 break;
1097
1098 default:
1099 pci_printf(cfg, "invalid state: %d\n", state);
1100 state = -1;
1101 break;
1102 }
1103 }
1104
1105 if (cksumvalid == 0 || state < -1) {
1106 /* read-only data bad, clean up */
1107 if (cfg->vpd.vpd_ros != NULL) {
1108 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1109 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1110 free(cfg->vpd.vpd_ros, M_DEVBUF);
1111 cfg->vpd.vpd_ros = NULL;
1112 }
1113 }
1114 if (state < -1) {
1115 /* I/O error, clean up */
1116 pci_printf(cfg, "failed to read VPD data.\n");
1117 if (cfg->vpd.vpd_ident != NULL) {
1118 free(cfg->vpd.vpd_ident, M_DEVBUF);
1119 cfg->vpd.vpd_ident = NULL;
1120 }
1121 if (cfg->vpd.vpd_w != NULL) {
1122 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1123 free(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1124 free(cfg->vpd.vpd_w, M_DEVBUF);
1125 cfg->vpd.vpd_w = NULL;
1126 }
1127 }
1128 cfg->vpd.vpd_cached = 1;
1129#undef REG
1130#undef WREG
1131}
1132
1133int
1134pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1135{
1136 struct pci_devinfo *dinfo = device_get_ivars(child);
1137 pcicfgregs *cfg = &dinfo->cfg;
1138
1139 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1140 pci_read_vpd(device_get_parent(dev), cfg);
1141
1142 *identptr = cfg->vpd.vpd_ident;
1143
1144 if (*identptr == NULL)
1145 return (ENXIO);
1146
1147 return (0);
1148}
1149
1150int
1151pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1152 const char **vptr)
1153{
1154 struct pci_devinfo *dinfo = device_get_ivars(child);
1155 pcicfgregs *cfg = &dinfo->cfg;
1156 int i;
1157
1158 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1159 pci_read_vpd(device_get_parent(dev), cfg);
1160
1161 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1162 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1163 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1164 *vptr = cfg->vpd.vpd_ros[i].value;
1165 return (0);
1166 }
1167
1168 *vptr = NULL;
1169 return (ENXIO);
1170}
1171
1172/*
1173 * Find the requested HyperTransport capability and return the offset
1174 * in configuration space via the pointer provided. The function
1175 * returns 0 on success and an error code otherwise.
1176 */
1177int
1178pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg)
1179{
1180 int ptr, error;
1181 uint16_t val;
1182
1183 error = pci_find_cap(child, PCIY_HT, &ptr);
1184 if (error)
1185 return (error);
1186
1187 /*
1188 * Traverse the capabilities list checking each HT capability
1189 * to see if it matches the requested HT capability.
1190 */
1191 while (ptr != 0) {
1192 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2);
1193 if (capability == PCIM_HTCAP_SLAVE ||
1194 capability == PCIM_HTCAP_HOST)
1195 val &= 0xe000;
1196 else
1197 val &= PCIM_HTCMD_CAP_MASK;
1198 if (val == capability) {
1199 if (capreg != NULL)
1200 *capreg = ptr;
1201 return (0);
1202 }
1203
1204 /* Skip to the next HT capability. */
1205 while (ptr != 0) {
1206 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1207 if (pci_read_config(child, ptr + PCICAP_ID, 1) ==
1208 PCIY_HT)
1209 break;
1210 }
1211 }
1212 return (ENOENT);
1213}
1214
1215/*
1216 * Find the requested capability and return the offset in
1217 * configuration space via the pointer provided. The function returns
1218 * 0 on success and an error code otherwise.
1219 */
1220int
1221pci_find_cap_method(device_t dev, device_t child, int capability,
1222 int *capreg)
1223{
1224 struct pci_devinfo *dinfo = device_get_ivars(child);
1225 pcicfgregs *cfg = &dinfo->cfg;
1226 u_int32_t status;
1227 u_int8_t ptr;
1228
1229 /*
1230 * Check the CAP_LIST bit of the PCI status register first.
1231 */
1232 status = pci_read_config(child, PCIR_STATUS, 2);
1233 if (!(status & PCIM_STATUS_CAPPRESENT))
1234 return (ENXIO);
1235
1236 /*
1237 * Determine the start pointer of the capabilities list.
1238 */
1239 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1240 case PCIM_HDRTYPE_NORMAL:
1241 case PCIM_HDRTYPE_BRIDGE:
1242 ptr = PCIR_CAP_PTR;
1243 break;
1244 case PCIM_HDRTYPE_CARDBUS:
1245 ptr = PCIR_CAP_PTR_2;
1246 break;
1247 default:
1248 /* XXX: panic? */
1249 return (ENXIO); /* no extended capabilities support */
1250 }
1251 ptr = pci_read_config(child, ptr, 1);
1252
1253 /*
1254 * Traverse the capabilities list.
1255 */
1256 while (ptr != 0) {
1257 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1258 if (capreg != NULL)
1259 *capreg = ptr;
1260 return (0);
1261 }
1262 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1263 }
1264
1265 return (ENOENT);
1266}
1267
1268/*
1269 * Find the requested extended capability and return the offset in
1270 * configuration space via the pointer provided. The function returns
1271 * 0 on success and an error code otherwise.
1272 */
1273int
1274pci_find_extcap_method(device_t dev, device_t child, int capability,
1275 int *capreg)
1276{
1277 struct pci_devinfo *dinfo = device_get_ivars(child);
1278 pcicfgregs *cfg = &dinfo->cfg;
1279 uint32_t ecap;
1280 uint16_t ptr;
1281
1282 /* Only supported for PCI-express devices. */
1283 if (cfg->pcie.pcie_location == 0)
1284 return (ENXIO);
1285
1286 ptr = PCIR_EXTCAP;
1287 ecap = pci_read_config(child, ptr, 4);
1288 if (ecap == 0xffffffff || ecap == 0)
1289 return (ENOENT);
1290 for (;;) {
1291 if (PCI_EXTCAP_ID(ecap) == capability) {
1292 if (capreg != NULL)
1293 *capreg = ptr;
1294 return (0);
1295 }
1296 ptr = PCI_EXTCAP_NEXTPTR(ecap);
1297 if (ptr == 0)
1298 break;
1299 ecap = pci_read_config(child, ptr, 4);
1300 }
1301
1302 return (ENOENT);
1303}
1304
1305/*
1306 * Support for MSI-X message interrupts.
1307 */
1308void
1309pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1310{
1311 struct pci_devinfo *dinfo = device_get_ivars(dev);
1312 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1313 uint32_t offset;
1314
1315 KASSERT(msix->msix_table_len > index, ("bogus index"));
1316 offset = msix->msix_table_offset + index * 16;
1317 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1318 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1319 bus_write_4(msix->msix_table_res, offset + 8, data);
1320
1321 /* Enable MSI -> HT mapping. */
1322 pci_ht_map_msi(dev, address);
1323}
1324
1325void
1326pci_mask_msix(device_t dev, u_int index)
1327{
1328 struct pci_devinfo *dinfo = device_get_ivars(dev);
1329 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1330 uint32_t offset, val;
1331
1332 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1333 offset = msix->msix_table_offset + index * 16 + 12;
1334 val = bus_read_4(msix->msix_table_res, offset);
1335 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1336 val |= PCIM_MSIX_VCTRL_MASK;
1337 bus_write_4(msix->msix_table_res, offset, val);
1338 }
1339}
1340
1341void
1342pci_unmask_msix(device_t dev, u_int index)
1343{
1344 struct pci_devinfo *dinfo = device_get_ivars(dev);
1345 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1346 uint32_t offset, val;
1347
1348 KASSERT(msix->msix_table_len > index, ("bogus index"));
1349 offset = msix->msix_table_offset + index * 16 + 12;
1350 val = bus_read_4(msix->msix_table_res, offset);
1351 if (val & PCIM_MSIX_VCTRL_MASK) {
1352 val &= ~PCIM_MSIX_VCTRL_MASK;
1353 bus_write_4(msix->msix_table_res, offset, val);
1354 }
1355}
1356
1357int
1358pci_pending_msix(device_t dev, u_int index)
1359{
1360 struct pci_devinfo *dinfo = device_get_ivars(dev);
1361 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1362 uint32_t offset, bit;
1363
1364 KASSERT(msix->msix_table_len > index, ("bogus index"));
1365 offset = msix->msix_pba_offset + (index / 32) * 4;
1366 bit = 1 << index % 32;
1367 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1368}
1369
1370/*
1371 * Restore MSI-X registers and table during resume. If MSI-X is
1372 * enabled then walk the virtual table to restore the actual MSI-X
1373 * table.
1374 */
1375static void
1376pci_resume_msix(device_t dev)
1377{
1378 struct pci_devinfo *dinfo = device_get_ivars(dev);
1379 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1380 struct msix_table_entry *mte;
1381 struct msix_vector *mv;
1382 int i;
1383
1384 if (msix->msix_alloc > 0) {
1385 /* First, mask all vectors. */
1386 for (i = 0; i < msix->msix_msgnum; i++)
1387 pci_mask_msix(dev, i);
1388
1389 /* Second, program any messages with at least one handler. */
1390 for (i = 0; i < msix->msix_table_len; i++) {
1391 mte = &msix->msix_table[i];
1392 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1393 continue;
1394 mv = &msix->msix_vectors[mte->mte_vector - 1];
1395 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1396 pci_unmask_msix(dev, i);
1397 }
1398 }
1399 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1400 msix->msix_ctrl, 2);
1401}
1402
1403/*
1404 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1405 * returned in *count. After this function returns, each message will be
1406 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1407 */
1408int
1409pci_alloc_msix_method(device_t dev, device_t child, int *count)
1410{
1411 struct pci_devinfo *dinfo = device_get_ivars(child);
1412 pcicfgregs *cfg = &dinfo->cfg;
1413 struct resource_list_entry *rle;
1414 int actual, error, i, irq, max;
1415
1416 /* Don't let count == 0 get us into trouble. */
1417 if (*count == 0)
1418 return (EINVAL);
1419
1420 /* If rid 0 is allocated, then fail. */
1421 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1422 if (rle != NULL && rle->res != NULL)
1423 return (ENXIO);
1424
1425 /* Already have allocated messages? */
1426 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1427 return (ENXIO);
1428
| 352/* Find a device_t by bus/slot/function in domain 0 */
353
354device_t
355pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
356{
357
358 return (pci_find_dbsf(0, bus, slot, func));
359}
360
361/* Find a device_t by domain/bus/slot/function */
362
363device_t
364pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
365{
366 struct pci_devinfo *dinfo;
367
368 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
369 if ((dinfo->cfg.domain == domain) &&
370 (dinfo->cfg.bus == bus) &&
371 (dinfo->cfg.slot == slot) &&
372 (dinfo->cfg.func == func)) {
373 return (dinfo->cfg.dev);
374 }
375 }
376
377 return (NULL);
378}
379
380/* Find a device_t by vendor/device ID */
381
382device_t
383pci_find_device(uint16_t vendor, uint16_t device)
384{
385 struct pci_devinfo *dinfo;
386
387 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
388 if ((dinfo->cfg.vendor == vendor) &&
389 (dinfo->cfg.device == device)) {
390 return (dinfo->cfg.dev);
391 }
392 }
393
394 return (NULL);
395}
396
397device_t
398pci_find_class(uint8_t class, uint8_t subclass)
399{
400 struct pci_devinfo *dinfo;
401
402 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
403 if (dinfo->cfg.baseclass == class &&
404 dinfo->cfg.subclass == subclass) {
405 return (dinfo->cfg.dev);
406 }
407 }
408
409 return (NULL);
410}
411
412static int
413pci_printf(pcicfgregs *cfg, const char *fmt, ...)
414{
415 va_list ap;
416 int retval;
417
418 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot,
419 cfg->func);
420 va_start(ap, fmt);
421 retval += vprintf(fmt, ap);
422 va_end(ap);
423 return (retval);
424}
425
426/* return base address of memory or port map */
427
428static pci_addr_t
429pci_mapbase(uint64_t mapreg)
430{
431
432 if (PCI_BAR_MEM(mapreg))
433 return (mapreg & PCIM_BAR_MEM_BASE);
434 else
435 return (mapreg & PCIM_BAR_IO_BASE);
436}
437
438/* return map type of memory or port map */
439
440static const char *
441pci_maptype(uint64_t mapreg)
442{
443
444 if (PCI_BAR_IO(mapreg))
445 return ("I/O Port");
446 if (mapreg & PCIM_BAR_MEM_PREFETCH)
447 return ("Prefetchable Memory");
448 return ("Memory");
449}
450
451/* return log2 of map size decoded for memory or port map */
452
453static int
454pci_mapsize(uint64_t testval)
455{
456 int ln2size;
457
458 testval = pci_mapbase(testval);
459 ln2size = 0;
460 if (testval != 0) {
461 while ((testval & 1) == 0)
462 {
463 ln2size++;
464 testval >>= 1;
465 }
466 }
467 return (ln2size);
468}
469
470/* return base address of device ROM */
471
472static pci_addr_t
473pci_rombase(uint64_t mapreg)
474{
475
476 return (mapreg & PCIM_BIOS_ADDR_MASK);
477}
478
479/* return log2 of map size decided for device ROM */
480
481static int
482pci_romsize(uint64_t testval)
483{
484 int ln2size;
485
486 testval = pci_rombase(testval);
487 ln2size = 0;
488 if (testval != 0) {
489 while ((testval & 1) == 0)
490 {
491 ln2size++;
492 testval >>= 1;
493 }
494 }
495 return (ln2size);
496}
497
498/* return log2 of address range supported by map register */
499
500static int
501pci_maprange(uint64_t mapreg)
502{
503 int ln2range = 0;
504
505 if (PCI_BAR_IO(mapreg))
506 ln2range = 32;
507 else
508 switch (mapreg & PCIM_BAR_MEM_TYPE) {
509 case PCIM_BAR_MEM_32:
510 ln2range = 32;
511 break;
512 case PCIM_BAR_MEM_1MB:
513 ln2range = 20;
514 break;
515 case PCIM_BAR_MEM_64:
516 ln2range = 64;
517 break;
518 }
519 return (ln2range);
520}
521
522/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
523
524static void
525pci_fixancient(pcicfgregs *cfg)
526{
527 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
528 return;
529
530 /* PCI to PCI bridges use header type 1 */
531 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
532 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
533}
534
535/* extract header type specific config data */
536
537static void
538pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
539{
540#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
541 switch (cfg->hdrtype & PCIM_HDRTYPE) {
542 case PCIM_HDRTYPE_NORMAL:
543 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
544 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
545 cfg->nummaps = PCI_MAXMAPS_0;
546 break;
547 case PCIM_HDRTYPE_BRIDGE:
548 cfg->nummaps = PCI_MAXMAPS_1;
549 break;
550 case PCIM_HDRTYPE_CARDBUS:
551 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
552 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
553 cfg->nummaps = PCI_MAXMAPS_2;
554 break;
555 }
556#undef REG
557}
558
559/* read configuration header into pcicfgregs structure */
560struct pci_devinfo *
561pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
562{
563#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
564 pcicfgregs *cfg = NULL;
565 struct pci_devinfo *devlist_entry;
566 struct devlist *devlist_head;
567
568 devlist_head = &pci_devq;
569
570 devlist_entry = NULL;
571
572 if (REG(PCIR_DEVVENDOR, 4) != 0xfffffffful) {
573 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
574 if (devlist_entry == NULL)
575 return (NULL);
576
577 cfg = &devlist_entry->cfg;
578
579 cfg->domain = d;
580 cfg->bus = b;
581 cfg->slot = s;
582 cfg->func = f;
583 cfg->vendor = REG(PCIR_VENDOR, 2);
584 cfg->device = REG(PCIR_DEVICE, 2);
585 cfg->cmdreg = REG(PCIR_COMMAND, 2);
586 cfg->statreg = REG(PCIR_STATUS, 2);
587 cfg->baseclass = REG(PCIR_CLASS, 1);
588 cfg->subclass = REG(PCIR_SUBCLASS, 1);
589 cfg->progif = REG(PCIR_PROGIF, 1);
590 cfg->revid = REG(PCIR_REVID, 1);
591 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
592 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
593 cfg->lattimer = REG(PCIR_LATTIMER, 1);
594 cfg->intpin = REG(PCIR_INTPIN, 1);
595 cfg->intline = REG(PCIR_INTLINE, 1);
596
597 cfg->mingnt = REG(PCIR_MINGNT, 1);
598 cfg->maxlat = REG(PCIR_MAXLAT, 1);
599
600 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
601 cfg->hdrtype &= ~PCIM_MFDEV;
602 STAILQ_INIT(&cfg->maps);
603
604 pci_fixancient(cfg);
605 pci_hdrtypedata(pcib, b, s, f, cfg);
606
607 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
608 pci_read_cap(pcib, cfg);
609
610 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
611
612 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
613 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
614 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
615 devlist_entry->conf.pc_sel.pc_func = cfg->func;
616 devlist_entry->conf.pc_hdr = cfg->hdrtype;
617
618 devlist_entry->conf.pc_subvendor = cfg->subvendor;
619 devlist_entry->conf.pc_subdevice = cfg->subdevice;
620 devlist_entry->conf.pc_vendor = cfg->vendor;
621 devlist_entry->conf.pc_device = cfg->device;
622
623 devlist_entry->conf.pc_class = cfg->baseclass;
624 devlist_entry->conf.pc_subclass = cfg->subclass;
625 devlist_entry->conf.pc_progif = cfg->progif;
626 devlist_entry->conf.pc_revid = cfg->revid;
627
628 pci_numdevs++;
629 pci_generation++;
630 }
631 return (devlist_entry);
632#undef REG
633}
634
635static void
636pci_read_cap(device_t pcib, pcicfgregs *cfg)
637{
638#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
639#define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
640#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
641 uint64_t addr;
642#endif
643 uint32_t val;
644 int ptr, nextptr, ptrptr;
645
646 switch (cfg->hdrtype & PCIM_HDRTYPE) {
647 case PCIM_HDRTYPE_NORMAL:
648 case PCIM_HDRTYPE_BRIDGE:
649 ptrptr = PCIR_CAP_PTR;
650 break;
651 case PCIM_HDRTYPE_CARDBUS:
652 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
653 break;
654 default:
655 return; /* no extended capabilities support */
656 }
657 nextptr = REG(ptrptr, 1); /* sanity check? */
658
659 /*
660 * Read capability entries.
661 */
662 while (nextptr != 0) {
663 /* Sanity check */
664 if (nextptr > 255) {
665 printf("illegal PCI extended capability offset %d\n",
666 nextptr);
667 return;
668 }
669 /* Find the next entry */
670 ptr = nextptr;
671 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
672
673 /* Process this entry */
674 switch (REG(ptr + PCICAP_ID, 1)) {
675 case PCIY_PMG: /* PCI power management */
676 if (cfg->pp.pp_cap == 0) {
677 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
678 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
679 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE;
680 if ((nextptr - ptr) > PCIR_POWER_DATA)
681 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
682 }
683 break;
684 case PCIY_HT: /* HyperTransport */
685 /* Determine HT-specific capability type. */
686 val = REG(ptr + PCIR_HT_COMMAND, 2);
687
688 if ((val & 0xe000) == PCIM_HTCAP_SLAVE)
689 cfg->ht.ht_slave = ptr;
690
691#if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
692 switch (val & PCIM_HTCMD_CAP_MASK) {
693 case PCIM_HTCAP_MSI_MAPPING:
694 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
695 /* Sanity check the mapping window. */
696 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
697 4);
698 addr <<= 32;
699 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
700 4);
701 if (addr != MSI_INTEL_ADDR_BASE)
702 device_printf(pcib,
703 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
704 cfg->domain, cfg->bus,
705 cfg->slot, cfg->func,
706 (long long)addr);
707 } else
708 addr = MSI_INTEL_ADDR_BASE;
709
710 cfg->ht.ht_msimap = ptr;
711 cfg->ht.ht_msictrl = val;
712 cfg->ht.ht_msiaddr = addr;
713 break;
714 }
715#endif
716 break;
717 case PCIY_MSI: /* PCI MSI */
718 cfg->msi.msi_location = ptr;
719 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
720 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
721 PCIM_MSICTRL_MMC_MASK)>>1);
722 break;
723 case PCIY_MSIX: /* PCI MSI-X */
724 cfg->msix.msix_location = ptr;
725 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
726 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
727 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
728 val = REG(ptr + PCIR_MSIX_TABLE, 4);
729 cfg->msix.msix_table_bar = PCIR_BAR(val &
730 PCIM_MSIX_BIR_MASK);
731 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
732 val = REG(ptr + PCIR_MSIX_PBA, 4);
733 cfg->msix.msix_pba_bar = PCIR_BAR(val &
734 PCIM_MSIX_BIR_MASK);
735 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
736 break;
737 case PCIY_VPD: /* PCI Vital Product Data */
738 cfg->vpd.vpd_reg = ptr;
739 break;
740 case PCIY_SUBVENDOR:
741 /* Should always be true. */
742 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
743 PCIM_HDRTYPE_BRIDGE) {
744 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
745 cfg->subvendor = val & 0xffff;
746 cfg->subdevice = val >> 16;
747 }
748 break;
749 case PCIY_PCIX: /* PCI-X */
750 /*
751 * Assume we have a PCI-X chipset if we have
752 * at least one PCI-PCI bridge with a PCI-X
753 * capability. Note that some systems with
754 * PCI-express or HT chipsets might match on
755 * this check as well.
756 */
757 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
758 PCIM_HDRTYPE_BRIDGE)
759 pcix_chipset = 1;
760 cfg->pcix.pcix_location = ptr;
761 break;
762 case PCIY_EXPRESS: /* PCI-express */
763 /*
764 * Assume we have a PCI-express chipset if we have
765 * at least one PCI-express device.
766 */
767 pcie_chipset = 1;
768 cfg->pcie.pcie_location = ptr;
769 val = REG(ptr + PCIER_FLAGS, 2);
770 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE;
771 break;
772 default:
773 break;
774 }
775 }
776
777#if defined(__powerpc__)
778 /*
779 * Enable the MSI mapping window for all HyperTransport
780 * slaves. PCI-PCI bridges have their windows enabled via
781 * PCIB_MAP_MSI().
782 */
783 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
784 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
785 device_printf(pcib,
786 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n",
787 cfg->domain, cfg->bus, cfg->slot, cfg->func);
788 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
789 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
790 2);
791 }
792#endif
793/* REG and WREG use carry through to next functions */
794}
795
796/*
797 * PCI Vital Product Data
798 */
799
800#define PCI_VPD_TIMEOUT 1000000
801
802static int
803pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
804{
805 int count = PCI_VPD_TIMEOUT;
806
807 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
808
809 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
810
811 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
812 if (--count < 0)
813 return (ENXIO);
814 DELAY(1); /* limit looping */
815 }
816 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
817
818 return (0);
819}
820
821#if 0
822static int
823pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
824{
825 int count = PCI_VPD_TIMEOUT;
826
827 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
828
829 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
830 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
831 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
832 if (--count < 0)
833 return (ENXIO);
834 DELAY(1); /* limit looping */
835 }
836
837 return (0);
838}
839#endif
840
841#undef PCI_VPD_TIMEOUT
842
843struct vpd_readstate {
844 device_t pcib;
845 pcicfgregs *cfg;
846 uint32_t val;
847 int bytesinval;
848 int off;
849 uint8_t cksum;
850};
851
852static int
853vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
854{
855 uint32_t reg;
856 uint8_t byte;
857
858 if (vrs->bytesinval == 0) {
859 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
860 return (ENXIO);
861 vrs->val = le32toh(reg);
862 vrs->off += 4;
863 byte = vrs->val & 0xff;
864 vrs->bytesinval = 3;
865 } else {
866 vrs->val = vrs->val >> 8;
867 byte = vrs->val & 0xff;
868 vrs->bytesinval--;
869 }
870
871 vrs->cksum += byte;
872 *data = byte;
873 return (0);
874}
875
876static void
877pci_read_vpd(device_t pcib, pcicfgregs *cfg)
878{
879 struct vpd_readstate vrs;
880 int state;
881 int name;
882 int remain;
883 int i;
884 int alloc, off; /* alloc/off for RO/W arrays */
885 int cksumvalid;
886 int dflen;
887 uint8_t byte;
888 uint8_t byte2;
889
890 /* init vpd reader */
891 vrs.bytesinval = 0;
892 vrs.off = 0;
893 vrs.pcib = pcib;
894 vrs.cfg = cfg;
895 vrs.cksum = 0;
896
897 state = 0;
898 name = remain = i = 0; /* shut up stupid gcc */
899 alloc = off = 0; /* shut up stupid gcc */
900 dflen = 0; /* shut up stupid gcc */
901 cksumvalid = -1;
902 while (state >= 0) {
903 if (vpd_nextbyte(&vrs, &byte)) {
904 state = -2;
905 break;
906 }
907#if 0
908 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
909 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
910 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
911#endif
912 switch (state) {
913 case 0: /* item name */
914 if (byte & 0x80) {
915 if (vpd_nextbyte(&vrs, &byte2)) {
916 state = -2;
917 break;
918 }
919 remain = byte2;
920 if (vpd_nextbyte(&vrs, &byte2)) {
921 state = -2;
922 break;
923 }
924 remain |= byte2 << 8;
925 if (remain > (0x7f*4 - vrs.off)) {
926 state = -1;
927 pci_printf(cfg,
928 "invalid VPD data, remain %#x\n",
929 remain);
930 }
931 name = byte & 0x7f;
932 } else {
933 remain = byte & 0x7;
934 name = (byte >> 3) & 0xf;
935 }
936 switch (name) {
937 case 0x2: /* String */
938 cfg->vpd.vpd_ident = malloc(remain + 1,
939 M_DEVBUF, M_WAITOK);
940 i = 0;
941 state = 1;
942 break;
943 case 0xf: /* End */
944 state = -1;
945 break;
946 case 0x10: /* VPD-R */
947 alloc = 8;
948 off = 0;
949 cfg->vpd.vpd_ros = malloc(alloc *
950 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
951 M_WAITOK | M_ZERO);
952 state = 2;
953 break;
954 case 0x11: /* VPD-W */
955 alloc = 8;
956 off = 0;
957 cfg->vpd.vpd_w = malloc(alloc *
958 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
959 M_WAITOK | M_ZERO);
960 state = 5;
961 break;
962 default: /* Invalid data, abort */
963 state = -1;
964 break;
965 }
966 break;
967
968 case 1: /* Identifier String */
969 cfg->vpd.vpd_ident[i++] = byte;
970 remain--;
971 if (remain == 0) {
972 cfg->vpd.vpd_ident[i] = '\0';
973 state = 0;
974 }
975 break;
976
977 case 2: /* VPD-R Keyword Header */
978 if (off == alloc) {
979 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
980 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
981 M_DEVBUF, M_WAITOK | M_ZERO);
982 }
983 cfg->vpd.vpd_ros[off].keyword[0] = byte;
984 if (vpd_nextbyte(&vrs, &byte2)) {
985 state = -2;
986 break;
987 }
988 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
989 if (vpd_nextbyte(&vrs, &byte2)) {
990 state = -2;
991 break;
992 }
993 dflen = byte2;
994 if (dflen == 0 &&
995 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
996 2) == 0) {
997 /*
998 * if this happens, we can't trust the rest
999 * of the VPD.
1000 */
1001 pci_printf(cfg, "bad keyword length: %d\n",
1002 dflen);
1003 cksumvalid = 0;
1004 state = -1;
1005 break;
1006 } else if (dflen == 0) {
1007 cfg->vpd.vpd_ros[off].value = malloc(1 *
1008 sizeof(*cfg->vpd.vpd_ros[off].value),
1009 M_DEVBUF, M_WAITOK);
1010 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1011 } else
1012 cfg->vpd.vpd_ros[off].value = malloc(
1013 (dflen + 1) *
1014 sizeof(*cfg->vpd.vpd_ros[off].value),
1015 M_DEVBUF, M_WAITOK);
1016 remain -= 3;
1017 i = 0;
1018 /* keep in sync w/ state 3's transistions */
1019 if (dflen == 0 && remain == 0)
1020 state = 0;
1021 else if (dflen == 0)
1022 state = 2;
1023 else
1024 state = 3;
1025 break;
1026
1027 case 3: /* VPD-R Keyword Value */
1028 cfg->vpd.vpd_ros[off].value[i++] = byte;
1029 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1030 "RV", 2) == 0 && cksumvalid == -1) {
1031 if (vrs.cksum == 0)
1032 cksumvalid = 1;
1033 else {
1034 if (bootverbose)
1035 pci_printf(cfg,
1036 "bad VPD cksum, remain %hhu\n",
1037 vrs.cksum);
1038 cksumvalid = 0;
1039 state = -1;
1040 break;
1041 }
1042 }
1043 dflen--;
1044 remain--;
1045 /* keep in sync w/ state 2's transistions */
1046 if (dflen == 0)
1047 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1048 if (dflen == 0 && remain == 0) {
1049 cfg->vpd.vpd_rocnt = off;
1050 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
1051 off * sizeof(*cfg->vpd.vpd_ros),
1052 M_DEVBUF, M_WAITOK | M_ZERO);
1053 state = 0;
1054 } else if (dflen == 0)
1055 state = 2;
1056 break;
1057
1058 case 4:
1059 remain--;
1060 if (remain == 0)
1061 state = 0;
1062 break;
1063
1064 case 5: /* VPD-W Keyword Header */
1065 if (off == alloc) {
1066 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1067 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1068 M_DEVBUF, M_WAITOK | M_ZERO);
1069 }
1070 cfg->vpd.vpd_w[off].keyword[0] = byte;
1071 if (vpd_nextbyte(&vrs, &byte2)) {
1072 state = -2;
1073 break;
1074 }
1075 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1076 if (vpd_nextbyte(&vrs, &byte2)) {
1077 state = -2;
1078 break;
1079 }
1080 cfg->vpd.vpd_w[off].len = dflen = byte2;
1081 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1082 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) *
1083 sizeof(*cfg->vpd.vpd_w[off].value),
1084 M_DEVBUF, M_WAITOK);
1085 remain -= 3;
1086 i = 0;
1087 /* keep in sync w/ state 6's transistions */
1088 if (dflen == 0 && remain == 0)
1089 state = 0;
1090 else if (dflen == 0)
1091 state = 5;
1092 else
1093 state = 6;
1094 break;
1095
1096 case 6: /* VPD-W Keyword Value */
1097 cfg->vpd.vpd_w[off].value[i++] = byte;
1098 dflen--;
1099 remain--;
1100 /* keep in sync w/ state 5's transistions */
1101 if (dflen == 0)
1102 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1103 if (dflen == 0 && remain == 0) {
1104 cfg->vpd.vpd_wcnt = off;
1105 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1106 off * sizeof(*cfg->vpd.vpd_w),
1107 M_DEVBUF, M_WAITOK | M_ZERO);
1108 state = 0;
1109 } else if (dflen == 0)
1110 state = 5;
1111 break;
1112
1113 default:
1114 pci_printf(cfg, "invalid state: %d\n", state);
1115 state = -1;
1116 break;
1117 }
1118 }
1119
1120 if (cksumvalid == 0 || state < -1) {
1121 /* read-only data bad, clean up */
1122 if (cfg->vpd.vpd_ros != NULL) {
1123 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1124 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1125 free(cfg->vpd.vpd_ros, M_DEVBUF);
1126 cfg->vpd.vpd_ros = NULL;
1127 }
1128 }
1129 if (state < -1) {
1130 /* I/O error, clean up */
1131 pci_printf(cfg, "failed to read VPD data.\n");
1132 if (cfg->vpd.vpd_ident != NULL) {
1133 free(cfg->vpd.vpd_ident, M_DEVBUF);
1134 cfg->vpd.vpd_ident = NULL;
1135 }
1136 if (cfg->vpd.vpd_w != NULL) {
1137 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1138 free(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1139 free(cfg->vpd.vpd_w, M_DEVBUF);
1140 cfg->vpd.vpd_w = NULL;
1141 }
1142 }
1143 cfg->vpd.vpd_cached = 1;
1144#undef REG
1145#undef WREG
1146}
1147
1148int
1149pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1150{
1151 struct pci_devinfo *dinfo = device_get_ivars(child);
1152 pcicfgregs *cfg = &dinfo->cfg;
1153
1154 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1155 pci_read_vpd(device_get_parent(dev), cfg);
1156
1157 *identptr = cfg->vpd.vpd_ident;
1158
1159 if (*identptr == NULL)
1160 return (ENXIO);
1161
1162 return (0);
1163}
1164
1165int
1166pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1167 const char **vptr)
1168{
1169 struct pci_devinfo *dinfo = device_get_ivars(child);
1170 pcicfgregs *cfg = &dinfo->cfg;
1171 int i;
1172
1173 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1174 pci_read_vpd(device_get_parent(dev), cfg);
1175
1176 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1177 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1178 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1179 *vptr = cfg->vpd.vpd_ros[i].value;
1180 return (0);
1181 }
1182
1183 *vptr = NULL;
1184 return (ENXIO);
1185}
1186
1187/*
1188 * Find the requested HyperTransport capability and return the offset
1189 * in configuration space via the pointer provided. The function
1190 * returns 0 on success and an error code otherwise.
1191 */
1192int
1193pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg)
1194{
1195 int ptr, error;
1196 uint16_t val;
1197
1198 error = pci_find_cap(child, PCIY_HT, &ptr);
1199 if (error)
1200 return (error);
1201
1202 /*
1203 * Traverse the capabilities list checking each HT capability
1204 * to see if it matches the requested HT capability.
1205 */
1206 while (ptr != 0) {
1207 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2);
1208 if (capability == PCIM_HTCAP_SLAVE ||
1209 capability == PCIM_HTCAP_HOST)
1210 val &= 0xe000;
1211 else
1212 val &= PCIM_HTCMD_CAP_MASK;
1213 if (val == capability) {
1214 if (capreg != NULL)
1215 *capreg = ptr;
1216 return (0);
1217 }
1218
1219 /* Skip to the next HT capability. */
1220 while (ptr != 0) {
1221 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1222 if (pci_read_config(child, ptr + PCICAP_ID, 1) ==
1223 PCIY_HT)
1224 break;
1225 }
1226 }
1227 return (ENOENT);
1228}
1229
1230/*
1231 * Find the requested capability and return the offset in
1232 * configuration space via the pointer provided. The function returns
1233 * 0 on success and an error code otherwise.
1234 */
1235int
1236pci_find_cap_method(device_t dev, device_t child, int capability,
1237 int *capreg)
1238{
1239 struct pci_devinfo *dinfo = device_get_ivars(child);
1240 pcicfgregs *cfg = &dinfo->cfg;
1241 u_int32_t status;
1242 u_int8_t ptr;
1243
1244 /*
1245 * Check the CAP_LIST bit of the PCI status register first.
1246 */
1247 status = pci_read_config(child, PCIR_STATUS, 2);
1248 if (!(status & PCIM_STATUS_CAPPRESENT))
1249 return (ENXIO);
1250
1251 /*
1252 * Determine the start pointer of the capabilities list.
1253 */
1254 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1255 case PCIM_HDRTYPE_NORMAL:
1256 case PCIM_HDRTYPE_BRIDGE:
1257 ptr = PCIR_CAP_PTR;
1258 break;
1259 case PCIM_HDRTYPE_CARDBUS:
1260 ptr = PCIR_CAP_PTR_2;
1261 break;
1262 default:
1263 /* XXX: panic? */
1264 return (ENXIO); /* no extended capabilities support */
1265 }
1266 ptr = pci_read_config(child, ptr, 1);
1267
1268 /*
1269 * Traverse the capabilities list.
1270 */
1271 while (ptr != 0) {
1272 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1273 if (capreg != NULL)
1274 *capreg = ptr;
1275 return (0);
1276 }
1277 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1278 }
1279
1280 return (ENOENT);
1281}
1282
1283/*
1284 * Find the requested extended capability and return the offset in
1285 * configuration space via the pointer provided. The function returns
1286 * 0 on success and an error code otherwise.
1287 */
1288int
1289pci_find_extcap_method(device_t dev, device_t child, int capability,
1290 int *capreg)
1291{
1292 struct pci_devinfo *dinfo = device_get_ivars(child);
1293 pcicfgregs *cfg = &dinfo->cfg;
1294 uint32_t ecap;
1295 uint16_t ptr;
1296
1297 /* Only supported for PCI-express devices. */
1298 if (cfg->pcie.pcie_location == 0)
1299 return (ENXIO);
1300
1301 ptr = PCIR_EXTCAP;
1302 ecap = pci_read_config(child, ptr, 4);
1303 if (ecap == 0xffffffff || ecap == 0)
1304 return (ENOENT);
1305 for (;;) {
1306 if (PCI_EXTCAP_ID(ecap) == capability) {
1307 if (capreg != NULL)
1308 *capreg = ptr;
1309 return (0);
1310 }
1311 ptr = PCI_EXTCAP_NEXTPTR(ecap);
1312 if (ptr == 0)
1313 break;
1314 ecap = pci_read_config(child, ptr, 4);
1315 }
1316
1317 return (ENOENT);
1318}
1319
1320/*
1321 * Support for MSI-X message interrupts.
1322 */
1323void
1324pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1325{
1326 struct pci_devinfo *dinfo = device_get_ivars(dev);
1327 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1328 uint32_t offset;
1329
1330 KASSERT(msix->msix_table_len > index, ("bogus index"));
1331 offset = msix->msix_table_offset + index * 16;
1332 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1333 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1334 bus_write_4(msix->msix_table_res, offset + 8, data);
1335
1336 /* Enable MSI -> HT mapping. */
1337 pci_ht_map_msi(dev, address);
1338}
1339
1340void
1341pci_mask_msix(device_t dev, u_int index)
1342{
1343 struct pci_devinfo *dinfo = device_get_ivars(dev);
1344 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1345 uint32_t offset, val;
1346
1347 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1348 offset = msix->msix_table_offset + index * 16 + 12;
1349 val = bus_read_4(msix->msix_table_res, offset);
1350 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1351 val |= PCIM_MSIX_VCTRL_MASK;
1352 bus_write_4(msix->msix_table_res, offset, val);
1353 }
1354}
1355
1356void
1357pci_unmask_msix(device_t dev, u_int index)
1358{
1359 struct pci_devinfo *dinfo = device_get_ivars(dev);
1360 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1361 uint32_t offset, val;
1362
1363 KASSERT(msix->msix_table_len > index, ("bogus index"));
1364 offset = msix->msix_table_offset + index * 16 + 12;
1365 val = bus_read_4(msix->msix_table_res, offset);
1366 if (val & PCIM_MSIX_VCTRL_MASK) {
1367 val &= ~PCIM_MSIX_VCTRL_MASK;
1368 bus_write_4(msix->msix_table_res, offset, val);
1369 }
1370}
1371
1372int
1373pci_pending_msix(device_t dev, u_int index)
1374{
1375 struct pci_devinfo *dinfo = device_get_ivars(dev);
1376 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1377 uint32_t offset, bit;
1378
1379 KASSERT(msix->msix_table_len > index, ("bogus index"));
1380 offset = msix->msix_pba_offset + (index / 32) * 4;
1381 bit = 1 << index % 32;
1382 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1383}
1384
1385/*
1386 * Restore MSI-X registers and table during resume. If MSI-X is
1387 * enabled then walk the virtual table to restore the actual MSI-X
1388 * table.
1389 */
1390static void
1391pci_resume_msix(device_t dev)
1392{
1393 struct pci_devinfo *dinfo = device_get_ivars(dev);
1394 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1395 struct msix_table_entry *mte;
1396 struct msix_vector *mv;
1397 int i;
1398
1399 if (msix->msix_alloc > 0) {
1400 /* First, mask all vectors. */
1401 for (i = 0; i < msix->msix_msgnum; i++)
1402 pci_mask_msix(dev, i);
1403
1404 /* Second, program any messages with at least one handler. */
1405 for (i = 0; i < msix->msix_table_len; i++) {
1406 mte = &msix->msix_table[i];
1407 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1408 continue;
1409 mv = &msix->msix_vectors[mte->mte_vector - 1];
1410 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1411 pci_unmask_msix(dev, i);
1412 }
1413 }
1414 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1415 msix->msix_ctrl, 2);
1416}
1417
1418/*
1419 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1420 * returned in *count. After this function returns, each message will be
1421 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1422 */
1423int
1424pci_alloc_msix_method(device_t dev, device_t child, int *count)
1425{
1426 struct pci_devinfo *dinfo = device_get_ivars(child);
1427 pcicfgregs *cfg = &dinfo->cfg;
1428 struct resource_list_entry *rle;
1429 int actual, error, i, irq, max;
1430
1431 /* Don't let count == 0 get us into trouble. */
1432 if (*count == 0)
1433 return (EINVAL);
1434
1435 /* If rid 0 is allocated, then fail. */
1436 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1437 if (rle != NULL && rle->res != NULL)
1438 return (ENXIO);
1439
1440 /* Already have allocated messages? */
1441 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1442 return (ENXIO);
1443
|
2048 * Attempt to allocate *count MSI messages. The actual number allocated is
2049 * returned in *count. After this function returns, each message will be
2050 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
2051 */
2052int
2053pci_alloc_msi_method(device_t dev, device_t child, int *count)
2054{
2055 struct pci_devinfo *dinfo = device_get_ivars(child);
2056 pcicfgregs *cfg = &dinfo->cfg;
2057 struct resource_list_entry *rle;
2058 int actual, error, i, irqs[32];
2059 uint16_t ctrl;
2060
2061 /* Don't let count == 0 get us into trouble. */
2062 if (*count == 0)
2063 return (EINVAL);
2064
2065 /* If rid 0 is allocated, then fail. */
2066 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2067 if (rle != NULL && rle->res != NULL)
2068 return (ENXIO);
2069
2070 /* Already have allocated messages? */
2071 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2072 return (ENXIO);
2073
2074 /* If MSI is blacklisted for this system, fail. */
2075 if (pci_msi_blacklisted())
2076 return (ENXIO);
2077
2078 /* MSI capability present? */
2079 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2080 return (ENODEV);
2081
2082 if (bootverbose)
2083 device_printf(child,
2084 "attempting to allocate %d MSI vectors (%d supported)\n",
2085 *count, cfg->msi.msi_msgnum);
2086
2087 /* Don't ask for more than the device supports. */
2088 actual = min(*count, cfg->msi.msi_msgnum);
2089
2090 /* Don't ask for more than 32 messages. */
2091 actual = min(actual, 32);
2092
2093 /* MSI requires power of 2 number of messages. */
2094 if (!powerof2(actual))
2095 return (EINVAL);
2096
2097 for (;;) {
2098 /* Try to allocate N messages. */
2099 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2100 actual, irqs);
2101 if (error == 0)
2102 break;
2103 if (actual == 1)
2104 return (error);
2105
2106 /* Try N / 2. */
2107 actual >>= 1;
2108 }
2109
2110 /*
2111 * We now have N actual messages mapped onto SYS_RES_IRQ
2112 * resources in the irqs[] array, so add new resources
2113 * starting at rid 1.
2114 */
2115 for (i = 0; i < actual; i++)
2116 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2117 irqs[i], irqs[i], 1);
2118
2119 if (bootverbose) {
2120 if (actual == 1)
2121 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2122 else {
2123 int run;
2124
2125 /*
2126 * Be fancy and try to print contiguous runs
2127 * of IRQ values as ranges. 'run' is true if
2128 * we are in a range.
2129 */
2130 device_printf(child, "using IRQs %d", irqs[0]);
2131 run = 0;
2132 for (i = 1; i < actual; i++) {
2133
2134 /* Still in a run? */
2135 if (irqs[i] == irqs[i - 1] + 1) {
2136 run = 1;
2137 continue;
2138 }
2139
2140 /* Finish previous range. */
2141 if (run) {
2142 printf("-%d", irqs[i - 1]);
2143 run = 0;
2144 }
2145
2146 /* Start new range. */
2147 printf(",%d", irqs[i]);
2148 }
2149
2150 /* Unfinished range? */
2151 if (run)
2152 printf("-%d", irqs[actual - 1]);
2153 printf(" for MSI\n");
2154 }
2155 }
2156
2157 /* Update control register with actual count. */
2158 ctrl = cfg->msi.msi_ctrl;
2159 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2160 ctrl |= (ffs(actual) - 1) << 4;
2161 cfg->msi.msi_ctrl = ctrl;
2162 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2163
2164 /* Update counts of alloc'd messages. */
2165 cfg->msi.msi_alloc = actual;
2166 cfg->msi.msi_handlers = 0;
2167 *count = actual;
2168 return (0);
2169}
2170
2171/* Release the MSI messages associated with this device. */
2172int
2173pci_release_msi_method(device_t dev, device_t child)
2174{
2175 struct pci_devinfo *dinfo = device_get_ivars(child);
2176 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2177 struct resource_list_entry *rle;
2178 int error, i, irqs[32];
2179
2180 /* Try MSI-X first. */
2181 error = pci_release_msix(dev, child);
2182 if (error != ENODEV)
2183 return (error);
2184
2185 /* Do we have any messages to release? */
2186 if (msi->msi_alloc == 0)
2187 return (ENODEV);
2188 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2189
2190 /* Make sure none of the resources are allocated. */
2191 if (msi->msi_handlers > 0)
2192 return (EBUSY);
2193 for (i = 0; i < msi->msi_alloc; i++) {
2194 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2195 KASSERT(rle != NULL, ("missing MSI resource"));
2196 if (rle->res != NULL)
2197 return (EBUSY);
2198 irqs[i] = rle->start;
2199 }
2200
2201 /* Update control register with 0 count. */
2202 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2203 ("%s: MSI still enabled", __func__));
2204 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2205 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2206 msi->msi_ctrl, 2);
2207
2208 /* Release the messages. */
2209 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2210 for (i = 0; i < msi->msi_alloc; i++)
2211 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2212
2213 /* Update alloc count. */
2214 msi->msi_alloc = 0;
2215 msi->msi_addr = 0;
2216 msi->msi_data = 0;
2217 return (0);
2218}
2219
2220/*
2221 * Return the max supported MSI messages this device supports.
2222 * Basically, assuming the MD code can alloc messages, this function
2223 * should return the maximum value that pci_alloc_msi() can return.
2224 * Thus, it is subject to the tunables, etc.
2225 */
2226int
2227pci_msi_count_method(device_t dev, device_t child)
2228{
2229 struct pci_devinfo *dinfo = device_get_ivars(child);
2230 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2231
2232 if (pci_do_msi && msi->msi_location != 0)
2233 return (msi->msi_msgnum);
2234 return (0);
2235}
2236
2237/* free pcicfgregs structure and all depending data structures */
2238
2239int
2240pci_freecfg(struct pci_devinfo *dinfo)
2241{
2242 struct devlist *devlist_head;
2243 struct pci_map *pm, *next;
2244 int i;
2245
2246 devlist_head = &pci_devq;
2247
2248 if (dinfo->cfg.vpd.vpd_reg) {
2249 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2250 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2251 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2252 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2253 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2254 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2255 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2256 }
2257 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) {
2258 free(pm, M_DEVBUF);
2259 }
2260 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2261 free(dinfo, M_DEVBUF);
2262
2263 /* increment the generation count */
2264 pci_generation++;
2265
2266 /* we're losing one device */
2267 pci_numdevs--;
2268 return (0);
2269}
2270
2271/*
2272 * PCI power manangement
2273 */
2274int
2275pci_set_powerstate_method(device_t dev, device_t child, int state)
2276{
2277 struct pci_devinfo *dinfo = device_get_ivars(child);
2278 pcicfgregs *cfg = &dinfo->cfg;
2279 uint16_t status;
2280 int result, oldstate, highest, delay;
2281
2282 if (cfg->pp.pp_cap == 0)
2283 return (EOPNOTSUPP);
2284
2285 /*
2286 * Optimize a no state change request away. While it would be OK to
2287 * write to the hardware in theory, some devices have shown odd
2288 * behavior when going from D3 -> D3.
2289 */
2290 oldstate = pci_get_powerstate(child);
2291 if (oldstate == state)
2292 return (0);
2293
2294 /*
2295 * The PCI power management specification states that after a state
2296 * transition between PCI power states, system software must
2297 * guarantee a minimal delay before the function accesses the device.
2298 * Compute the worst case delay that we need to guarantee before we
2299 * access the device. Many devices will be responsive much more
2300 * quickly than this delay, but there are some that don't respond
2301 * instantly to state changes. Transitions to/from D3 state require
2302 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2303 * is done below with DELAY rather than a sleeper function because
2304 * this function can be called from contexts where we cannot sleep.
2305 */
2306 highest = (oldstate > state) ? oldstate : state;
2307 if (highest == PCI_POWERSTATE_D3)
2308 delay = 10000;
2309 else if (highest == PCI_POWERSTATE_D2)
2310 delay = 200;
2311 else
2312 delay = 0;
2313 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2314 & ~PCIM_PSTAT_DMASK;
2315 result = 0;
2316 switch (state) {
2317 case PCI_POWERSTATE_D0:
2318 status |= PCIM_PSTAT_D0;
2319 break;
2320 case PCI_POWERSTATE_D1:
2321 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2322 return (EOPNOTSUPP);
2323 status |= PCIM_PSTAT_D1;
2324 break;
2325 case PCI_POWERSTATE_D2:
2326 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2327 return (EOPNOTSUPP);
2328 status |= PCIM_PSTAT_D2;
2329 break;
2330 case PCI_POWERSTATE_D3:
2331 status |= PCIM_PSTAT_D3;
2332 break;
2333 default:
2334 return (EINVAL);
2335 }
2336
2337 if (bootverbose)
2338 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate,
2339 state);
2340
2341 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2342 if (delay)
2343 DELAY(delay);
2344 return (0);
2345}
2346
2347int
2348pci_get_powerstate_method(device_t dev, device_t child)
2349{
2350 struct pci_devinfo *dinfo = device_get_ivars(child);
2351 pcicfgregs *cfg = &dinfo->cfg;
2352 uint16_t status;
2353 int result;
2354
2355 if (cfg->pp.pp_cap != 0) {
2356 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2357 switch (status & PCIM_PSTAT_DMASK) {
2358 case PCIM_PSTAT_D0:
2359 result = PCI_POWERSTATE_D0;
2360 break;
2361 case PCIM_PSTAT_D1:
2362 result = PCI_POWERSTATE_D1;
2363 break;
2364 case PCIM_PSTAT_D2:
2365 result = PCI_POWERSTATE_D2;
2366 break;
2367 case PCIM_PSTAT_D3:
2368 result = PCI_POWERSTATE_D3;
2369 break;
2370 default:
2371 result = PCI_POWERSTATE_UNKNOWN;
2372 break;
2373 }
2374 } else {
2375 /* No support, device is always at D0 */
2376 result = PCI_POWERSTATE_D0;
2377 }
2378 return (result);
2379}
2380
2381/*
2382 * Some convenience functions for PCI device drivers.
2383 */
2384
2385static __inline void
2386pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2387{
2388 uint16_t command;
2389
2390 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2391 command |= bit;
2392 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2393}
2394
2395static __inline void
2396pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2397{
2398 uint16_t command;
2399
2400 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2401 command &= ~bit;
2402 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2403}
2404
2405int
2406pci_enable_busmaster_method(device_t dev, device_t child)
2407{
2408 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2409 return (0);
2410}
2411
2412int
2413pci_disable_busmaster_method(device_t dev, device_t child)
2414{
2415 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2416 return (0);
2417}
2418
2419int
2420pci_enable_io_method(device_t dev, device_t child, int space)
2421{
2422 uint16_t bit;
2423
2424 switch(space) {
2425 case SYS_RES_IOPORT:
2426 bit = PCIM_CMD_PORTEN;
2427 break;
2428 case SYS_RES_MEMORY:
2429 bit = PCIM_CMD_MEMEN;
2430 break;
2431 default:
2432 return (EINVAL);
2433 }
2434 pci_set_command_bit(dev, child, bit);
2435 return (0);
2436}
2437
2438int
2439pci_disable_io_method(device_t dev, device_t child, int space)
2440{
2441 uint16_t bit;
2442
2443 switch(space) {
2444 case SYS_RES_IOPORT:
2445 bit = PCIM_CMD_PORTEN;
2446 break;
2447 case SYS_RES_MEMORY:
2448 bit = PCIM_CMD_MEMEN;
2449 break;
2450 default:
2451 return (EINVAL);
2452 }
2453 pci_clear_command_bit(dev, child, bit);
2454 return (0);
2455}
2456
2457/*
2458 * New style pci driver. Parent device is either a pci-host-bridge or a
2459 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2460 */
2461
2462void
2463pci_print_verbose(struct pci_devinfo *dinfo)
2464{
2465
2466 if (bootverbose) {
2467 pcicfgregs *cfg = &dinfo->cfg;
2468
2469 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2470 cfg->vendor, cfg->device, cfg->revid);
2471 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2472 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2473 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2474 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2475 cfg->mfdev);
2476 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2477 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2478 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2479 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2480 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2481 if (cfg->intpin > 0)
2482 printf("\tintpin=%c, irq=%d\n",
2483 cfg->intpin +'a' -1, cfg->intline);
2484 if (cfg->pp.pp_cap) {
2485 uint16_t status;
2486
2487 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2488 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2489 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2490 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2491 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2492 status & PCIM_PSTAT_DMASK);
2493 }
2494 if (cfg->msi.msi_location) {
2495 int ctrl;
2496
2497 ctrl = cfg->msi.msi_ctrl;
2498 printf("\tMSI supports %d message%s%s%s\n",
2499 cfg->msi.msi_msgnum,
2500 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2501 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2502 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2503 }
2504 if (cfg->msix.msix_location) {
2505 printf("\tMSI-X supports %d message%s ",
2506 cfg->msix.msix_msgnum,
2507 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2508 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2509 printf("in map 0x%x\n",
2510 cfg->msix.msix_table_bar);
2511 else
2512 printf("in maps 0x%x and 0x%x\n",
2513 cfg->msix.msix_table_bar,
2514 cfg->msix.msix_pba_bar);
2515 }
2516 }
2517}
2518
2519static int
2520pci_porten(device_t dev)
2521{
2522 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
2523}
2524
2525static int
2526pci_memen(device_t dev)
2527{
2528 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
2529}
2530
2531static void
2532pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp)
2533{
2534 struct pci_devinfo *dinfo;
2535 pci_addr_t map, testval;
2536 int ln2range;
2537 uint16_t cmd;
2538
2539 /*
2540 * The device ROM BAR is special. It is always a 32-bit
2541 * memory BAR. Bit 0 is special and should not be set when
2542 * sizing the BAR.
2543 */
2544 dinfo = device_get_ivars(dev);
2545 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) {
2546 map = pci_read_config(dev, reg, 4);
2547 pci_write_config(dev, reg, 0xfffffffe, 4);
2548 testval = pci_read_config(dev, reg, 4);
2549 pci_write_config(dev, reg, map, 4);
2550 *mapp = map;
2551 *testvalp = testval;
2552 return;
2553 }
2554
2555 map = pci_read_config(dev, reg, 4);
2556 ln2range = pci_maprange(map);
2557 if (ln2range == 64)
2558 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2559
2560 /*
2561 * Disable decoding via the command register before
2562 * determining the BAR's length since we will be placing it in
2563 * a weird state.
2564 */
2565 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2566 pci_write_config(dev, PCIR_COMMAND,
2567 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
2568
2569 /*
2570 * Determine the BAR's length by writing all 1's. The bottom
2571 * log_2(size) bits of the BAR will stick as 0 when we read
2572 * the value back.
2573 */
2574 pci_write_config(dev, reg, 0xffffffff, 4);
2575 testval = pci_read_config(dev, reg, 4);
2576 if (ln2range == 64) {
2577 pci_write_config(dev, reg + 4, 0xffffffff, 4);
2578 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2579 }
2580
2581 /*
2582 * Restore the original value of the BAR. We may have reprogrammed
2583 * the BAR of the low-level console device and when booting verbose,
2584 * we need the console device addressable.
2585 */
2586 pci_write_config(dev, reg, map, 4);
2587 if (ln2range == 64)
2588 pci_write_config(dev, reg + 4, map >> 32, 4);
2589 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2590
2591 *mapp = map;
2592 *testvalp = testval;
2593}
2594
2595static void
2596pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base)
2597{
2598 struct pci_devinfo *dinfo;
2599 int ln2range;
2600
2601 /* The device ROM BAR is always a 32-bit memory BAR. */
2602 dinfo = device_get_ivars(dev);
2603 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
2604 ln2range = 32;
2605 else
2606 ln2range = pci_maprange(pm->pm_value);
2607 pci_write_config(dev, pm->pm_reg, base, 4);
2608 if (ln2range == 64)
2609 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4);
2610 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4);
2611 if (ln2range == 64)
2612 pm->pm_value |= (pci_addr_t)pci_read_config(dev,
2613 pm->pm_reg + 4, 4) << 32;
2614}
2615
2616struct pci_map *
2617pci_find_bar(device_t dev, int reg)
2618{
2619 struct pci_devinfo *dinfo;
2620 struct pci_map *pm;
2621
2622 dinfo = device_get_ivars(dev);
2623 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
2624 if (pm->pm_reg == reg)
2625 return (pm);
2626 }
2627 return (NULL);
2628}
2629
2630int
2631pci_bar_enabled(device_t dev, struct pci_map *pm)
2632{
2633 struct pci_devinfo *dinfo;
2634 uint16_t cmd;
2635
2636 dinfo = device_get_ivars(dev);
2637 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) &&
2638 !(pm->pm_value & PCIM_BIOS_ENABLE))
2639 return (0);
2640 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2641 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value))
2642 return ((cmd & PCIM_CMD_MEMEN) != 0);
2643 else
2644 return ((cmd & PCIM_CMD_PORTEN) != 0);
2645}
2646
2647static struct pci_map *
2648pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size)
2649{
2650 struct pci_devinfo *dinfo;
2651 struct pci_map *pm, *prev;
2652
2653 dinfo = device_get_ivars(dev);
2654 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO);
2655 pm->pm_reg = reg;
2656 pm->pm_value = value;
2657 pm->pm_size = size;
2658 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) {
2659 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x",
2660 reg));
2661 if (STAILQ_NEXT(prev, pm_link) == NULL ||
2662 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg)
2663 break;
2664 }
2665 if (prev != NULL)
2666 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link);
2667 else
2668 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link);
2669 return (pm);
2670}
2671
2672static void
2673pci_restore_bars(device_t dev)
2674{
2675 struct pci_devinfo *dinfo;
2676 struct pci_map *pm;
2677 int ln2range;
2678
2679 dinfo = device_get_ivars(dev);
2680 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
2681 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
2682 ln2range = 32;
2683 else
2684 ln2range = pci_maprange(pm->pm_value);
2685 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4);
2686 if (ln2range == 64)
2687 pci_write_config(dev, pm->pm_reg + 4,
2688 pm->pm_value >> 32, 4);
2689 }
2690}
2691
2692/*
2693 * Add a resource based on a pci map register. Return 1 if the map
2694 * register is a 32bit map register or 2 if it is a 64bit register.
2695 */
2696static int
2697pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
2698 int force, int prefetch)
2699{
2700 struct pci_map *pm;
2701 pci_addr_t base, map, testval;
2702 pci_addr_t start, end, count;
2703 int barlen, basezero, maprange, mapsize, type;
2704 uint16_t cmd;
2705 struct resource *res;
2706
2707 /*
2708 * The BAR may already exist if the device is a CardBus card
2709 * whose CIS is stored in this BAR.
2710 */
2711 pm = pci_find_bar(dev, reg);
2712 if (pm != NULL) {
2713 maprange = pci_maprange(pm->pm_value);
2714 barlen = maprange == 64 ? 2 : 1;
2715 return (barlen);
2716 }
2717
2718 pci_read_bar(dev, reg, &map, &testval);
2719 if (PCI_BAR_MEM(map)) {
2720 type = SYS_RES_MEMORY;
2721 if (map & PCIM_BAR_MEM_PREFETCH)
2722 prefetch = 1;
2723 } else
2724 type = SYS_RES_IOPORT;
2725 mapsize = pci_mapsize(testval);
2726 base = pci_mapbase(map);
2727#ifdef __PCI_BAR_ZERO_VALID
2728 basezero = 0;
2729#else
2730 basezero = base == 0;
2731#endif
2732 maprange = pci_maprange(map);
2733 barlen = maprange == 64 ? 2 : 1;
2734
2735 /*
2736 * For I/O registers, if bottom bit is set, and the next bit up
2737 * isn't clear, we know we have a BAR that doesn't conform to the
2738 * spec, so ignore it. Also, sanity check the size of the data
2739 * areas to the type of memory involved. Memory must be at least
2740 * 16 bytes in size, while I/O ranges must be at least 4.
2741 */
2742 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2743 return (barlen);
2744 if ((type == SYS_RES_MEMORY && mapsize < 4) ||
2745 (type == SYS_RES_IOPORT && mapsize < 2))
2746 return (barlen);
2747
2748 /* Save a record of this BAR. */
2749 pm = pci_add_bar(dev, reg, map, mapsize);
2750 if (bootverbose) {
2751 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2752 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);
2753 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2754 printf(", port disabled\n");
2755 else if (type == SYS_RES_MEMORY && !pci_memen(dev))
2756 printf(", memory disabled\n");
2757 else
2758 printf(", enabled\n");
2759 }
2760
2761 /*
2762 * If base is 0, then we have problems if this architecture does
2763 * not allow that. It is best to ignore such entries for the
2764 * moment. These will be allocated later if the driver specifically
2765 * requests them. However, some removable busses look better when
2766 * all resources are allocated, so allow '0' to be overriden.
2767 *
2768 * Similarly treat maps whose values is the same as the test value
2769 * read back. These maps have had all f's written to them by the
2770 * BIOS in an attempt to disable the resources.
2771 */
2772 if (!force && (basezero || map == testval))
2773 return (barlen);
2774 if ((u_long)base != base) {
2775 device_printf(bus,
2776 "pci%d:%d:%d:%d bar %#x too many address bits",
2777 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
2778 pci_get_function(dev), reg);
2779 return (barlen);
2780 }
2781
2782 /*
2783 * This code theoretically does the right thing, but has
2784 * undesirable side effects in some cases where peripherals
2785 * respond oddly to having these bits enabled. Let the user
2786 * be able to turn them off (since pci_enable_io_modes is 1 by
2787 * default).
2788 */
2789 if (pci_enable_io_modes) {
2790 /* Turn on resources that have been left off by a lazy BIOS */
2791 if (type == SYS_RES_IOPORT && !pci_porten(dev)) {
2792 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2793 cmd |= PCIM_CMD_PORTEN;
2794 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2795 }
2796 if (type == SYS_RES_MEMORY && !pci_memen(dev)) {
2797 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2798 cmd |= PCIM_CMD_MEMEN;
2799 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2800 }
2801 } else {
2802 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2803 return (barlen);
2804 if (type == SYS_RES_MEMORY && !pci_memen(dev))
2805 return (barlen);
2806 }
2807
2808 count = (pci_addr_t)1 << mapsize;
2809 if (basezero || base == pci_mapbase(testval)) {
2810 start = 0; /* Let the parent decide. */
2811 end = ~0ul;
2812 } else {
2813 start = base;
2814 end = base + count - 1;
2815 }
2816 resource_list_add(rl, type, reg, start, end, count);
2817
2818 /*
2819 * Try to allocate the resource for this BAR from our parent
2820 * so that this resource range is already reserved. The
2821 * driver for this device will later inherit this resource in
2822 * pci_alloc_resource().
2823 */
2824 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count,
2825 prefetch ? RF_PREFETCHABLE : 0);
2826 if (pci_do_realloc_bars && res == NULL && (start != 0 || end != ~0ul)) {
2827 /*
2828 * If the allocation fails, try to allocate a resource for
2829 * this BAR using any available range. The firmware felt
2830 * it was important enough to assign a resource, so don't
2831 * disable decoding if we can help it.
2832 */
2833 resource_list_delete(rl, type, reg);
2834 resource_list_add(rl, type, reg, 0, ~0ul, count);
2835 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0ul,
2836 count, prefetch ? RF_PREFETCHABLE : 0);
2837 }
2838 if (res == NULL) {
2839 /*
2840 * If the allocation fails, delete the resource list entry
2841 * and disable decoding for this device.
2842 *
2843 * If the driver requests this resource in the future,
2844 * pci_reserve_map() will try to allocate a fresh
2845 * resource range.
2846 */
2847 resource_list_delete(rl, type, reg);
2848 pci_disable_io(dev, type);
2849 if (bootverbose)
2850 device_printf(bus,
2851 "pci%d:%d:%d:%d bar %#x failed to allocate\n",
2852 pci_get_domain(dev), pci_get_bus(dev),
2853 pci_get_slot(dev), pci_get_function(dev), reg);
2854 } else {
2855 start = rman_get_start(res);
2856 pci_write_bar(dev, pm, start);
2857 }
2858 return (barlen);
2859}
2860
2861/*
2862 * For ATA devices we need to decide early what addressing mode to use.
2863 * Legacy demands that the primary and secondary ATA ports sits on the
2864 * same addresses that old ISA hardware did. This dictates that we use
2865 * those addresses and ignore the BAR's if we cannot set PCI native
2866 * addressing mode.
2867 */
2868static void
2869pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
2870 uint32_t prefetchmask)
2871{
2872 struct resource *r;
2873 int rid, type, progif;
2874#if 0
2875 /* if this device supports PCI native addressing use it */
2876 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2877 if ((progif & 0x8a) == 0x8a) {
2878 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2879 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2880 printf("Trying ATA native PCI addressing mode\n");
2881 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2882 }
2883 }
2884#endif
2885 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2886 type = SYS_RES_IOPORT;
2887 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2888 pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
2889 prefetchmask & (1 << 0));
2890 pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
2891 prefetchmask & (1 << 1));
2892 } else {
2893 rid = PCIR_BAR(0);
2894 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2895 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0,
2896 0x1f7, 8, 0);
2897 rid = PCIR_BAR(1);
2898 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2899 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6,
2900 0x3f6, 1, 0);
2901 }
2902 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2903 pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
2904 prefetchmask & (1 << 2));
2905 pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
2906 prefetchmask & (1 << 3));
2907 } else {
2908 rid = PCIR_BAR(2);
2909 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2910 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x170,
2911 0x177, 8, 0);
2912 rid = PCIR_BAR(3);
2913 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2914 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x376,
2915 0x376, 1, 0);
2916 }
2917 pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
2918 prefetchmask & (1 << 4));
2919 pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
2920 prefetchmask & (1 << 5));
2921}
2922
2923static void
2924pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2925{
2926 struct pci_devinfo *dinfo = device_get_ivars(dev);
2927 pcicfgregs *cfg = &dinfo->cfg;
2928 char tunable_name[64];
2929 int irq;
2930
2931 /* Has to have an intpin to have an interrupt. */
2932 if (cfg->intpin == 0)
2933 return;
2934
2935 /* Let the user override the IRQ with a tunable. */
2936 irq = PCI_INVALID_IRQ;
2937 snprintf(tunable_name, sizeof(tunable_name),
2938 "hw.pci%d.%d.%d.INT%c.irq",
2939 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2940 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2941 irq = PCI_INVALID_IRQ;
2942
2943 /*
2944 * If we didn't get an IRQ via the tunable, then we either use the
2945 * IRQ value in the intline register or we ask the bus to route an
2946 * interrupt for us. If force_route is true, then we only use the
2947 * value in the intline register if the bus was unable to assign an
2948 * IRQ.
2949 */
2950 if (!PCI_INTERRUPT_VALID(irq)) {
2951 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2952 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2953 if (!PCI_INTERRUPT_VALID(irq))
2954 irq = cfg->intline;
2955 }
2956
2957 /* If after all that we don't have an IRQ, just bail. */
2958 if (!PCI_INTERRUPT_VALID(irq))
2959 return;
2960
2961 /* Update the config register if it changed. */
2962 if (irq != cfg->intline) {
2963 cfg->intline = irq;
2964 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2965 }
2966
2967 /* Add this IRQ as rid 0 interrupt resource. */
2968 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
2969}
2970
2971/* Perform early OHCI takeover from SMM. */
2972static void
2973ohci_early_takeover(device_t self)
2974{
2975 struct resource *res;
2976 uint32_t ctl;
2977 int rid;
2978 int i;
2979
2980 rid = PCIR_BAR(0);
2981 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
2982 if (res == NULL)
2983 return;
2984
2985 ctl = bus_read_4(res, OHCI_CONTROL);
2986 if (ctl & OHCI_IR) {
2987 if (bootverbose)
2988 printf("ohci early: "
2989 "SMM active, request owner change\n");
2990 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR);
2991 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) {
2992 DELAY(1000);
2993 ctl = bus_read_4(res, OHCI_CONTROL);
2994 }
2995 if (ctl & OHCI_IR) {
2996 if (bootverbose)
2997 printf("ohci early: "
2998 "SMM does not respond, resetting\n");
2999 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET);
3000 }
3001 /* Disable interrupts */
3002 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
3003 }
3004
3005 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3006}
3007
3008/* Perform early UHCI takeover from SMM. */
3009static void
3010uhci_early_takeover(device_t self)
3011{
3012 struct resource *res;
3013 int rid;
3014
3015 /*
3016 * Set the PIRQD enable bit and switch off all the others. We don't
3017 * want legacy support to interfere with us XXX Does this also mean
3018 * that the BIOS won't touch the keyboard anymore if it is connected
3019 * to the ports of the root hub?
3020 */
3021 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2);
3022
3023 /* Disable interrupts */
3024 rid = PCI_UHCI_BASE_REG;
3025 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE);
3026 if (res != NULL) {
3027 bus_write_2(res, UHCI_INTR, 0);
3028 bus_release_resource(self, SYS_RES_IOPORT, rid, res);
3029 }
3030}
3031
3032/* Perform early EHCI takeover from SMM. */
3033static void
3034ehci_early_takeover(device_t self)
3035{
3036 struct resource *res;
3037 uint32_t cparams;
3038 uint32_t eec;
3039 uint8_t eecp;
3040 uint8_t bios_sem;
3041 uint8_t offs;
3042 int rid;
3043 int i;
3044
3045 rid = PCIR_BAR(0);
3046 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3047 if (res == NULL)
3048 return;
3049
3050 cparams = bus_read_4(res, EHCI_HCCPARAMS);
3051
3052 /* Synchronise with the BIOS if it owns the controller. */
3053 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0;
3054 eecp = EHCI_EECP_NEXT(eec)) {
3055 eec = pci_read_config(self, eecp, 4);
3056 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) {
3057 continue;
3058 }
3059 bios_sem = pci_read_config(self, eecp +
3060 EHCI_LEGSUP_BIOS_SEM, 1);
3061 if (bios_sem == 0) {
3062 continue;
3063 }
3064 if (bootverbose)
3065 printf("ehci early: "
3066 "SMM active, request owner change\n");
3067
3068 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1);
3069
3070 for (i = 0; (i < 100) && (bios_sem != 0); i++) {
3071 DELAY(1000);
3072 bios_sem = pci_read_config(self, eecp +
3073 EHCI_LEGSUP_BIOS_SEM, 1);
3074 }
3075
3076 if (bios_sem != 0) {
3077 if (bootverbose)
3078 printf("ehci early: "
3079 "SMM does not respond\n");
3080 }
3081 /* Disable interrupts */
3082 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION));
3083 bus_write_4(res, offs + EHCI_USBINTR, 0);
3084 }
3085 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3086}
3087
3088/* Perform early XHCI takeover from SMM. */
3089static void
3090xhci_early_takeover(device_t self)
3091{
3092 struct resource *res;
3093 uint32_t cparams;
3094 uint32_t eec;
3095 uint8_t eecp;
3096 uint8_t bios_sem;
3097 uint8_t offs;
3098 int rid;
3099 int i;
3100
3101 rid = PCIR_BAR(0);
3102 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3103 if (res == NULL)
3104 return;
3105
3106 cparams = bus_read_4(res, XHCI_HCSPARAMS0);
3107
3108 eec = -1;
3109
3110 /* Synchronise with the BIOS if it owns the controller. */
3111 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
3112 eecp += XHCI_XECP_NEXT(eec) << 2) {
3113 eec = bus_read_4(res, eecp);
3114
3115 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
3116 continue;
3117
3118 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM);
3119 if (bios_sem == 0)
3120 continue;
3121
3122 if (bootverbose)
3123 printf("xhci early: "
3124 "SMM active, request owner change\n");
3125
3126 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1);
3127
3128 /* wait a maximum of 5 second */
3129
3130 for (i = 0; (i < 5000) && (bios_sem != 0); i++) {
3131 DELAY(1000);
3132 bios_sem = bus_read_1(res, eecp +
3133 XHCI_XECP_BIOS_SEM);
3134 }
3135
3136 if (bios_sem != 0) {
3137 if (bootverbose)
3138 printf("xhci early: "
3139 "SMM does not respond\n");
3140 }
3141
3142 /* Disable interrupts */
3143 offs = bus_read_1(res, XHCI_CAPLENGTH);
3144 bus_write_4(res, offs + XHCI_USBCMD, 0);
3145 bus_read_4(res, offs + XHCI_USBSTS);
3146 }
3147 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3148}
3149
3150void
3151pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
3152{
3153 struct pci_devinfo *dinfo;
3154 pcicfgregs *cfg;
3155 struct resource_list *rl;
3156 const struct pci_quirk *q;
3157 uint32_t devid;
3158 int i;
3159
3160 dinfo = device_get_ivars(dev);
3161 cfg = &dinfo->cfg;
3162 rl = &dinfo->resources;
3163 devid = (cfg->device << 16) | cfg->vendor;
3164
3165 /* ATA devices needs special map treatment */
3166 if ((pci_get_class(dev) == PCIC_STORAGE) &&
3167 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
3168 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
3169 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
3170 !pci_read_config(dev, PCIR_BAR(2), 4))) )
3171 pci_ata_maps(bus, dev, rl, force, prefetchmask);
3172 else
3173 for (i = 0; i < cfg->nummaps;) {
3174 /*
3175 * Skip quirked resources.
3176 */
3177 for (q = &pci_quirks[0]; q->devid != 0; q++)
3178 if (q->devid == devid &&
3179 q->type == PCI_QUIRK_UNMAP_REG &&
3180 q->arg1 == PCIR_BAR(i))
3181 break;
3182 if (q->devid != 0) {
3183 i++;
3184 continue;
3185 }
3186 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force,
3187 prefetchmask & (1 << i));
3188 }
3189
3190 /*
3191 * Add additional, quirked resources.
3192 */
3193 for (q = &pci_quirks[0]; q->devid != 0; q++)
3194 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG)
3195 pci_add_map(bus, dev, q->arg1, rl, force, 0);
3196
3197 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
3198#ifdef __PCI_REROUTE_INTERRUPT
3199 /*
3200 * Try to re-route interrupts. Sometimes the BIOS or
3201 * firmware may leave bogus values in these registers.
3202 * If the re-route fails, then just stick with what we
3203 * have.
3204 */
3205 pci_assign_interrupt(bus, dev, 1);
3206#else
3207 pci_assign_interrupt(bus, dev, 0);
3208#endif
3209 }
3210
3211 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS &&
3212 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
3213 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI)
3214 xhci_early_takeover(dev);
3215 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
3216 ehci_early_takeover(dev);
3217 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
3218 ohci_early_takeover(dev);
3219 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI)
3220 uhci_early_takeover(dev);
3221 }
3222}
3223
3224void
3225pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
3226{
3227#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
3228 device_t pcib = device_get_parent(dev);
3229 struct pci_devinfo *dinfo;
3230 int maxslots;
3231 int s, f, pcifunchigh;
3232 uint8_t hdrtype;
3233
3234 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
3235 ("dinfo_size too small"));
3236 maxslots = PCIB_MAXSLOTS(pcib);
3237 for (s = 0; s <= maxslots; s++) {
3238 pcifunchigh = 0;
3239 f = 0;
3240 DELAY(1);
3241 hdrtype = REG(PCIR_HDRTYPE, 1);
3242 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
3243 continue;
3244 if (hdrtype & PCIM_MFDEV)
3245 pcifunchigh = PCI_FUNCMAX;
3246 for (f = 0; f <= pcifunchigh; f++) {
3247 dinfo = pci_read_device(pcib, domain, busno, s, f,
3248 dinfo_size);
3249 if (dinfo != NULL) {
3250 pci_add_child(dev, dinfo);
3251 }
3252 }
3253 }
3254#undef REG
3255}
3256
3257void
3258pci_add_child(device_t bus, struct pci_devinfo *dinfo)
3259{
3260 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
3261 device_set_ivars(dinfo->cfg.dev, dinfo);
3262 resource_list_init(&dinfo->resources);
3263 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
3264 pci_cfg_restore(dinfo->cfg.dev, dinfo);
3265 pci_print_verbose(dinfo);
3266 pci_add_resources(bus, dinfo->cfg.dev, 0, 0);
3267}
3268
3269static int
3270pci_probe(device_t dev)
3271{
3272
3273 device_set_desc(dev, "PCI bus");
3274
3275 /* Allow other subclasses to override this driver. */
3276 return (BUS_PROBE_GENERIC);
3277}
3278
3279int
3280pci_attach_common(device_t dev)
3281{
3282 struct pci_softc *sc;
3283 int busno, domain;
3284#ifdef PCI_DMA_BOUNDARY
3285 int error, tag_valid;
3286#endif
3287
3288 sc = device_get_softc(dev);
3289 domain = pcib_get_domain(dev);
3290 busno = pcib_get_bus(dev);
3291 if (bootverbose)
3292 device_printf(dev, "domain=%d, physical bus=%d\n",
3293 domain, busno);
3294#ifdef PCI_DMA_BOUNDARY
3295 tag_valid = 0;
3296 if (device_get_devclass(device_get_parent(device_get_parent(dev))) !=
3297 devclass_find("pci")) {
3298 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1,
3299 PCI_DMA_BOUNDARY, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3300 NULL, NULL, BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED,
3301 BUS_SPACE_MAXSIZE, 0, NULL, NULL, &sc->sc_dma_tag);
3302 if (error)
3303 device_printf(dev, "Failed to create DMA tag: %d\n",
3304 error);
3305 else
3306 tag_valid = 1;
3307 }
3308 if (!tag_valid)
3309#endif
3310 sc->sc_dma_tag = bus_get_dma_tag(dev);
3311 return (0);
3312}
3313
3314static int
3315pci_attach(device_t dev)
3316{
3317 int busno, domain, error;
3318
3319 error = pci_attach_common(dev);
3320 if (error)
3321 return (error);
3322
3323 /*
3324 * Since there can be multiple independantly numbered PCI
3325 * busses on systems with multiple PCI domains, we can't use
3326 * the unit number to decide which bus we are probing. We ask
3327 * the parent pcib what our domain and bus numbers are.
3328 */
3329 domain = pcib_get_domain(dev);
3330 busno = pcib_get_bus(dev);
3331 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
3332 return (bus_generic_attach(dev));
3333}
3334
3335static void
3336pci_set_power_children(device_t dev, device_t *devlist, int numdevs,
3337 int state)
3338{
3339 device_t child, pcib;
3340 struct pci_devinfo *dinfo;
3341 int dstate, i;
3342
3343 /*
3344 * Set the device to the given state. If the firmware suggests
3345 * a different power state, use it instead. If power management
3346 * is not present, the firmware is responsible for managing
3347 * device power. Skip children who aren't attached since they
3348 * are handled separately.
3349 */
3350 pcib = device_get_parent(dev);
3351 for (i = 0; i < numdevs; i++) {
3352 child = devlist[i];
3353 dinfo = device_get_ivars(child);
3354 dstate = state;
3355 if (device_is_attached(child) &&
3356 PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0)
3357 pci_set_powerstate(child, dstate);
3358 }
3359}
3360
3361int
3362pci_suspend(device_t dev)
3363{
3364 device_t child, *devlist;
3365 struct pci_devinfo *dinfo;
3366 int error, i, numdevs;
3367
3368 /*
3369 * Save the PCI configuration space for each child and set the
3370 * device in the appropriate power state for this sleep state.
3371 */
3372 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
3373 return (error);
3374 for (i = 0; i < numdevs; i++) {
3375 child = devlist[i];
3376 dinfo = device_get_ivars(child);
3377 pci_cfg_save(child, dinfo, 0);
3378 }
3379
3380 /* Suspend devices before potentially powering them down. */
3381 error = bus_generic_suspend(dev);
3382 if (error) {
3383 free(devlist, M_TEMP);
3384 return (error);
3385 }
3386 if (pci_do_power_suspend)
3387 pci_set_power_children(dev, devlist, numdevs,
3388 PCI_POWERSTATE_D3);
3389 free(devlist, M_TEMP);
3390 return (0);
3391}
3392
3393int
3394pci_resume(device_t dev)
3395{
3396 device_t child, *devlist;
3397 struct pci_devinfo *dinfo;
3398 int error, i, numdevs;
3399
3400 /*
3401 * Set each child to D0 and restore its PCI configuration space.
3402 */
3403 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
3404 return (error);
3405 if (pci_do_power_resume)
3406 pci_set_power_children(dev, devlist, numdevs,
3407 PCI_POWERSTATE_D0);
3408
3409 /* Now the device is powered up, restore its config space. */
3410 for (i = 0; i < numdevs; i++) {
3411 child = devlist[i];
3412 dinfo = device_get_ivars(child);
3413
3414 pci_cfg_restore(child, dinfo);
3415 if (!device_is_attached(child))
3416 pci_cfg_save(child, dinfo, 1);
3417 }
3418
3419 /*
3420 * Resume critical devices first, then everything else later.
3421 */
3422 for (i = 0; i < numdevs; i++) {
3423 child = devlist[i];
3424 switch (pci_get_class(child)) {
3425 case PCIC_DISPLAY:
3426 case PCIC_MEMORY:
3427 case PCIC_BRIDGE:
3428 case PCIC_BASEPERIPH:
3429 DEVICE_RESUME(child);
3430 break;
3431 }
3432 }
3433 for (i = 0; i < numdevs; i++) {
3434 child = devlist[i];
3435 switch (pci_get_class(child)) {
3436 case PCIC_DISPLAY:
3437 case PCIC_MEMORY:
3438 case PCIC_BRIDGE:
3439 case PCIC_BASEPERIPH:
3440 break;
3441 default:
3442 DEVICE_RESUME(child);
3443 }
3444 }
3445 free(devlist, M_TEMP);
3446 return (0);
3447}
3448
3449static void
3450pci_load_vendor_data(void)
3451{
3452 caddr_t data;
3453 void *ptr;
3454 size_t sz;
3455
3456 data = preload_search_by_type("pci_vendor_data");
3457 if (data != NULL) {
3458 ptr = preload_fetch_addr(data);
3459 sz = preload_fetch_size(data);
3460 if (ptr != NULL && sz != 0) {
3461 pci_vendordata = ptr;
3462 pci_vendordata_size = sz;
3463 /* terminate the database */
3464 pci_vendordata[pci_vendordata_size] = '\n';
3465 }
3466 }
3467}
3468
3469void
3470pci_driver_added(device_t dev, driver_t *driver)
3471{
3472 int numdevs;
3473 device_t *devlist;
3474 device_t child;
3475 struct pci_devinfo *dinfo;
3476 int i;
3477
3478 if (bootverbose)
3479 device_printf(dev, "driver added\n");
3480 DEVICE_IDENTIFY(driver, dev);
3481 if (device_get_children(dev, &devlist, &numdevs) != 0)
3482 return;
3483 for (i = 0; i < numdevs; i++) {
3484 child = devlist[i];
3485 if (device_get_state(child) != DS_NOTPRESENT)
3486 continue;
3487 dinfo = device_get_ivars(child);
3488 pci_print_verbose(dinfo);
3489 if (bootverbose)
3490 pci_printf(&dinfo->cfg, "reprobing on driver added\n");
3491 pci_cfg_restore(child, dinfo);
3492 if (device_probe_and_attach(child) != 0)
3493 pci_child_detached(dev, child);
3494 }
3495 free(devlist, M_TEMP);
3496}
3497
3498int
3499pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3500 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep)
3501{
3502 struct pci_devinfo *dinfo;
3503 struct msix_table_entry *mte;
3504 struct msix_vector *mv;
3505 uint64_t addr;
3506 uint32_t data;
3507 void *cookie;
3508 int error, rid;
3509
3510 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr,
3511 arg, &cookie);
3512 if (error)
3513 return (error);
3514
3515 /* If this is not a direct child, just bail out. */
3516 if (device_get_parent(child) != dev) {
3517 *cookiep = cookie;
3518 return(0);
3519 }
3520
3521 rid = rman_get_rid(irq);
3522 if (rid == 0) {
3523 /* Make sure that INTx is enabled */
3524 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3525 } else {
3526 /*
3527 * Check to see if the interrupt is MSI or MSI-X.
3528 * Ask our parent to map the MSI and give
3529 * us the address and data register values.
3530 * If we fail for some reason, teardown the
3531 * interrupt handler.
3532 */
3533 dinfo = device_get_ivars(child);
3534 if (dinfo->cfg.msi.msi_alloc > 0) {
3535 if (dinfo->cfg.msi.msi_addr == 0) {
3536 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3537 ("MSI has handlers, but vectors not mapped"));
3538 error = PCIB_MAP_MSI(device_get_parent(dev),
3539 child, rman_get_start(irq), &addr, &data);
3540 if (error)
3541 goto bad;
3542 dinfo->cfg.msi.msi_addr = addr;
3543 dinfo->cfg.msi.msi_data = data;
3544 }
3545 if (dinfo->cfg.msi.msi_handlers == 0)
3546 pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
3547 dinfo->cfg.msi.msi_data);
3548 dinfo->cfg.msi.msi_handlers++;
3549 } else {
3550 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3551 ("No MSI or MSI-X interrupts allocated"));
3552 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3553 ("MSI-X index too high"));
3554 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3555 KASSERT(mte->mte_vector != 0, ("no message vector"));
3556 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3557 KASSERT(mv->mv_irq == rman_get_start(irq),
3558 ("IRQ mismatch"));
3559 if (mv->mv_address == 0) {
3560 KASSERT(mte->mte_handlers == 0,
3561 ("MSI-X table entry has handlers, but vector not mapped"));
3562 error = PCIB_MAP_MSI(device_get_parent(dev),
3563 child, rman_get_start(irq), &addr, &data);
3564 if (error)
3565 goto bad;
3566 mv->mv_address = addr;
3567 mv->mv_data = data;
3568 }
3569 if (mte->mte_handlers == 0) {
3570 pci_enable_msix(child, rid - 1, mv->mv_address,
3571 mv->mv_data);
3572 pci_unmask_msix(child, rid - 1);
3573 }
3574 mte->mte_handlers++;
3575 }
3576
3577 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3578 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3579 bad:
3580 if (error) {
3581 (void)bus_generic_teardown_intr(dev, child, irq,
3582 cookie);
3583 return (error);
3584 }
3585 }
3586 *cookiep = cookie;
3587 return (0);
3588}
3589
3590int
3591pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3592 void *cookie)
3593{
3594 struct msix_table_entry *mte;
3595 struct resource_list_entry *rle;
3596 struct pci_devinfo *dinfo;
3597 int error, rid;
3598
3599 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3600 return (EINVAL);
3601
3602 /* If this isn't a direct child, just bail out */
3603 if (device_get_parent(child) != dev)
3604 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3605
3606 rid = rman_get_rid(irq);
3607 if (rid == 0) {
3608 /* Mask INTx */
3609 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3610 } else {
3611 /*
3612 * Check to see if the interrupt is MSI or MSI-X. If so,
3613 * decrement the appropriate handlers count and mask the
3614 * MSI-X message, or disable MSI messages if the count
3615 * drops to 0.
3616 */
3617 dinfo = device_get_ivars(child);
3618 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3619 if (rle->res != irq)
3620 return (EINVAL);
3621 if (dinfo->cfg.msi.msi_alloc > 0) {
3622 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3623 ("MSI-X index too high"));
3624 if (dinfo->cfg.msi.msi_handlers == 0)
3625 return (EINVAL);
3626 dinfo->cfg.msi.msi_handlers--;
3627 if (dinfo->cfg.msi.msi_handlers == 0)
3628 pci_disable_msi(child);
3629 } else {
3630 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3631 ("No MSI or MSI-X interrupts allocated"));
3632 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3633 ("MSI-X index too high"));
3634 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3635 if (mte->mte_handlers == 0)
3636 return (EINVAL);
3637 mte->mte_handlers--;
3638 if (mte->mte_handlers == 0)
3639 pci_mask_msix(child, rid - 1);
3640 }
3641 }
3642 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3643 if (rid > 0)
3644 KASSERT(error == 0,
3645 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3646 return (error);
3647}
3648
3649int
3650pci_print_child(device_t dev, device_t child)
3651{
3652 struct pci_devinfo *dinfo;
3653 struct resource_list *rl;
3654 int retval = 0;
3655
3656 dinfo = device_get_ivars(child);
3657 rl = &dinfo->resources;
3658
3659 retval += bus_print_child_header(dev, child);
3660
3661 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3662 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3663 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3664 if (device_get_flags(dev))
3665 retval += printf(" flags %#x", device_get_flags(dev));
3666
3667 retval += printf(" at device %d.%d", pci_get_slot(child),
3668 pci_get_function(child));
3669
3670 retval += bus_print_child_footer(dev, child);
3671
3672 return (retval);
3673}
3674
3675static const struct
3676{
3677 int class;
3678 int subclass;
3679 const char *desc;
3680} pci_nomatch_tab[] = {
3681 {PCIC_OLD, -1, "old"},
3682 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3683 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3684 {PCIC_STORAGE, -1, "mass storage"},
3685 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3686 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3687 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3688 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3689 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3690 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3691 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3692 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3693 {PCIC_STORAGE, PCIS_STORAGE_NVM, "NVM"},
3694 {PCIC_NETWORK, -1, "network"},
3695 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3696 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3697 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3698 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3699 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3700 {PCIC_DISPLAY, -1, "display"},
3701 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3702 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3703 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3704 {PCIC_MULTIMEDIA, -1, "multimedia"},
3705 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3706 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3707 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3708 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3709 {PCIC_MEMORY, -1, "memory"},
3710 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3711 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3712 {PCIC_BRIDGE, -1, "bridge"},
3713 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3714 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3715 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3716 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3717 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3718 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3719 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3720 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3721 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3722 {PCIC_SIMPLECOMM, -1, "simple comms"},
3723 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3724 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3725 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3726 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3727 {PCIC_BASEPERIPH, -1, "base peripheral"},
3728 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3729 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3730 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3731 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3732 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3733 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3734 {PCIC_INPUTDEV, -1, "input device"},
3735 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3736 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3737 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3738 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3739 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3740 {PCIC_DOCKING, -1, "docking station"},
3741 {PCIC_PROCESSOR, -1, "processor"},
3742 {PCIC_SERIALBUS, -1, "serial bus"},
3743 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3744 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3745 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3746 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3747 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3748 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3749 {PCIC_WIRELESS, -1, "wireless controller"},
3750 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3751 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3752 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3753 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3754 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3755 {PCIC_SATCOM, -1, "satellite communication"},
3756 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3757 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3758 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3759 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3760 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3761 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3762 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3763 {PCIC_DASP, -1, "dasp"},
3764 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3765 {0, 0, NULL}
3766};
3767
3768void
3769pci_probe_nomatch(device_t dev, device_t child)
3770{
3771 int i;
3772 const char *cp, *scp;
3773 char *device;
3774
3775 /*
3776 * Look for a listing for this device in a loaded device database.
3777 */
3778 if ((device = pci_describe_device(child)) != NULL) {
3779 device_printf(dev, "<%s>", device);
3780 free(device, M_DEVBUF);
3781 } else {
3782 /*
3783 * Scan the class/subclass descriptions for a general
3784 * description.
3785 */
3786 cp = "unknown";
3787 scp = NULL;
3788 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3789 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3790 if (pci_nomatch_tab[i].subclass == -1) {
3791 cp = pci_nomatch_tab[i].desc;
3792 } else if (pci_nomatch_tab[i].subclass ==
3793 pci_get_subclass(child)) {
3794 scp = pci_nomatch_tab[i].desc;
3795 }
3796 }
3797 }
3798 device_printf(dev, "<%s%s%s>",
3799 cp ? cp : "",
3800 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3801 scp ? scp : "");
3802 }
3803 printf(" at device %d.%d (no driver attached)\n",
3804 pci_get_slot(child), pci_get_function(child));
3805 pci_cfg_save(child, device_get_ivars(child), 1);
3806}
3807
3808void
3809pci_child_detached(device_t dev, device_t child)
3810{
3811 struct pci_devinfo *dinfo;
3812 struct resource_list *rl;
3813
3814 dinfo = device_get_ivars(child);
3815 rl = &dinfo->resources;
3816
3817 /*
3818 * Have to deallocate IRQs before releasing any MSI messages and
3819 * have to release MSI messages before deallocating any memory
3820 * BARs.
3821 */
3822 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0)
3823 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n");
3824 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) {
3825 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n");
3826 (void)pci_release_msi(child);
3827 }
3828 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0)
3829 pci_printf(&dinfo->cfg, "Device leaked memory resources\n");
3830 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0)
3831 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n");
3832
3833 pci_cfg_save(child, dinfo, 1);
3834}
3835
3836/*
3837 * Parse the PCI device database, if loaded, and return a pointer to a
3838 * description of the device.
3839 *
3840 * The database is flat text formatted as follows:
3841 *
3842 * Any line not in a valid format is ignored.
3843 * Lines are terminated with newline '\n' characters.
3844 *
3845 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3846 * the vendor name.
3847 *
3848 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3849 * - devices cannot be listed without a corresponding VENDOR line.
3850 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3851 * another TAB, then the device name.
3852 */
3853
3854/*
3855 * Assuming (ptr) points to the beginning of a line in the database,
3856 * return the vendor or device and description of the next entry.
3857 * The value of (vendor) or (device) inappropriate for the entry type
3858 * is set to -1. Returns nonzero at the end of the database.
3859 *
3860 * Note that this is slightly unrobust in the face of corrupt data;
3861 * we attempt to safeguard against this by spamming the end of the
3862 * database with a newline when we initialise.
3863 */
3864static int
3865pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3866{
3867 char *cp = *ptr;
3868 int left;
3869
3870 *device = -1;
3871 *vendor = -1;
3872 **desc = '\0';
3873 for (;;) {
3874 left = pci_vendordata_size - (cp - pci_vendordata);
3875 if (left <= 0) {
3876 *ptr = cp;
3877 return(1);
3878 }
3879
3880 /* vendor entry? */
3881 if (*cp != '\t' &&
3882 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3883 break;
3884 /* device entry? */
3885 if (*cp == '\t' &&
3886 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3887 break;
3888
3889 /* skip to next line */
3890 while (*cp != '\n' && left > 0) {
3891 cp++;
3892 left--;
3893 }
3894 if (*cp == '\n') {
3895 cp++;
3896 left--;
3897 }
3898 }
3899 /* skip to next line */
3900 while (*cp != '\n' && left > 0) {
3901 cp++;
3902 left--;
3903 }
3904 if (*cp == '\n' && left > 0)
3905 cp++;
3906 *ptr = cp;
3907 return(0);
3908}
3909
3910static char *
3911pci_describe_device(device_t dev)
3912{
3913 int vendor, device;
3914 char *desc, *vp, *dp, *line;
3915
3916 desc = vp = dp = NULL;
3917
3918 /*
3919 * If we have no vendor data, we can't do anything.
3920 */
3921 if (pci_vendordata == NULL)
3922 goto out;
3923
3924 /*
3925 * Scan the vendor data looking for this device
3926 */
3927 line = pci_vendordata;
3928 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3929 goto out;
3930 for (;;) {
3931 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3932 goto out;
3933 if (vendor == pci_get_vendor(dev))
3934 break;
3935 }
3936 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3937 goto out;
3938 for (;;) {
3939 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3940 *dp = 0;
3941 break;
3942 }
3943 if (vendor != -1) {
3944 *dp = 0;
3945 break;
3946 }
3947 if (device == pci_get_device(dev))
3948 break;
3949 }
3950 if (dp[0] == '\0')
3951 snprintf(dp, 80, "0x%x", pci_get_device(dev));
3952 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3953 NULL)
3954 sprintf(desc, "%s, %s", vp, dp);
3955out:
3956 if (vp != NULL)
3957 free(vp, M_DEVBUF);
3958 if (dp != NULL)
3959 free(dp, M_DEVBUF);
3960 return(desc);
3961}
3962
3963int
3964pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3965{
3966 struct pci_devinfo *dinfo;
3967 pcicfgregs *cfg;
3968
3969 dinfo = device_get_ivars(child);
3970 cfg = &dinfo->cfg;
3971
3972 switch (which) {
3973 case PCI_IVAR_ETHADDR:
3974 /*
3975 * The generic accessor doesn't deal with failure, so
3976 * we set the return value, then return an error.
3977 */
3978 *((uint8_t **) result) = NULL;
3979 return (EINVAL);
3980 case PCI_IVAR_SUBVENDOR:
3981 *result = cfg->subvendor;
3982 break;
3983 case PCI_IVAR_SUBDEVICE:
3984 *result = cfg->subdevice;
3985 break;
3986 case PCI_IVAR_VENDOR:
3987 *result = cfg->vendor;
3988 break;
3989 case PCI_IVAR_DEVICE:
3990 *result = cfg->device;
3991 break;
3992 case PCI_IVAR_DEVID:
3993 *result = (cfg->device << 16) | cfg->vendor;
3994 break;
3995 case PCI_IVAR_CLASS:
3996 *result = cfg->baseclass;
3997 break;
3998 case PCI_IVAR_SUBCLASS:
3999 *result = cfg->subclass;
4000 break;
4001 case PCI_IVAR_PROGIF:
4002 *result = cfg->progif;
4003 break;
4004 case PCI_IVAR_REVID:
4005 *result = cfg->revid;
4006 break;
4007 case PCI_IVAR_INTPIN:
4008 *result = cfg->intpin;
4009 break;
4010 case PCI_IVAR_IRQ:
4011 *result = cfg->intline;
4012 break;
4013 case PCI_IVAR_DOMAIN:
4014 *result = cfg->domain;
4015 break;
4016 case PCI_IVAR_BUS:
4017 *result = cfg->bus;
4018 break;
4019 case PCI_IVAR_SLOT:
4020 *result = cfg->slot;
4021 break;
4022 case PCI_IVAR_FUNCTION:
4023 *result = cfg->func;
4024 break;
4025 case PCI_IVAR_CMDREG:
4026 *result = cfg->cmdreg;
4027 break;
4028 case PCI_IVAR_CACHELNSZ:
4029 *result = cfg->cachelnsz;
4030 break;
4031 case PCI_IVAR_MINGNT:
4032 *result = cfg->mingnt;
4033 break;
4034 case PCI_IVAR_MAXLAT:
4035 *result = cfg->maxlat;
4036 break;
4037 case PCI_IVAR_LATTIMER:
4038 *result = cfg->lattimer;
4039 break;
4040 default:
4041 return (ENOENT);
4042 }
4043 return (0);
4044}
4045
4046int
4047pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
4048{
4049 struct pci_devinfo *dinfo;
4050
4051 dinfo = device_get_ivars(child);
4052
4053 switch (which) {
4054 case PCI_IVAR_INTPIN:
4055 dinfo->cfg.intpin = value;
4056 return (0);
4057 case PCI_IVAR_ETHADDR:
4058 case PCI_IVAR_SUBVENDOR:
4059 case PCI_IVAR_SUBDEVICE:
4060 case PCI_IVAR_VENDOR:
4061 case PCI_IVAR_DEVICE:
4062 case PCI_IVAR_DEVID:
4063 case PCI_IVAR_CLASS:
4064 case PCI_IVAR_SUBCLASS:
4065 case PCI_IVAR_PROGIF:
4066 case PCI_IVAR_REVID:
4067 case PCI_IVAR_IRQ:
4068 case PCI_IVAR_DOMAIN:
4069 case PCI_IVAR_BUS:
4070 case PCI_IVAR_SLOT:
4071 case PCI_IVAR_FUNCTION:
4072 return (EINVAL); /* disallow for now */
4073
4074 default:
4075 return (ENOENT);
4076 }
4077}
4078
4079#include "opt_ddb.h"
4080#ifdef DDB
4081#include <ddb/ddb.h>
4082#include <sys/cons.h>
4083
4084/*
4085 * List resources based on pci map registers, used for within ddb
4086 */
4087
4088DB_SHOW_COMMAND(pciregs, db_pci_dump)
4089{
4090 struct pci_devinfo *dinfo;
4091 struct devlist *devlist_head;
4092 struct pci_conf *p;
4093 const char *name;
4094 int i, error, none_count;
4095
4096 none_count = 0;
4097 /* get the head of the device queue */
4098 devlist_head = &pci_devq;
4099
4100 /*
4101 * Go through the list of devices and print out devices
4102 */
4103 for (error = 0, i = 0,
4104 dinfo = STAILQ_FIRST(devlist_head);
4105 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
4106 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4107
4108 /* Populate pd_name and pd_unit */
4109 name = NULL;
4110 if (dinfo->cfg.dev)
4111 name = device_get_name(dinfo->cfg.dev);
4112
4113 p = &dinfo->conf;
4114 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
4115 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
4116 (name && *name) ? name : "none",
4117 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
4118 none_count++,
4119 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
4120 p->pc_sel.pc_func, (p->pc_class << 16) |
4121 (p->pc_subclass << 8) | p->pc_progif,
4122 (p->pc_subdevice << 16) | p->pc_subvendor,
4123 (p->pc_device << 16) | p->pc_vendor,
4124 p->pc_revid, p->pc_hdr);
4125 }
4126}
4127#endif /* DDB */
4128
4129static struct resource *
4130pci_reserve_map(device_t dev, device_t child, int type, int *rid,
4131 u_long start, u_long end, u_long count, u_int flags)
4132{
4133 struct pci_devinfo *dinfo = device_get_ivars(child);
4134 struct resource_list *rl = &dinfo->resources;
4135 struct resource_list_entry *rle;
4136 struct resource *res;
4137 struct pci_map *pm;
4138 pci_addr_t map, testval;
4139 int mapsize;
4140
4141 res = NULL;
4142 pm = pci_find_bar(child, *rid);
4143 if (pm != NULL) {
4144 /* This is a BAR that we failed to allocate earlier. */
4145 mapsize = pm->pm_size;
4146 map = pm->pm_value;
4147 } else {
4148 /*
4149 * Weed out the bogons, and figure out how large the
4150 * BAR/map is. BARs that read back 0 here are bogus
4151 * and unimplemented. Note: atapci in legacy mode are
4152 * special and handled elsewhere in the code. If you
4153 * have a atapci device in legacy mode and it fails
4154 * here, that other code is broken.
4155 */
4156 pci_read_bar(child, *rid, &map, &testval);
4157
4158 /*
4159 * Determine the size of the BAR and ignore BARs with a size
4160 * of 0. Device ROM BARs use a different mask value.
4161 */
4162 if (PCIR_IS_BIOS(&dinfo->cfg, *rid))
4163 mapsize = pci_romsize(testval);
4164 else
4165 mapsize = pci_mapsize(testval);
4166 if (mapsize == 0)
4167 goto out;
4168 pm = pci_add_bar(child, *rid, map, mapsize);
4169 }
4170
4171 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) {
4172 if (type != SYS_RES_MEMORY) {
4173 if (bootverbose)
4174 device_printf(dev,
4175 "child %s requested type %d for rid %#x,"
4176 " but the BAR says it is an memio\n",
4177 device_get_nameunit(child), type, *rid);
4178 goto out;
4179 }
4180 } else {
4181 if (type != SYS_RES_IOPORT) {
4182 if (bootverbose)
4183 device_printf(dev,
4184 "child %s requested type %d for rid %#x,"
4185 " but the BAR says it is an ioport\n",
4186 device_get_nameunit(child), type, *rid);
4187 goto out;
4188 }
4189 }
4190
4191 /*
4192 * For real BARs, we need to override the size that
4193 * the driver requests, because that's what the BAR
4194 * actually uses and we would otherwise have a
4195 * situation where we might allocate the excess to
4196 * another driver, which won't work.
4197 */
4198 count = (pci_addr_t)1 << mapsize;
4199 if (RF_ALIGNMENT(flags) < mapsize)
4200 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
4201 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH))
4202 flags |= RF_PREFETCHABLE;
4203
4204 /*
4205 * Allocate enough resource, and then write back the
4206 * appropriate BAR for that resource.
4207 */
4208 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
4209 start, end, count, flags & ~RF_ACTIVE);
4210 if (res == NULL) {
4211 device_printf(child,
4212 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
4213 count, *rid, type, start, end);
4214 goto out;
4215 }
4216 resource_list_add(rl, type, *rid, start, end, count);
4217 rle = resource_list_find(rl, type, *rid);
4218 if (rle == NULL)
4219 panic("pci_reserve_map: unexpectedly can't find resource.");
4220 rle->res = res;
4221 rle->start = rman_get_start(res);
4222 rle->end = rman_get_end(res);
4223 rle->count = count;
4224 rle->flags = RLE_RESERVED;
4225 if (bootverbose)
4226 device_printf(child,
4227 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
4228 count, *rid, type, rman_get_start(res));
4229 map = rman_get_start(res);
4230 pci_write_bar(child, pm, map);
4231out:
4232 return (res);
4233}
4234
4235struct resource *
4236pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
4237 u_long start, u_long end, u_long count, u_int flags)
4238{
4239 struct pci_devinfo *dinfo = device_get_ivars(child);
4240 struct resource_list *rl = &dinfo->resources;
4241 struct resource_list_entry *rle;
4242 struct resource *res;
4243 pcicfgregs *cfg = &dinfo->cfg;
4244
4245 if (device_get_parent(child) != dev)
4246 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
4247 type, rid, start, end, count, flags));
4248
4249 /*
4250 * Perform lazy resource allocation
4251 */
4252 switch (type) {
4253 case SYS_RES_IRQ:
4254 /*
4255 * Can't alloc legacy interrupt once MSI messages have
4256 * been allocated.
4257 */
4258 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
4259 cfg->msix.msix_alloc > 0))
4260 return (NULL);
4261
4262 /*
4263 * If the child device doesn't have an interrupt
4264 * routed and is deserving of an interrupt, try to
4265 * assign it one.
4266 */
4267 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
4268 (cfg->intpin != 0))
4269 pci_assign_interrupt(dev, child, 0);
4270 break;
4271 case SYS_RES_IOPORT:
4272 case SYS_RES_MEMORY:
4273#ifdef NEW_PCIB
4274 /*
4275 * PCI-PCI bridge I/O window resources are not BARs.
4276 * For those allocations just pass the request up the
4277 * tree.
4278 */
4279 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) {
4280 switch (*rid) {
4281 case PCIR_IOBASEL_1:
4282 case PCIR_MEMBASE_1:
4283 case PCIR_PMBASEL_1:
4284 /*
4285 * XXX: Should we bother creating a resource
4286 * list entry?
4287 */
4288 return (bus_generic_alloc_resource(dev, child,
4289 type, rid, start, end, count, flags));
4290 }
4291 }
4292#endif
4293 /* Reserve resources for this BAR if needed. */
4294 rle = resource_list_find(rl, type, *rid);
4295 if (rle == NULL) {
4296 res = pci_reserve_map(dev, child, type, rid, start, end,
4297 count, flags);
4298 if (res == NULL)
4299 return (NULL);
4300 }
4301 }
4302 return (resource_list_alloc(rl, dev, child, type, rid,
4303 start, end, count, flags));
4304}
4305
4306int
4307pci_activate_resource(device_t dev, device_t child, int type, int rid,
4308 struct resource *r)
4309{
4310 struct pci_devinfo *dinfo;
4311 int error;
4312
4313 error = bus_generic_activate_resource(dev, child, type, rid, r);
4314 if (error)
4315 return (error);
4316
4317 /* Enable decoding in the command register when activating BARs. */
4318 if (device_get_parent(child) == dev) {
4319 /* Device ROMs need their decoding explicitly enabled. */
4320 dinfo = device_get_ivars(child);
4321 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
4322 pci_write_bar(child, pci_find_bar(child, rid),
4323 rman_get_start(r) | PCIM_BIOS_ENABLE);
4324 switch (type) {
4325 case SYS_RES_IOPORT:
4326 case SYS_RES_MEMORY:
4327 error = PCI_ENABLE_IO(dev, child, type);
4328 break;
4329 }
4330 }
4331 return (error);
4332}
4333
4334int
4335pci_deactivate_resource(device_t dev, device_t child, int type,
4336 int rid, struct resource *r)
4337{
4338 struct pci_devinfo *dinfo;
4339 int error;
4340
4341 error = bus_generic_deactivate_resource(dev, child, type, rid, r);
4342 if (error)
4343 return (error);
4344
4345 /* Disable decoding for device ROMs. */
4346 if (device_get_parent(child) == dev) {
4347 dinfo = device_get_ivars(child);
4348 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
4349 pci_write_bar(child, pci_find_bar(child, rid),
4350 rman_get_start(r));
4351 }
4352 return (0);
4353}
4354
4355void
4356pci_delete_child(device_t dev, device_t child)
4357{
4358 struct resource_list_entry *rle;
4359 struct resource_list *rl;
4360 struct pci_devinfo *dinfo;
4361
4362 dinfo = device_get_ivars(child);
4363 rl = &dinfo->resources;
4364
4365 if (device_is_attached(child))
4366 device_detach(child);
4367
4368 /* Turn off access to resources we're about to free */
4369 pci_write_config(child, PCIR_COMMAND, pci_read_config(child,
4370 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2);
4371
4372 /* Free all allocated resources */
4373 STAILQ_FOREACH(rle, rl, link) {
4374 if (rle->res) {
4375 if (rman_get_flags(rle->res) & RF_ACTIVE ||
4376 resource_list_busy(rl, rle->type, rle->rid)) {
4377 pci_printf(&dinfo->cfg,
4378 "Resource still owned, oops. "
4379 "(type=%d, rid=%d, addr=%lx)\n",
4380 rle->type, rle->rid,
4381 rman_get_start(rle->res));
4382 bus_release_resource(child, rle->type, rle->rid,
4383 rle->res);
4384 }
4385 resource_list_unreserve(rl, dev, child, rle->type,
4386 rle->rid);
4387 }
4388 }
4389 resource_list_free(rl);
4390
4391 device_delete_child(dev, child);
4392 pci_freecfg(dinfo);
4393}
4394
4395void
4396pci_delete_resource(device_t dev, device_t child, int type, int rid)
4397{
4398 struct pci_devinfo *dinfo;
4399 struct resource_list *rl;
4400 struct resource_list_entry *rle;
4401
4402 if (device_get_parent(child) != dev)
4403 return;
4404
4405 dinfo = device_get_ivars(child);
4406 rl = &dinfo->resources;
4407 rle = resource_list_find(rl, type, rid);
4408 if (rle == NULL)
4409 return;
4410
4411 if (rle->res) {
4412 if (rman_get_flags(rle->res) & RF_ACTIVE ||
4413 resource_list_busy(rl, type, rid)) {
4414 device_printf(dev, "delete_resource: "
4415 "Resource still owned by child, oops. "
4416 "(type=%d, rid=%d, addr=%lx)\n",
4417 type, rid, rman_get_start(rle->res));
4418 return;
4419 }
4420 resource_list_unreserve(rl, dev, child, type, rid);
4421 }
4422 resource_list_delete(rl, type, rid);
4423}
4424
4425struct resource_list *
4426pci_get_resource_list (device_t dev, device_t child)
4427{
4428 struct pci_devinfo *dinfo = device_get_ivars(child);
4429
4430 return (&dinfo->resources);
4431}
4432
4433bus_dma_tag_t
4434pci_get_dma_tag(device_t bus, device_t dev)
4435{
4436 struct pci_softc *sc = device_get_softc(bus);
4437
4438 return (sc->sc_dma_tag);
4439}
4440
4441uint32_t
4442pci_read_config_method(device_t dev, device_t child, int reg, int width)
4443{
4444 struct pci_devinfo *dinfo = device_get_ivars(child);
4445 pcicfgregs *cfg = &dinfo->cfg;
4446
4447 return (PCIB_READ_CONFIG(device_get_parent(dev),
4448 cfg->bus, cfg->slot, cfg->func, reg, width));
4449}
4450
4451void
4452pci_write_config_method(device_t dev, device_t child, int reg,
4453 uint32_t val, int width)
4454{
4455 struct pci_devinfo *dinfo = device_get_ivars(child);
4456 pcicfgregs *cfg = &dinfo->cfg;
4457
4458 PCIB_WRITE_CONFIG(device_get_parent(dev),
4459 cfg->bus, cfg->slot, cfg->func, reg, val, width);
4460}
4461
4462int
4463pci_child_location_str_method(device_t dev, device_t child, char *buf,
4464 size_t buflen)
4465{
4466
4467 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
4468 pci_get_function(child));
4469 return (0);
4470}
4471
4472int
4473pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
4474 size_t buflen)
4475{
4476 struct pci_devinfo *dinfo;
4477 pcicfgregs *cfg;
4478
4479 dinfo = device_get_ivars(child);
4480 cfg = &dinfo->cfg;
4481 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
4482 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
4483 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
4484 cfg->progif);
4485 return (0);
4486}
4487
4488int
4489pci_assign_interrupt_method(device_t dev, device_t child)
4490{
4491 struct pci_devinfo *dinfo = device_get_ivars(child);
4492 pcicfgregs *cfg = &dinfo->cfg;
4493
4494 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
4495 cfg->intpin));
4496}
4497
4498static int
4499pci_modevent(module_t mod, int what, void *arg)
4500{
4501 static struct cdev *pci_cdev;
4502
4503 switch (what) {
4504 case MOD_LOAD:
4505 STAILQ_INIT(&pci_devq);
4506 pci_generation = 0;
4507 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
4508 "pci");
4509 pci_load_vendor_data();
4510 break;
4511
4512 case MOD_UNLOAD:
4513 destroy_dev(pci_cdev);
4514 break;
4515 }
4516
4517 return (0);
4518}
4519
4520static void
4521pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo)
4522{
4523#define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2)
4524 struct pcicfg_pcie *cfg;
4525 int version, pos;
4526
4527 cfg = &dinfo->cfg.pcie;
4528 pos = cfg->pcie_location;
4529
4530 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
4531
4532 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl);
4533
4534 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4535 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
4536 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
4537 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl);
4538
4539 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4540 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
4541 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
4542 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl);
4543
4544 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4545 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
4546 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl);
4547
4548 if (version > 1) {
4549 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2);
4550 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2);
4551 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2);
4552 }
4553#undef WREG
4554}
4555
4556static void
4557pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo)
4558{
4559 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND,
4560 dinfo->cfg.pcix.pcix_command, 2);
4561}
4562
4563void
4564pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
4565{
4566
4567 /*
4568 * Only do header type 0 devices. Type 1 devices are bridges,
4569 * which we know need special treatment. Type 2 devices are
4570 * cardbus bridges which also require special treatment.
4571 * Other types are unknown, and we err on the side of safety
4572 * by ignoring them.
4573 */
4574 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
4575 return;
4576
4577 /*
4578 * Restore the device to full power mode. We must do this
4579 * before we restore the registers because moving from D3 to
4580 * D0 will cause the chip's BARs and some other registers to
4581 * be reset to some unknown power on reset values. Cut down
4582 * the noise on boot by doing nothing if we are already in
4583 * state D0.
4584 */
4585 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0)
4586 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4587 pci_restore_bars(dev);
4588 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
4589 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
4590 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
4591 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
4592 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
4593 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
4594 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
4595 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
4596 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
4597
4598 /*
4599 * Restore extended capabilities for PCI-Express and PCI-X
4600 */
4601 if (dinfo->cfg.pcie.pcie_location != 0)
4602 pci_cfg_restore_pcie(dev, dinfo);
4603 if (dinfo->cfg.pcix.pcix_location != 0)
4604 pci_cfg_restore_pcix(dev, dinfo);
4605
4606 /* Restore MSI and MSI-X configurations if they are present. */
4607 if (dinfo->cfg.msi.msi_location != 0)
4608 pci_resume_msi(dev);
4609 if (dinfo->cfg.msix.msix_location != 0)
4610 pci_resume_msix(dev);
4611}
4612
4613static void
4614pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo)
4615{
4616#define RREG(n) pci_read_config(dev, pos + (n), 2)
4617 struct pcicfg_pcie *cfg;
4618 int version, pos;
4619
4620 cfg = &dinfo->cfg.pcie;
4621 pos = cfg->pcie_location;
4622
4623 cfg->pcie_flags = RREG(PCIER_FLAGS);
4624
4625 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
4626
4627 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL);
4628
4629 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4630 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
4631 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
4632 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL);
4633
4634 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4635 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
4636 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
4637 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL);
4638
4639 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4640 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
4641 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL);
4642
4643 if (version > 1) {
4644 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2);
4645 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2);
4646 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2);
4647 }
4648#undef RREG
4649}
4650
4651static void
4652pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo)
4653{
4654 dinfo->cfg.pcix.pcix_command = pci_read_config(dev,
4655 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2);
4656}
4657
4658void
4659pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
4660{
4661 uint32_t cls;
4662 int ps;
4663
4664 /*
4665 * Only do header type 0 devices. Type 1 devices are bridges, which
4666 * we know need special treatment. Type 2 devices are cardbus bridges
4667 * which also require special treatment. Other types are unknown, and
4668 * we err on the side of safety by ignoring them. Powering down
4669 * bridges should not be undertaken lightly.
4670 */
4671 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
4672 return;
4673
4674 /*
4675 * Some drivers apparently write to these registers w/o updating our
4676 * cached copy. No harm happens if we update the copy, so do so here
4677 * so we can restore them. The COMMAND register is modified by the
4678 * bus w/o updating the cache. This should represent the normally
4679 * writable portion of the 'defined' part of type 0 headers. In
4680 * theory we also need to save/restore the PCI capability structures
4681 * we know about, but apart from power we don't know any that are
4682 * writable.
4683 */
4684 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4685 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4686 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4687 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4688 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4689 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4690 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4691 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4692 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4693 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4694 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4695 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4696 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4697 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4698 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4699
4700 if (dinfo->cfg.pcie.pcie_location != 0)
4701 pci_cfg_save_pcie(dev, dinfo);
4702
4703 if (dinfo->cfg.pcix.pcix_location != 0)
4704 pci_cfg_save_pcix(dev, dinfo);
4705
4706 /*
4707 * don't set the state for display devices, base peripherals and
4708 * memory devices since bad things happen when they are powered down.
4709 * We should (a) have drivers that can easily detach and (b) use
4710 * generic drivers for these devices so that some device actually
4711 * attaches. We need to make sure that when we implement (a) we don't
4712 * power the device down on a reattach.
4713 */
4714 cls = pci_get_class(dev);
4715 if (!setstate)
4716 return;
4717 switch (pci_do_power_nodriver)
4718 {
4719 case 0: /* NO powerdown at all */
4720 return;
4721 case 1: /* Conservative about what to power down */
4722 if (cls == PCIC_STORAGE)
4723 return;
4724 /*FALLTHROUGH*/
4725 case 2: /* Agressive about what to power down */
4726 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4727 cls == PCIC_BASEPERIPH)
4728 return;
4729 /*FALLTHROUGH*/
4730 case 3: /* Power down everything */
4731 break;
4732 }
4733 /*
4734 * PCI spec says we can only go into D3 state from D0 state.
4735 * Transition from D[12] into D0 before going to D3 state.
4736 */
4737 ps = pci_get_powerstate(dev);
4738 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4739 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4740 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4741 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
4742}
4743
4744/* Wrapper APIs suitable for device driver use. */
4745void
4746pci_save_state(device_t dev)
4747{
4748 struct pci_devinfo *dinfo;
4749
4750 dinfo = device_get_ivars(dev);
4751 pci_cfg_save(dev, dinfo, 0);
4752}
4753
4754void
4755pci_restore_state(device_t dev)
4756{
4757 struct pci_devinfo *dinfo;
4758
4759 dinfo = device_get_ivars(dev);
4760 pci_cfg_restore(dev, dinfo);
4761}
| 2084 * Attempt to allocate *count MSI messages. The actual number allocated is
2085 * returned in *count. After this function returns, each message will be
2086 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
2087 */
2088int
2089pci_alloc_msi_method(device_t dev, device_t child, int *count)
2090{
2091 struct pci_devinfo *dinfo = device_get_ivars(child);
2092 pcicfgregs *cfg = &dinfo->cfg;
2093 struct resource_list_entry *rle;
2094 int actual, error, i, irqs[32];
2095 uint16_t ctrl;
2096
2097 /* Don't let count == 0 get us into trouble. */
2098 if (*count == 0)
2099 return (EINVAL);
2100
2101 /* If rid 0 is allocated, then fail. */
2102 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2103 if (rle != NULL && rle->res != NULL)
2104 return (ENXIO);
2105
2106 /* Already have allocated messages? */
2107 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2108 return (ENXIO);
2109
2110 /* If MSI is blacklisted for this system, fail. */
2111 if (pci_msi_blacklisted())
2112 return (ENXIO);
2113
2114 /* MSI capability present? */
2115 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2116 return (ENODEV);
2117
2118 if (bootverbose)
2119 device_printf(child,
2120 "attempting to allocate %d MSI vectors (%d supported)\n",
2121 *count, cfg->msi.msi_msgnum);
2122
2123 /* Don't ask for more than the device supports. */
2124 actual = min(*count, cfg->msi.msi_msgnum);
2125
2126 /* Don't ask for more than 32 messages. */
2127 actual = min(actual, 32);
2128
2129 /* MSI requires power of 2 number of messages. */
2130 if (!powerof2(actual))
2131 return (EINVAL);
2132
2133 for (;;) {
2134 /* Try to allocate N messages. */
2135 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2136 actual, irqs);
2137 if (error == 0)
2138 break;
2139 if (actual == 1)
2140 return (error);
2141
2142 /* Try N / 2. */
2143 actual >>= 1;
2144 }
2145
2146 /*
2147 * We now have N actual messages mapped onto SYS_RES_IRQ
2148 * resources in the irqs[] array, so add new resources
2149 * starting at rid 1.
2150 */
2151 for (i = 0; i < actual; i++)
2152 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2153 irqs[i], irqs[i], 1);
2154
2155 if (bootverbose) {
2156 if (actual == 1)
2157 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2158 else {
2159 int run;
2160
2161 /*
2162 * Be fancy and try to print contiguous runs
2163 * of IRQ values as ranges. 'run' is true if
2164 * we are in a range.
2165 */
2166 device_printf(child, "using IRQs %d", irqs[0]);
2167 run = 0;
2168 for (i = 1; i < actual; i++) {
2169
2170 /* Still in a run? */
2171 if (irqs[i] == irqs[i - 1] + 1) {
2172 run = 1;
2173 continue;
2174 }
2175
2176 /* Finish previous range. */
2177 if (run) {
2178 printf("-%d", irqs[i - 1]);
2179 run = 0;
2180 }
2181
2182 /* Start new range. */
2183 printf(",%d", irqs[i]);
2184 }
2185
2186 /* Unfinished range? */
2187 if (run)
2188 printf("-%d", irqs[actual - 1]);
2189 printf(" for MSI\n");
2190 }
2191 }
2192
2193 /* Update control register with actual count. */
2194 ctrl = cfg->msi.msi_ctrl;
2195 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2196 ctrl |= (ffs(actual) - 1) << 4;
2197 cfg->msi.msi_ctrl = ctrl;
2198 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2199
2200 /* Update counts of alloc'd messages. */
2201 cfg->msi.msi_alloc = actual;
2202 cfg->msi.msi_handlers = 0;
2203 *count = actual;
2204 return (0);
2205}
2206
2207/* Release the MSI messages associated with this device. */
2208int
2209pci_release_msi_method(device_t dev, device_t child)
2210{
2211 struct pci_devinfo *dinfo = device_get_ivars(child);
2212 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2213 struct resource_list_entry *rle;
2214 int error, i, irqs[32];
2215
2216 /* Try MSI-X first. */
2217 error = pci_release_msix(dev, child);
2218 if (error != ENODEV)
2219 return (error);
2220
2221 /* Do we have any messages to release? */
2222 if (msi->msi_alloc == 0)
2223 return (ENODEV);
2224 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2225
2226 /* Make sure none of the resources are allocated. */
2227 if (msi->msi_handlers > 0)
2228 return (EBUSY);
2229 for (i = 0; i < msi->msi_alloc; i++) {
2230 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2231 KASSERT(rle != NULL, ("missing MSI resource"));
2232 if (rle->res != NULL)
2233 return (EBUSY);
2234 irqs[i] = rle->start;
2235 }
2236
2237 /* Update control register with 0 count. */
2238 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2239 ("%s: MSI still enabled", __func__));
2240 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2241 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2242 msi->msi_ctrl, 2);
2243
2244 /* Release the messages. */
2245 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2246 for (i = 0; i < msi->msi_alloc; i++)
2247 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2248
2249 /* Update alloc count. */
2250 msi->msi_alloc = 0;
2251 msi->msi_addr = 0;
2252 msi->msi_data = 0;
2253 return (0);
2254}
2255
2256/*
2257 * Return the max supported MSI messages this device supports.
2258 * Basically, assuming the MD code can alloc messages, this function
2259 * should return the maximum value that pci_alloc_msi() can return.
2260 * Thus, it is subject to the tunables, etc.
2261 */
2262int
2263pci_msi_count_method(device_t dev, device_t child)
2264{
2265 struct pci_devinfo *dinfo = device_get_ivars(child);
2266 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2267
2268 if (pci_do_msi && msi->msi_location != 0)
2269 return (msi->msi_msgnum);
2270 return (0);
2271}
2272
2273/* free pcicfgregs structure and all depending data structures */
2274
2275int
2276pci_freecfg(struct pci_devinfo *dinfo)
2277{
2278 struct devlist *devlist_head;
2279 struct pci_map *pm, *next;
2280 int i;
2281
2282 devlist_head = &pci_devq;
2283
2284 if (dinfo->cfg.vpd.vpd_reg) {
2285 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2286 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2287 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2288 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2289 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2290 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2291 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2292 }
2293 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) {
2294 free(pm, M_DEVBUF);
2295 }
2296 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2297 free(dinfo, M_DEVBUF);
2298
2299 /* increment the generation count */
2300 pci_generation++;
2301
2302 /* we're losing one device */
2303 pci_numdevs--;
2304 return (0);
2305}
2306
2307/*
2308 * PCI power manangement
2309 */
2310int
2311pci_set_powerstate_method(device_t dev, device_t child, int state)
2312{
2313 struct pci_devinfo *dinfo = device_get_ivars(child);
2314 pcicfgregs *cfg = &dinfo->cfg;
2315 uint16_t status;
2316 int result, oldstate, highest, delay;
2317
2318 if (cfg->pp.pp_cap == 0)
2319 return (EOPNOTSUPP);
2320
2321 /*
2322 * Optimize a no state change request away. While it would be OK to
2323 * write to the hardware in theory, some devices have shown odd
2324 * behavior when going from D3 -> D3.
2325 */
2326 oldstate = pci_get_powerstate(child);
2327 if (oldstate == state)
2328 return (0);
2329
2330 /*
2331 * The PCI power management specification states that after a state
2332 * transition between PCI power states, system software must
2333 * guarantee a minimal delay before the function accesses the device.
2334 * Compute the worst case delay that we need to guarantee before we
2335 * access the device. Many devices will be responsive much more
2336 * quickly than this delay, but there are some that don't respond
2337 * instantly to state changes. Transitions to/from D3 state require
2338 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2339 * is done below with DELAY rather than a sleeper function because
2340 * this function can be called from contexts where we cannot sleep.
2341 */
2342 highest = (oldstate > state) ? oldstate : state;
2343 if (highest == PCI_POWERSTATE_D3)
2344 delay = 10000;
2345 else if (highest == PCI_POWERSTATE_D2)
2346 delay = 200;
2347 else
2348 delay = 0;
2349 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2350 & ~PCIM_PSTAT_DMASK;
2351 result = 0;
2352 switch (state) {
2353 case PCI_POWERSTATE_D0:
2354 status |= PCIM_PSTAT_D0;
2355 break;
2356 case PCI_POWERSTATE_D1:
2357 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2358 return (EOPNOTSUPP);
2359 status |= PCIM_PSTAT_D1;
2360 break;
2361 case PCI_POWERSTATE_D2:
2362 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2363 return (EOPNOTSUPP);
2364 status |= PCIM_PSTAT_D2;
2365 break;
2366 case PCI_POWERSTATE_D3:
2367 status |= PCIM_PSTAT_D3;
2368 break;
2369 default:
2370 return (EINVAL);
2371 }
2372
2373 if (bootverbose)
2374 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate,
2375 state);
2376
2377 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2378 if (delay)
2379 DELAY(delay);
2380 return (0);
2381}
2382
2383int
2384pci_get_powerstate_method(device_t dev, device_t child)
2385{
2386 struct pci_devinfo *dinfo = device_get_ivars(child);
2387 pcicfgregs *cfg = &dinfo->cfg;
2388 uint16_t status;
2389 int result;
2390
2391 if (cfg->pp.pp_cap != 0) {
2392 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2393 switch (status & PCIM_PSTAT_DMASK) {
2394 case PCIM_PSTAT_D0:
2395 result = PCI_POWERSTATE_D0;
2396 break;
2397 case PCIM_PSTAT_D1:
2398 result = PCI_POWERSTATE_D1;
2399 break;
2400 case PCIM_PSTAT_D2:
2401 result = PCI_POWERSTATE_D2;
2402 break;
2403 case PCIM_PSTAT_D3:
2404 result = PCI_POWERSTATE_D3;
2405 break;
2406 default:
2407 result = PCI_POWERSTATE_UNKNOWN;
2408 break;
2409 }
2410 } else {
2411 /* No support, device is always at D0 */
2412 result = PCI_POWERSTATE_D0;
2413 }
2414 return (result);
2415}
2416
2417/*
2418 * Some convenience functions for PCI device drivers.
2419 */
2420
2421static __inline void
2422pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2423{
2424 uint16_t command;
2425
2426 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2427 command |= bit;
2428 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2429}
2430
2431static __inline void
2432pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2433{
2434 uint16_t command;
2435
2436 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2437 command &= ~bit;
2438 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2439}
2440
2441int
2442pci_enable_busmaster_method(device_t dev, device_t child)
2443{
2444 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2445 return (0);
2446}
2447
2448int
2449pci_disable_busmaster_method(device_t dev, device_t child)
2450{
2451 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2452 return (0);
2453}
2454
2455int
2456pci_enable_io_method(device_t dev, device_t child, int space)
2457{
2458 uint16_t bit;
2459
2460 switch(space) {
2461 case SYS_RES_IOPORT:
2462 bit = PCIM_CMD_PORTEN;
2463 break;
2464 case SYS_RES_MEMORY:
2465 bit = PCIM_CMD_MEMEN;
2466 break;
2467 default:
2468 return (EINVAL);
2469 }
2470 pci_set_command_bit(dev, child, bit);
2471 return (0);
2472}
2473
2474int
2475pci_disable_io_method(device_t dev, device_t child, int space)
2476{
2477 uint16_t bit;
2478
2479 switch(space) {
2480 case SYS_RES_IOPORT:
2481 bit = PCIM_CMD_PORTEN;
2482 break;
2483 case SYS_RES_MEMORY:
2484 bit = PCIM_CMD_MEMEN;
2485 break;
2486 default:
2487 return (EINVAL);
2488 }
2489 pci_clear_command_bit(dev, child, bit);
2490 return (0);
2491}
2492
2493/*
2494 * New style pci driver. Parent device is either a pci-host-bridge or a
2495 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2496 */
2497
2498void
2499pci_print_verbose(struct pci_devinfo *dinfo)
2500{
2501
2502 if (bootverbose) {
2503 pcicfgregs *cfg = &dinfo->cfg;
2504
2505 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2506 cfg->vendor, cfg->device, cfg->revid);
2507 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2508 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2509 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2510 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2511 cfg->mfdev);
2512 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2513 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2514 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2515 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2516 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2517 if (cfg->intpin > 0)
2518 printf("\tintpin=%c, irq=%d\n",
2519 cfg->intpin +'a' -1, cfg->intline);
2520 if (cfg->pp.pp_cap) {
2521 uint16_t status;
2522
2523 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2524 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2525 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2526 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2527 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2528 status & PCIM_PSTAT_DMASK);
2529 }
2530 if (cfg->msi.msi_location) {
2531 int ctrl;
2532
2533 ctrl = cfg->msi.msi_ctrl;
2534 printf("\tMSI supports %d message%s%s%s\n",
2535 cfg->msi.msi_msgnum,
2536 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2537 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2538 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2539 }
2540 if (cfg->msix.msix_location) {
2541 printf("\tMSI-X supports %d message%s ",
2542 cfg->msix.msix_msgnum,
2543 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2544 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2545 printf("in map 0x%x\n",
2546 cfg->msix.msix_table_bar);
2547 else
2548 printf("in maps 0x%x and 0x%x\n",
2549 cfg->msix.msix_table_bar,
2550 cfg->msix.msix_pba_bar);
2551 }
2552 }
2553}
2554
2555static int
2556pci_porten(device_t dev)
2557{
2558 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
2559}
2560
2561static int
2562pci_memen(device_t dev)
2563{
2564 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
2565}
2566
2567static void
2568pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp)
2569{
2570 struct pci_devinfo *dinfo;
2571 pci_addr_t map, testval;
2572 int ln2range;
2573 uint16_t cmd;
2574
2575 /*
2576 * The device ROM BAR is special. It is always a 32-bit
2577 * memory BAR. Bit 0 is special and should not be set when
2578 * sizing the BAR.
2579 */
2580 dinfo = device_get_ivars(dev);
2581 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) {
2582 map = pci_read_config(dev, reg, 4);
2583 pci_write_config(dev, reg, 0xfffffffe, 4);
2584 testval = pci_read_config(dev, reg, 4);
2585 pci_write_config(dev, reg, map, 4);
2586 *mapp = map;
2587 *testvalp = testval;
2588 return;
2589 }
2590
2591 map = pci_read_config(dev, reg, 4);
2592 ln2range = pci_maprange(map);
2593 if (ln2range == 64)
2594 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2595
2596 /*
2597 * Disable decoding via the command register before
2598 * determining the BAR's length since we will be placing it in
2599 * a weird state.
2600 */
2601 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2602 pci_write_config(dev, PCIR_COMMAND,
2603 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
2604
2605 /*
2606 * Determine the BAR's length by writing all 1's. The bottom
2607 * log_2(size) bits of the BAR will stick as 0 when we read
2608 * the value back.
2609 */
2610 pci_write_config(dev, reg, 0xffffffff, 4);
2611 testval = pci_read_config(dev, reg, 4);
2612 if (ln2range == 64) {
2613 pci_write_config(dev, reg + 4, 0xffffffff, 4);
2614 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2615 }
2616
2617 /*
2618 * Restore the original value of the BAR. We may have reprogrammed
2619 * the BAR of the low-level console device and when booting verbose,
2620 * we need the console device addressable.
2621 */
2622 pci_write_config(dev, reg, map, 4);
2623 if (ln2range == 64)
2624 pci_write_config(dev, reg + 4, map >> 32, 4);
2625 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2626
2627 *mapp = map;
2628 *testvalp = testval;
2629}
2630
2631static void
2632pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base)
2633{
2634 struct pci_devinfo *dinfo;
2635 int ln2range;
2636
2637 /* The device ROM BAR is always a 32-bit memory BAR. */
2638 dinfo = device_get_ivars(dev);
2639 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
2640 ln2range = 32;
2641 else
2642 ln2range = pci_maprange(pm->pm_value);
2643 pci_write_config(dev, pm->pm_reg, base, 4);
2644 if (ln2range == 64)
2645 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4);
2646 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4);
2647 if (ln2range == 64)
2648 pm->pm_value |= (pci_addr_t)pci_read_config(dev,
2649 pm->pm_reg + 4, 4) << 32;
2650}
2651
2652struct pci_map *
2653pci_find_bar(device_t dev, int reg)
2654{
2655 struct pci_devinfo *dinfo;
2656 struct pci_map *pm;
2657
2658 dinfo = device_get_ivars(dev);
2659 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
2660 if (pm->pm_reg == reg)
2661 return (pm);
2662 }
2663 return (NULL);
2664}
2665
2666int
2667pci_bar_enabled(device_t dev, struct pci_map *pm)
2668{
2669 struct pci_devinfo *dinfo;
2670 uint16_t cmd;
2671
2672 dinfo = device_get_ivars(dev);
2673 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) &&
2674 !(pm->pm_value & PCIM_BIOS_ENABLE))
2675 return (0);
2676 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2677 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value))
2678 return ((cmd & PCIM_CMD_MEMEN) != 0);
2679 else
2680 return ((cmd & PCIM_CMD_PORTEN) != 0);
2681}
2682
2683static struct pci_map *
2684pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size)
2685{
2686 struct pci_devinfo *dinfo;
2687 struct pci_map *pm, *prev;
2688
2689 dinfo = device_get_ivars(dev);
2690 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO);
2691 pm->pm_reg = reg;
2692 pm->pm_value = value;
2693 pm->pm_size = size;
2694 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) {
2695 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x",
2696 reg));
2697 if (STAILQ_NEXT(prev, pm_link) == NULL ||
2698 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg)
2699 break;
2700 }
2701 if (prev != NULL)
2702 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link);
2703 else
2704 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link);
2705 return (pm);
2706}
2707
2708static void
2709pci_restore_bars(device_t dev)
2710{
2711 struct pci_devinfo *dinfo;
2712 struct pci_map *pm;
2713 int ln2range;
2714
2715 dinfo = device_get_ivars(dev);
2716 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
2717 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
2718 ln2range = 32;
2719 else
2720 ln2range = pci_maprange(pm->pm_value);
2721 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4);
2722 if (ln2range == 64)
2723 pci_write_config(dev, pm->pm_reg + 4,
2724 pm->pm_value >> 32, 4);
2725 }
2726}
2727
2728/*
2729 * Add a resource based on a pci map register. Return 1 if the map
2730 * register is a 32bit map register or 2 if it is a 64bit register.
2731 */
2732static int
2733pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
2734 int force, int prefetch)
2735{
2736 struct pci_map *pm;
2737 pci_addr_t base, map, testval;
2738 pci_addr_t start, end, count;
2739 int barlen, basezero, maprange, mapsize, type;
2740 uint16_t cmd;
2741 struct resource *res;
2742
2743 /*
2744 * The BAR may already exist if the device is a CardBus card
2745 * whose CIS is stored in this BAR.
2746 */
2747 pm = pci_find_bar(dev, reg);
2748 if (pm != NULL) {
2749 maprange = pci_maprange(pm->pm_value);
2750 barlen = maprange == 64 ? 2 : 1;
2751 return (barlen);
2752 }
2753
2754 pci_read_bar(dev, reg, &map, &testval);
2755 if (PCI_BAR_MEM(map)) {
2756 type = SYS_RES_MEMORY;
2757 if (map & PCIM_BAR_MEM_PREFETCH)
2758 prefetch = 1;
2759 } else
2760 type = SYS_RES_IOPORT;
2761 mapsize = pci_mapsize(testval);
2762 base = pci_mapbase(map);
2763#ifdef __PCI_BAR_ZERO_VALID
2764 basezero = 0;
2765#else
2766 basezero = base == 0;
2767#endif
2768 maprange = pci_maprange(map);
2769 barlen = maprange == 64 ? 2 : 1;
2770
2771 /*
2772 * For I/O registers, if bottom bit is set, and the next bit up
2773 * isn't clear, we know we have a BAR that doesn't conform to the
2774 * spec, so ignore it. Also, sanity check the size of the data
2775 * areas to the type of memory involved. Memory must be at least
2776 * 16 bytes in size, while I/O ranges must be at least 4.
2777 */
2778 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2779 return (barlen);
2780 if ((type == SYS_RES_MEMORY && mapsize < 4) ||
2781 (type == SYS_RES_IOPORT && mapsize < 2))
2782 return (barlen);
2783
2784 /* Save a record of this BAR. */
2785 pm = pci_add_bar(dev, reg, map, mapsize);
2786 if (bootverbose) {
2787 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2788 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);
2789 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2790 printf(", port disabled\n");
2791 else if (type == SYS_RES_MEMORY && !pci_memen(dev))
2792 printf(", memory disabled\n");
2793 else
2794 printf(", enabled\n");
2795 }
2796
2797 /*
2798 * If base is 0, then we have problems if this architecture does
2799 * not allow that. It is best to ignore such entries for the
2800 * moment. These will be allocated later if the driver specifically
2801 * requests them. However, some removable busses look better when
2802 * all resources are allocated, so allow '0' to be overriden.
2803 *
2804 * Similarly treat maps whose values is the same as the test value
2805 * read back. These maps have had all f's written to them by the
2806 * BIOS in an attempt to disable the resources.
2807 */
2808 if (!force && (basezero || map == testval))
2809 return (barlen);
2810 if ((u_long)base != base) {
2811 device_printf(bus,
2812 "pci%d:%d:%d:%d bar %#x too many address bits",
2813 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
2814 pci_get_function(dev), reg);
2815 return (barlen);
2816 }
2817
2818 /*
2819 * This code theoretically does the right thing, but has
2820 * undesirable side effects in some cases where peripherals
2821 * respond oddly to having these bits enabled. Let the user
2822 * be able to turn them off (since pci_enable_io_modes is 1 by
2823 * default).
2824 */
2825 if (pci_enable_io_modes) {
2826 /* Turn on resources that have been left off by a lazy BIOS */
2827 if (type == SYS_RES_IOPORT && !pci_porten(dev)) {
2828 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2829 cmd |= PCIM_CMD_PORTEN;
2830 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2831 }
2832 if (type == SYS_RES_MEMORY && !pci_memen(dev)) {
2833 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2834 cmd |= PCIM_CMD_MEMEN;
2835 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2836 }
2837 } else {
2838 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2839 return (barlen);
2840 if (type == SYS_RES_MEMORY && !pci_memen(dev))
2841 return (barlen);
2842 }
2843
2844 count = (pci_addr_t)1 << mapsize;
2845 if (basezero || base == pci_mapbase(testval)) {
2846 start = 0; /* Let the parent decide. */
2847 end = ~0ul;
2848 } else {
2849 start = base;
2850 end = base + count - 1;
2851 }
2852 resource_list_add(rl, type, reg, start, end, count);
2853
2854 /*
2855 * Try to allocate the resource for this BAR from our parent
2856 * so that this resource range is already reserved. The
2857 * driver for this device will later inherit this resource in
2858 * pci_alloc_resource().
2859 */
2860 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count,
2861 prefetch ? RF_PREFETCHABLE : 0);
2862 if (pci_do_realloc_bars && res == NULL && (start != 0 || end != ~0ul)) {
2863 /*
2864 * If the allocation fails, try to allocate a resource for
2865 * this BAR using any available range. The firmware felt
2866 * it was important enough to assign a resource, so don't
2867 * disable decoding if we can help it.
2868 */
2869 resource_list_delete(rl, type, reg);
2870 resource_list_add(rl, type, reg, 0, ~0ul, count);
2871 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0ul,
2872 count, prefetch ? RF_PREFETCHABLE : 0);
2873 }
2874 if (res == NULL) {
2875 /*
2876 * If the allocation fails, delete the resource list entry
2877 * and disable decoding for this device.
2878 *
2879 * If the driver requests this resource in the future,
2880 * pci_reserve_map() will try to allocate a fresh
2881 * resource range.
2882 */
2883 resource_list_delete(rl, type, reg);
2884 pci_disable_io(dev, type);
2885 if (bootverbose)
2886 device_printf(bus,
2887 "pci%d:%d:%d:%d bar %#x failed to allocate\n",
2888 pci_get_domain(dev), pci_get_bus(dev),
2889 pci_get_slot(dev), pci_get_function(dev), reg);
2890 } else {
2891 start = rman_get_start(res);
2892 pci_write_bar(dev, pm, start);
2893 }
2894 return (barlen);
2895}
2896
2897/*
2898 * For ATA devices we need to decide early what addressing mode to use.
2899 * Legacy demands that the primary and secondary ATA ports sits on the
2900 * same addresses that old ISA hardware did. This dictates that we use
2901 * those addresses and ignore the BAR's if we cannot set PCI native
2902 * addressing mode.
2903 */
2904static void
2905pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
2906 uint32_t prefetchmask)
2907{
2908 struct resource *r;
2909 int rid, type, progif;
2910#if 0
2911 /* if this device supports PCI native addressing use it */
2912 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2913 if ((progif & 0x8a) == 0x8a) {
2914 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2915 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2916 printf("Trying ATA native PCI addressing mode\n");
2917 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2918 }
2919 }
2920#endif
2921 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2922 type = SYS_RES_IOPORT;
2923 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2924 pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
2925 prefetchmask & (1 << 0));
2926 pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
2927 prefetchmask & (1 << 1));
2928 } else {
2929 rid = PCIR_BAR(0);
2930 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2931 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0,
2932 0x1f7, 8, 0);
2933 rid = PCIR_BAR(1);
2934 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2935 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6,
2936 0x3f6, 1, 0);
2937 }
2938 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2939 pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
2940 prefetchmask & (1 << 2));
2941 pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
2942 prefetchmask & (1 << 3));
2943 } else {
2944 rid = PCIR_BAR(2);
2945 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2946 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x170,
2947 0x177, 8, 0);
2948 rid = PCIR_BAR(3);
2949 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2950 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x376,
2951 0x376, 1, 0);
2952 }
2953 pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
2954 prefetchmask & (1 << 4));
2955 pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
2956 prefetchmask & (1 << 5));
2957}
2958
2959static void
2960pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2961{
2962 struct pci_devinfo *dinfo = device_get_ivars(dev);
2963 pcicfgregs *cfg = &dinfo->cfg;
2964 char tunable_name[64];
2965 int irq;
2966
2967 /* Has to have an intpin to have an interrupt. */
2968 if (cfg->intpin == 0)
2969 return;
2970
2971 /* Let the user override the IRQ with a tunable. */
2972 irq = PCI_INVALID_IRQ;
2973 snprintf(tunable_name, sizeof(tunable_name),
2974 "hw.pci%d.%d.%d.INT%c.irq",
2975 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2976 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2977 irq = PCI_INVALID_IRQ;
2978
2979 /*
2980 * If we didn't get an IRQ via the tunable, then we either use the
2981 * IRQ value in the intline register or we ask the bus to route an
2982 * interrupt for us. If force_route is true, then we only use the
2983 * value in the intline register if the bus was unable to assign an
2984 * IRQ.
2985 */
2986 if (!PCI_INTERRUPT_VALID(irq)) {
2987 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2988 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2989 if (!PCI_INTERRUPT_VALID(irq))
2990 irq = cfg->intline;
2991 }
2992
2993 /* If after all that we don't have an IRQ, just bail. */
2994 if (!PCI_INTERRUPT_VALID(irq))
2995 return;
2996
2997 /* Update the config register if it changed. */
2998 if (irq != cfg->intline) {
2999 cfg->intline = irq;
3000 pci_write_config(dev, PCIR_INTLINE, irq, 1);
3001 }
3002
3003 /* Add this IRQ as rid 0 interrupt resource. */
3004 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
3005}
3006
3007/* Perform early OHCI takeover from SMM. */
3008static void
3009ohci_early_takeover(device_t self)
3010{
3011 struct resource *res;
3012 uint32_t ctl;
3013 int rid;
3014 int i;
3015
3016 rid = PCIR_BAR(0);
3017 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3018 if (res == NULL)
3019 return;
3020
3021 ctl = bus_read_4(res, OHCI_CONTROL);
3022 if (ctl & OHCI_IR) {
3023 if (bootverbose)
3024 printf("ohci early: "
3025 "SMM active, request owner change\n");
3026 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR);
3027 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) {
3028 DELAY(1000);
3029 ctl = bus_read_4(res, OHCI_CONTROL);
3030 }
3031 if (ctl & OHCI_IR) {
3032 if (bootverbose)
3033 printf("ohci early: "
3034 "SMM does not respond, resetting\n");
3035 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET);
3036 }
3037 /* Disable interrupts */
3038 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
3039 }
3040
3041 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3042}
3043
3044/* Perform early UHCI takeover from SMM. */
3045static void
3046uhci_early_takeover(device_t self)
3047{
3048 struct resource *res;
3049 int rid;
3050
3051 /*
3052 * Set the PIRQD enable bit and switch off all the others. We don't
3053 * want legacy support to interfere with us XXX Does this also mean
3054 * that the BIOS won't touch the keyboard anymore if it is connected
3055 * to the ports of the root hub?
3056 */
3057 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2);
3058
3059 /* Disable interrupts */
3060 rid = PCI_UHCI_BASE_REG;
3061 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE);
3062 if (res != NULL) {
3063 bus_write_2(res, UHCI_INTR, 0);
3064 bus_release_resource(self, SYS_RES_IOPORT, rid, res);
3065 }
3066}
3067
3068/* Perform early EHCI takeover from SMM. */
3069static void
3070ehci_early_takeover(device_t self)
3071{
3072 struct resource *res;
3073 uint32_t cparams;
3074 uint32_t eec;
3075 uint8_t eecp;
3076 uint8_t bios_sem;
3077 uint8_t offs;
3078 int rid;
3079 int i;
3080
3081 rid = PCIR_BAR(0);
3082 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3083 if (res == NULL)
3084 return;
3085
3086 cparams = bus_read_4(res, EHCI_HCCPARAMS);
3087
3088 /* Synchronise with the BIOS if it owns the controller. */
3089 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0;
3090 eecp = EHCI_EECP_NEXT(eec)) {
3091 eec = pci_read_config(self, eecp, 4);
3092 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) {
3093 continue;
3094 }
3095 bios_sem = pci_read_config(self, eecp +
3096 EHCI_LEGSUP_BIOS_SEM, 1);
3097 if (bios_sem == 0) {
3098 continue;
3099 }
3100 if (bootverbose)
3101 printf("ehci early: "
3102 "SMM active, request owner change\n");
3103
3104 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1);
3105
3106 for (i = 0; (i < 100) && (bios_sem != 0); i++) {
3107 DELAY(1000);
3108 bios_sem = pci_read_config(self, eecp +
3109 EHCI_LEGSUP_BIOS_SEM, 1);
3110 }
3111
3112 if (bios_sem != 0) {
3113 if (bootverbose)
3114 printf("ehci early: "
3115 "SMM does not respond\n");
3116 }
3117 /* Disable interrupts */
3118 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION));
3119 bus_write_4(res, offs + EHCI_USBINTR, 0);
3120 }
3121 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3122}
3123
3124/* Perform early XHCI takeover from SMM. */
3125static void
3126xhci_early_takeover(device_t self)
3127{
3128 struct resource *res;
3129 uint32_t cparams;
3130 uint32_t eec;
3131 uint8_t eecp;
3132 uint8_t bios_sem;
3133 uint8_t offs;
3134 int rid;
3135 int i;
3136
3137 rid = PCIR_BAR(0);
3138 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3139 if (res == NULL)
3140 return;
3141
3142 cparams = bus_read_4(res, XHCI_HCSPARAMS0);
3143
3144 eec = -1;
3145
3146 /* Synchronise with the BIOS if it owns the controller. */
3147 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
3148 eecp += XHCI_XECP_NEXT(eec) << 2) {
3149 eec = bus_read_4(res, eecp);
3150
3151 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
3152 continue;
3153
3154 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM);
3155 if (bios_sem == 0)
3156 continue;
3157
3158 if (bootverbose)
3159 printf("xhci early: "
3160 "SMM active, request owner change\n");
3161
3162 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1);
3163
3164 /* wait a maximum of 5 second */
3165
3166 for (i = 0; (i < 5000) && (bios_sem != 0); i++) {
3167 DELAY(1000);
3168 bios_sem = bus_read_1(res, eecp +
3169 XHCI_XECP_BIOS_SEM);
3170 }
3171
3172 if (bios_sem != 0) {
3173 if (bootverbose)
3174 printf("xhci early: "
3175 "SMM does not respond\n");
3176 }
3177
3178 /* Disable interrupts */
3179 offs = bus_read_1(res, XHCI_CAPLENGTH);
3180 bus_write_4(res, offs + XHCI_USBCMD, 0);
3181 bus_read_4(res, offs + XHCI_USBSTS);
3182 }
3183 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3184}
3185
3186void
3187pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
3188{
3189 struct pci_devinfo *dinfo;
3190 pcicfgregs *cfg;
3191 struct resource_list *rl;
3192 const struct pci_quirk *q;
3193 uint32_t devid;
3194 int i;
3195
3196 dinfo = device_get_ivars(dev);
3197 cfg = &dinfo->cfg;
3198 rl = &dinfo->resources;
3199 devid = (cfg->device << 16) | cfg->vendor;
3200
3201 /* ATA devices needs special map treatment */
3202 if ((pci_get_class(dev) == PCIC_STORAGE) &&
3203 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
3204 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
3205 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
3206 !pci_read_config(dev, PCIR_BAR(2), 4))) )
3207 pci_ata_maps(bus, dev, rl, force, prefetchmask);
3208 else
3209 for (i = 0; i < cfg->nummaps;) {
3210 /*
3211 * Skip quirked resources.
3212 */
3213 for (q = &pci_quirks[0]; q->devid != 0; q++)
3214 if (q->devid == devid &&
3215 q->type == PCI_QUIRK_UNMAP_REG &&
3216 q->arg1 == PCIR_BAR(i))
3217 break;
3218 if (q->devid != 0) {
3219 i++;
3220 continue;
3221 }
3222 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force,
3223 prefetchmask & (1 << i));
3224 }
3225
3226 /*
3227 * Add additional, quirked resources.
3228 */
3229 for (q = &pci_quirks[0]; q->devid != 0; q++)
3230 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG)
3231 pci_add_map(bus, dev, q->arg1, rl, force, 0);
3232
3233 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
3234#ifdef __PCI_REROUTE_INTERRUPT
3235 /*
3236 * Try to re-route interrupts. Sometimes the BIOS or
3237 * firmware may leave bogus values in these registers.
3238 * If the re-route fails, then just stick with what we
3239 * have.
3240 */
3241 pci_assign_interrupt(bus, dev, 1);
3242#else
3243 pci_assign_interrupt(bus, dev, 0);
3244#endif
3245 }
3246
3247 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS &&
3248 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
3249 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI)
3250 xhci_early_takeover(dev);
3251 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
3252 ehci_early_takeover(dev);
3253 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
3254 ohci_early_takeover(dev);
3255 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI)
3256 uhci_early_takeover(dev);
3257 }
3258}
3259
3260void
3261pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
3262{
3263#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
3264 device_t pcib = device_get_parent(dev);
3265 struct pci_devinfo *dinfo;
3266 int maxslots;
3267 int s, f, pcifunchigh;
3268 uint8_t hdrtype;
3269
3270 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
3271 ("dinfo_size too small"));
3272 maxslots = PCIB_MAXSLOTS(pcib);
3273 for (s = 0; s <= maxslots; s++) {
3274 pcifunchigh = 0;
3275 f = 0;
3276 DELAY(1);
3277 hdrtype = REG(PCIR_HDRTYPE, 1);
3278 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
3279 continue;
3280 if (hdrtype & PCIM_MFDEV)
3281 pcifunchigh = PCI_FUNCMAX;
3282 for (f = 0; f <= pcifunchigh; f++) {
3283 dinfo = pci_read_device(pcib, domain, busno, s, f,
3284 dinfo_size);
3285 if (dinfo != NULL) {
3286 pci_add_child(dev, dinfo);
3287 }
3288 }
3289 }
3290#undef REG
3291}
3292
3293void
3294pci_add_child(device_t bus, struct pci_devinfo *dinfo)
3295{
3296 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
3297 device_set_ivars(dinfo->cfg.dev, dinfo);
3298 resource_list_init(&dinfo->resources);
3299 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
3300 pci_cfg_restore(dinfo->cfg.dev, dinfo);
3301 pci_print_verbose(dinfo);
3302 pci_add_resources(bus, dinfo->cfg.dev, 0, 0);
3303}
3304
3305static int
3306pci_probe(device_t dev)
3307{
3308
3309 device_set_desc(dev, "PCI bus");
3310
3311 /* Allow other subclasses to override this driver. */
3312 return (BUS_PROBE_GENERIC);
3313}
3314
3315int
3316pci_attach_common(device_t dev)
3317{
3318 struct pci_softc *sc;
3319 int busno, domain;
3320#ifdef PCI_DMA_BOUNDARY
3321 int error, tag_valid;
3322#endif
3323
3324 sc = device_get_softc(dev);
3325 domain = pcib_get_domain(dev);
3326 busno = pcib_get_bus(dev);
3327 if (bootverbose)
3328 device_printf(dev, "domain=%d, physical bus=%d\n",
3329 domain, busno);
3330#ifdef PCI_DMA_BOUNDARY
3331 tag_valid = 0;
3332 if (device_get_devclass(device_get_parent(device_get_parent(dev))) !=
3333 devclass_find("pci")) {
3334 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1,
3335 PCI_DMA_BOUNDARY, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3336 NULL, NULL, BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED,
3337 BUS_SPACE_MAXSIZE, 0, NULL, NULL, &sc->sc_dma_tag);
3338 if (error)
3339 device_printf(dev, "Failed to create DMA tag: %d\n",
3340 error);
3341 else
3342 tag_valid = 1;
3343 }
3344 if (!tag_valid)
3345#endif
3346 sc->sc_dma_tag = bus_get_dma_tag(dev);
3347 return (0);
3348}
3349
3350static int
3351pci_attach(device_t dev)
3352{
3353 int busno, domain, error;
3354
3355 error = pci_attach_common(dev);
3356 if (error)
3357 return (error);
3358
3359 /*
3360 * Since there can be multiple independantly numbered PCI
3361 * busses on systems with multiple PCI domains, we can't use
3362 * the unit number to decide which bus we are probing. We ask
3363 * the parent pcib what our domain and bus numbers are.
3364 */
3365 domain = pcib_get_domain(dev);
3366 busno = pcib_get_bus(dev);
3367 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
3368 return (bus_generic_attach(dev));
3369}
3370
3371static void
3372pci_set_power_children(device_t dev, device_t *devlist, int numdevs,
3373 int state)
3374{
3375 device_t child, pcib;
3376 struct pci_devinfo *dinfo;
3377 int dstate, i;
3378
3379 /*
3380 * Set the device to the given state. If the firmware suggests
3381 * a different power state, use it instead. If power management
3382 * is not present, the firmware is responsible for managing
3383 * device power. Skip children who aren't attached since they
3384 * are handled separately.
3385 */
3386 pcib = device_get_parent(dev);
3387 for (i = 0; i < numdevs; i++) {
3388 child = devlist[i];
3389 dinfo = device_get_ivars(child);
3390 dstate = state;
3391 if (device_is_attached(child) &&
3392 PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0)
3393 pci_set_powerstate(child, dstate);
3394 }
3395}
3396
3397int
3398pci_suspend(device_t dev)
3399{
3400 device_t child, *devlist;
3401 struct pci_devinfo *dinfo;
3402 int error, i, numdevs;
3403
3404 /*
3405 * Save the PCI configuration space for each child and set the
3406 * device in the appropriate power state for this sleep state.
3407 */
3408 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
3409 return (error);
3410 for (i = 0; i < numdevs; i++) {
3411 child = devlist[i];
3412 dinfo = device_get_ivars(child);
3413 pci_cfg_save(child, dinfo, 0);
3414 }
3415
3416 /* Suspend devices before potentially powering them down. */
3417 error = bus_generic_suspend(dev);
3418 if (error) {
3419 free(devlist, M_TEMP);
3420 return (error);
3421 }
3422 if (pci_do_power_suspend)
3423 pci_set_power_children(dev, devlist, numdevs,
3424 PCI_POWERSTATE_D3);
3425 free(devlist, M_TEMP);
3426 return (0);
3427}
3428
3429int
3430pci_resume(device_t dev)
3431{
3432 device_t child, *devlist;
3433 struct pci_devinfo *dinfo;
3434 int error, i, numdevs;
3435
3436 /*
3437 * Set each child to D0 and restore its PCI configuration space.
3438 */
3439 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
3440 return (error);
3441 if (pci_do_power_resume)
3442 pci_set_power_children(dev, devlist, numdevs,
3443 PCI_POWERSTATE_D0);
3444
3445 /* Now the device is powered up, restore its config space. */
3446 for (i = 0; i < numdevs; i++) {
3447 child = devlist[i];
3448 dinfo = device_get_ivars(child);
3449
3450 pci_cfg_restore(child, dinfo);
3451 if (!device_is_attached(child))
3452 pci_cfg_save(child, dinfo, 1);
3453 }
3454
3455 /*
3456 * Resume critical devices first, then everything else later.
3457 */
3458 for (i = 0; i < numdevs; i++) {
3459 child = devlist[i];
3460 switch (pci_get_class(child)) {
3461 case PCIC_DISPLAY:
3462 case PCIC_MEMORY:
3463 case PCIC_BRIDGE:
3464 case PCIC_BASEPERIPH:
3465 DEVICE_RESUME(child);
3466 break;
3467 }
3468 }
3469 for (i = 0; i < numdevs; i++) {
3470 child = devlist[i];
3471 switch (pci_get_class(child)) {
3472 case PCIC_DISPLAY:
3473 case PCIC_MEMORY:
3474 case PCIC_BRIDGE:
3475 case PCIC_BASEPERIPH:
3476 break;
3477 default:
3478 DEVICE_RESUME(child);
3479 }
3480 }
3481 free(devlist, M_TEMP);
3482 return (0);
3483}
3484
3485static void
3486pci_load_vendor_data(void)
3487{
3488 caddr_t data;
3489 void *ptr;
3490 size_t sz;
3491
3492 data = preload_search_by_type("pci_vendor_data");
3493 if (data != NULL) {
3494 ptr = preload_fetch_addr(data);
3495 sz = preload_fetch_size(data);
3496 if (ptr != NULL && sz != 0) {
3497 pci_vendordata = ptr;
3498 pci_vendordata_size = sz;
3499 /* terminate the database */
3500 pci_vendordata[pci_vendordata_size] = '\n';
3501 }
3502 }
3503}
3504
3505void
3506pci_driver_added(device_t dev, driver_t *driver)
3507{
3508 int numdevs;
3509 device_t *devlist;
3510 device_t child;
3511 struct pci_devinfo *dinfo;
3512 int i;
3513
3514 if (bootverbose)
3515 device_printf(dev, "driver added\n");
3516 DEVICE_IDENTIFY(driver, dev);
3517 if (device_get_children(dev, &devlist, &numdevs) != 0)
3518 return;
3519 for (i = 0; i < numdevs; i++) {
3520 child = devlist[i];
3521 if (device_get_state(child) != DS_NOTPRESENT)
3522 continue;
3523 dinfo = device_get_ivars(child);
3524 pci_print_verbose(dinfo);
3525 if (bootverbose)
3526 pci_printf(&dinfo->cfg, "reprobing on driver added\n");
3527 pci_cfg_restore(child, dinfo);
3528 if (device_probe_and_attach(child) != 0)
3529 pci_child_detached(dev, child);
3530 }
3531 free(devlist, M_TEMP);
3532}
3533
3534int
3535pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3536 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep)
3537{
3538 struct pci_devinfo *dinfo;
3539 struct msix_table_entry *mte;
3540 struct msix_vector *mv;
3541 uint64_t addr;
3542 uint32_t data;
3543 void *cookie;
3544 int error, rid;
3545
3546 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr,
3547 arg, &cookie);
3548 if (error)
3549 return (error);
3550
3551 /* If this is not a direct child, just bail out. */
3552 if (device_get_parent(child) != dev) {
3553 *cookiep = cookie;
3554 return(0);
3555 }
3556
3557 rid = rman_get_rid(irq);
3558 if (rid == 0) {
3559 /* Make sure that INTx is enabled */
3560 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3561 } else {
3562 /*
3563 * Check to see if the interrupt is MSI or MSI-X.
3564 * Ask our parent to map the MSI and give
3565 * us the address and data register values.
3566 * If we fail for some reason, teardown the
3567 * interrupt handler.
3568 */
3569 dinfo = device_get_ivars(child);
3570 if (dinfo->cfg.msi.msi_alloc > 0) {
3571 if (dinfo->cfg.msi.msi_addr == 0) {
3572 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3573 ("MSI has handlers, but vectors not mapped"));
3574 error = PCIB_MAP_MSI(device_get_parent(dev),
3575 child, rman_get_start(irq), &addr, &data);
3576 if (error)
3577 goto bad;
3578 dinfo->cfg.msi.msi_addr = addr;
3579 dinfo->cfg.msi.msi_data = data;
3580 }
3581 if (dinfo->cfg.msi.msi_handlers == 0)
3582 pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
3583 dinfo->cfg.msi.msi_data);
3584 dinfo->cfg.msi.msi_handlers++;
3585 } else {
3586 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3587 ("No MSI or MSI-X interrupts allocated"));
3588 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3589 ("MSI-X index too high"));
3590 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3591 KASSERT(mte->mte_vector != 0, ("no message vector"));
3592 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3593 KASSERT(mv->mv_irq == rman_get_start(irq),
3594 ("IRQ mismatch"));
3595 if (mv->mv_address == 0) {
3596 KASSERT(mte->mte_handlers == 0,
3597 ("MSI-X table entry has handlers, but vector not mapped"));
3598 error = PCIB_MAP_MSI(device_get_parent(dev),
3599 child, rman_get_start(irq), &addr, &data);
3600 if (error)
3601 goto bad;
3602 mv->mv_address = addr;
3603 mv->mv_data = data;
3604 }
3605 if (mte->mte_handlers == 0) {
3606 pci_enable_msix(child, rid - 1, mv->mv_address,
3607 mv->mv_data);
3608 pci_unmask_msix(child, rid - 1);
3609 }
3610 mte->mte_handlers++;
3611 }
3612
3613 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3614 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3615 bad:
3616 if (error) {
3617 (void)bus_generic_teardown_intr(dev, child, irq,
3618 cookie);
3619 return (error);
3620 }
3621 }
3622 *cookiep = cookie;
3623 return (0);
3624}
3625
3626int
3627pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3628 void *cookie)
3629{
3630 struct msix_table_entry *mte;
3631 struct resource_list_entry *rle;
3632 struct pci_devinfo *dinfo;
3633 int error, rid;
3634
3635 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3636 return (EINVAL);
3637
3638 /* If this isn't a direct child, just bail out */
3639 if (device_get_parent(child) != dev)
3640 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3641
3642 rid = rman_get_rid(irq);
3643 if (rid == 0) {
3644 /* Mask INTx */
3645 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3646 } else {
3647 /*
3648 * Check to see if the interrupt is MSI or MSI-X. If so,
3649 * decrement the appropriate handlers count and mask the
3650 * MSI-X message, or disable MSI messages if the count
3651 * drops to 0.
3652 */
3653 dinfo = device_get_ivars(child);
3654 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3655 if (rle->res != irq)
3656 return (EINVAL);
3657 if (dinfo->cfg.msi.msi_alloc > 0) {
3658 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3659 ("MSI-X index too high"));
3660 if (dinfo->cfg.msi.msi_handlers == 0)
3661 return (EINVAL);
3662 dinfo->cfg.msi.msi_handlers--;
3663 if (dinfo->cfg.msi.msi_handlers == 0)
3664 pci_disable_msi(child);
3665 } else {
3666 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3667 ("No MSI or MSI-X interrupts allocated"));
3668 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3669 ("MSI-X index too high"));
3670 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3671 if (mte->mte_handlers == 0)
3672 return (EINVAL);
3673 mte->mte_handlers--;
3674 if (mte->mte_handlers == 0)
3675 pci_mask_msix(child, rid - 1);
3676 }
3677 }
3678 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3679 if (rid > 0)
3680 KASSERT(error == 0,
3681 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3682 return (error);
3683}
3684
3685int
3686pci_print_child(device_t dev, device_t child)
3687{
3688 struct pci_devinfo *dinfo;
3689 struct resource_list *rl;
3690 int retval = 0;
3691
3692 dinfo = device_get_ivars(child);
3693 rl = &dinfo->resources;
3694
3695 retval += bus_print_child_header(dev, child);
3696
3697 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3698 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3699 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3700 if (device_get_flags(dev))
3701 retval += printf(" flags %#x", device_get_flags(dev));
3702
3703 retval += printf(" at device %d.%d", pci_get_slot(child),
3704 pci_get_function(child));
3705
3706 retval += bus_print_child_footer(dev, child);
3707
3708 return (retval);
3709}
3710
3711static const struct
3712{
3713 int class;
3714 int subclass;
3715 const char *desc;
3716} pci_nomatch_tab[] = {
3717 {PCIC_OLD, -1, "old"},
3718 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3719 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3720 {PCIC_STORAGE, -1, "mass storage"},
3721 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3722 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3723 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3724 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3725 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3726 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3727 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3728 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3729 {PCIC_STORAGE, PCIS_STORAGE_NVM, "NVM"},
3730 {PCIC_NETWORK, -1, "network"},
3731 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3732 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3733 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3734 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3735 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3736 {PCIC_DISPLAY, -1, "display"},
3737 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3738 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3739 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3740 {PCIC_MULTIMEDIA, -1, "multimedia"},
3741 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3742 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3743 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3744 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3745 {PCIC_MEMORY, -1, "memory"},
3746 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3747 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3748 {PCIC_BRIDGE, -1, "bridge"},
3749 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3750 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3751 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3752 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3753 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3754 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3755 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3756 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3757 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3758 {PCIC_SIMPLECOMM, -1, "simple comms"},
3759 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3760 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3761 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3762 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3763 {PCIC_BASEPERIPH, -1, "base peripheral"},
3764 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3765 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3766 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3767 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3768 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3769 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3770 {PCIC_INPUTDEV, -1, "input device"},
3771 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3772 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3773 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3774 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3775 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3776 {PCIC_DOCKING, -1, "docking station"},
3777 {PCIC_PROCESSOR, -1, "processor"},
3778 {PCIC_SERIALBUS, -1, "serial bus"},
3779 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3780 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3781 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3782 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3783 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3784 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3785 {PCIC_WIRELESS, -1, "wireless controller"},
3786 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3787 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3788 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3789 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3790 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3791 {PCIC_SATCOM, -1, "satellite communication"},
3792 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3793 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3794 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3795 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3796 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3797 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3798 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3799 {PCIC_DASP, -1, "dasp"},
3800 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3801 {0, 0, NULL}
3802};
3803
3804void
3805pci_probe_nomatch(device_t dev, device_t child)
3806{
3807 int i;
3808 const char *cp, *scp;
3809 char *device;
3810
3811 /*
3812 * Look for a listing for this device in a loaded device database.
3813 */
3814 if ((device = pci_describe_device(child)) != NULL) {
3815 device_printf(dev, "<%s>", device);
3816 free(device, M_DEVBUF);
3817 } else {
3818 /*
3819 * Scan the class/subclass descriptions for a general
3820 * description.
3821 */
3822 cp = "unknown";
3823 scp = NULL;
3824 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3825 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3826 if (pci_nomatch_tab[i].subclass == -1) {
3827 cp = pci_nomatch_tab[i].desc;
3828 } else if (pci_nomatch_tab[i].subclass ==
3829 pci_get_subclass(child)) {
3830 scp = pci_nomatch_tab[i].desc;
3831 }
3832 }
3833 }
3834 device_printf(dev, "<%s%s%s>",
3835 cp ? cp : "",
3836 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3837 scp ? scp : "");
3838 }
3839 printf(" at device %d.%d (no driver attached)\n",
3840 pci_get_slot(child), pci_get_function(child));
3841 pci_cfg_save(child, device_get_ivars(child), 1);
3842}
3843
3844void
3845pci_child_detached(device_t dev, device_t child)
3846{
3847 struct pci_devinfo *dinfo;
3848 struct resource_list *rl;
3849
3850 dinfo = device_get_ivars(child);
3851 rl = &dinfo->resources;
3852
3853 /*
3854 * Have to deallocate IRQs before releasing any MSI messages and
3855 * have to release MSI messages before deallocating any memory
3856 * BARs.
3857 */
3858 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0)
3859 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n");
3860 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) {
3861 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n");
3862 (void)pci_release_msi(child);
3863 }
3864 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0)
3865 pci_printf(&dinfo->cfg, "Device leaked memory resources\n");
3866 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0)
3867 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n");
3868
3869 pci_cfg_save(child, dinfo, 1);
3870}
3871
3872/*
3873 * Parse the PCI device database, if loaded, and return a pointer to a
3874 * description of the device.
3875 *
3876 * The database is flat text formatted as follows:
3877 *
3878 * Any line not in a valid format is ignored.
3879 * Lines are terminated with newline '\n' characters.
3880 *
3881 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3882 * the vendor name.
3883 *
3884 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3885 * - devices cannot be listed without a corresponding VENDOR line.
3886 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3887 * another TAB, then the device name.
3888 */
3889
3890/*
3891 * Assuming (ptr) points to the beginning of a line in the database,
3892 * return the vendor or device and description of the next entry.
3893 * The value of (vendor) or (device) inappropriate for the entry type
3894 * is set to -1. Returns nonzero at the end of the database.
3895 *
3896 * Note that this is slightly unrobust in the face of corrupt data;
3897 * we attempt to safeguard against this by spamming the end of the
3898 * database with a newline when we initialise.
3899 */
3900static int
3901pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3902{
3903 char *cp = *ptr;
3904 int left;
3905
3906 *device = -1;
3907 *vendor = -1;
3908 **desc = '\0';
3909 for (;;) {
3910 left = pci_vendordata_size - (cp - pci_vendordata);
3911 if (left <= 0) {
3912 *ptr = cp;
3913 return(1);
3914 }
3915
3916 /* vendor entry? */
3917 if (*cp != '\t' &&
3918 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3919 break;
3920 /* device entry? */
3921 if (*cp == '\t' &&
3922 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3923 break;
3924
3925 /* skip to next line */
3926 while (*cp != '\n' && left > 0) {
3927 cp++;
3928 left--;
3929 }
3930 if (*cp == '\n') {
3931 cp++;
3932 left--;
3933 }
3934 }
3935 /* skip to next line */
3936 while (*cp != '\n' && left > 0) {
3937 cp++;
3938 left--;
3939 }
3940 if (*cp == '\n' && left > 0)
3941 cp++;
3942 *ptr = cp;
3943 return(0);
3944}
3945
3946static char *
3947pci_describe_device(device_t dev)
3948{
3949 int vendor, device;
3950 char *desc, *vp, *dp, *line;
3951
3952 desc = vp = dp = NULL;
3953
3954 /*
3955 * If we have no vendor data, we can't do anything.
3956 */
3957 if (pci_vendordata == NULL)
3958 goto out;
3959
3960 /*
3961 * Scan the vendor data looking for this device
3962 */
3963 line = pci_vendordata;
3964 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3965 goto out;
3966 for (;;) {
3967 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3968 goto out;
3969 if (vendor == pci_get_vendor(dev))
3970 break;
3971 }
3972 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3973 goto out;
3974 for (;;) {
3975 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3976 *dp = 0;
3977 break;
3978 }
3979 if (vendor != -1) {
3980 *dp = 0;
3981 break;
3982 }
3983 if (device == pci_get_device(dev))
3984 break;
3985 }
3986 if (dp[0] == '\0')
3987 snprintf(dp, 80, "0x%x", pci_get_device(dev));
3988 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3989 NULL)
3990 sprintf(desc, "%s, %s", vp, dp);
3991out:
3992 if (vp != NULL)
3993 free(vp, M_DEVBUF);
3994 if (dp != NULL)
3995 free(dp, M_DEVBUF);
3996 return(desc);
3997}
3998
3999int
4000pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
4001{
4002 struct pci_devinfo *dinfo;
4003 pcicfgregs *cfg;
4004
4005 dinfo = device_get_ivars(child);
4006 cfg = &dinfo->cfg;
4007
4008 switch (which) {
4009 case PCI_IVAR_ETHADDR:
4010 /*
4011 * The generic accessor doesn't deal with failure, so
4012 * we set the return value, then return an error.
4013 */
4014 *((uint8_t **) result) = NULL;
4015 return (EINVAL);
4016 case PCI_IVAR_SUBVENDOR:
4017 *result = cfg->subvendor;
4018 break;
4019 case PCI_IVAR_SUBDEVICE:
4020 *result = cfg->subdevice;
4021 break;
4022 case PCI_IVAR_VENDOR:
4023 *result = cfg->vendor;
4024 break;
4025 case PCI_IVAR_DEVICE:
4026 *result = cfg->device;
4027 break;
4028 case PCI_IVAR_DEVID:
4029 *result = (cfg->device << 16) | cfg->vendor;
4030 break;
4031 case PCI_IVAR_CLASS:
4032 *result = cfg->baseclass;
4033 break;
4034 case PCI_IVAR_SUBCLASS:
4035 *result = cfg->subclass;
4036 break;
4037 case PCI_IVAR_PROGIF:
4038 *result = cfg->progif;
4039 break;
4040 case PCI_IVAR_REVID:
4041 *result = cfg->revid;
4042 break;
4043 case PCI_IVAR_INTPIN:
4044 *result = cfg->intpin;
4045 break;
4046 case PCI_IVAR_IRQ:
4047 *result = cfg->intline;
4048 break;
4049 case PCI_IVAR_DOMAIN:
4050 *result = cfg->domain;
4051 break;
4052 case PCI_IVAR_BUS:
4053 *result = cfg->bus;
4054 break;
4055 case PCI_IVAR_SLOT:
4056 *result = cfg->slot;
4057 break;
4058 case PCI_IVAR_FUNCTION:
4059 *result = cfg->func;
4060 break;
4061 case PCI_IVAR_CMDREG:
4062 *result = cfg->cmdreg;
4063 break;
4064 case PCI_IVAR_CACHELNSZ:
4065 *result = cfg->cachelnsz;
4066 break;
4067 case PCI_IVAR_MINGNT:
4068 *result = cfg->mingnt;
4069 break;
4070 case PCI_IVAR_MAXLAT:
4071 *result = cfg->maxlat;
4072 break;
4073 case PCI_IVAR_LATTIMER:
4074 *result = cfg->lattimer;
4075 break;
4076 default:
4077 return (ENOENT);
4078 }
4079 return (0);
4080}
4081
4082int
4083pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
4084{
4085 struct pci_devinfo *dinfo;
4086
4087 dinfo = device_get_ivars(child);
4088
4089 switch (which) {
4090 case PCI_IVAR_INTPIN:
4091 dinfo->cfg.intpin = value;
4092 return (0);
4093 case PCI_IVAR_ETHADDR:
4094 case PCI_IVAR_SUBVENDOR:
4095 case PCI_IVAR_SUBDEVICE:
4096 case PCI_IVAR_VENDOR:
4097 case PCI_IVAR_DEVICE:
4098 case PCI_IVAR_DEVID:
4099 case PCI_IVAR_CLASS:
4100 case PCI_IVAR_SUBCLASS:
4101 case PCI_IVAR_PROGIF:
4102 case PCI_IVAR_REVID:
4103 case PCI_IVAR_IRQ:
4104 case PCI_IVAR_DOMAIN:
4105 case PCI_IVAR_BUS:
4106 case PCI_IVAR_SLOT:
4107 case PCI_IVAR_FUNCTION:
4108 return (EINVAL); /* disallow for now */
4109
4110 default:
4111 return (ENOENT);
4112 }
4113}
4114
4115#include "opt_ddb.h"
4116#ifdef DDB
4117#include <ddb/ddb.h>
4118#include <sys/cons.h>
4119
4120/*
4121 * List resources based on pci map registers, used for within ddb
4122 */
4123
4124DB_SHOW_COMMAND(pciregs, db_pci_dump)
4125{
4126 struct pci_devinfo *dinfo;
4127 struct devlist *devlist_head;
4128 struct pci_conf *p;
4129 const char *name;
4130 int i, error, none_count;
4131
4132 none_count = 0;
4133 /* get the head of the device queue */
4134 devlist_head = &pci_devq;
4135
4136 /*
4137 * Go through the list of devices and print out devices
4138 */
4139 for (error = 0, i = 0,
4140 dinfo = STAILQ_FIRST(devlist_head);
4141 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
4142 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4143
4144 /* Populate pd_name and pd_unit */
4145 name = NULL;
4146 if (dinfo->cfg.dev)
4147 name = device_get_name(dinfo->cfg.dev);
4148
4149 p = &dinfo->conf;
4150 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
4151 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
4152 (name && *name) ? name : "none",
4153 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
4154 none_count++,
4155 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
4156 p->pc_sel.pc_func, (p->pc_class << 16) |
4157 (p->pc_subclass << 8) | p->pc_progif,
4158 (p->pc_subdevice << 16) | p->pc_subvendor,
4159 (p->pc_device << 16) | p->pc_vendor,
4160 p->pc_revid, p->pc_hdr);
4161 }
4162}
4163#endif /* DDB */
4164
4165static struct resource *
4166pci_reserve_map(device_t dev, device_t child, int type, int *rid,
4167 u_long start, u_long end, u_long count, u_int flags)
4168{
4169 struct pci_devinfo *dinfo = device_get_ivars(child);
4170 struct resource_list *rl = &dinfo->resources;
4171 struct resource_list_entry *rle;
4172 struct resource *res;
4173 struct pci_map *pm;
4174 pci_addr_t map, testval;
4175 int mapsize;
4176
4177 res = NULL;
4178 pm = pci_find_bar(child, *rid);
4179 if (pm != NULL) {
4180 /* This is a BAR that we failed to allocate earlier. */
4181 mapsize = pm->pm_size;
4182 map = pm->pm_value;
4183 } else {
4184 /*
4185 * Weed out the bogons, and figure out how large the
4186 * BAR/map is. BARs that read back 0 here are bogus
4187 * and unimplemented. Note: atapci in legacy mode are
4188 * special and handled elsewhere in the code. If you
4189 * have a atapci device in legacy mode and it fails
4190 * here, that other code is broken.
4191 */
4192 pci_read_bar(child, *rid, &map, &testval);
4193
4194 /*
4195 * Determine the size of the BAR and ignore BARs with a size
4196 * of 0. Device ROM BARs use a different mask value.
4197 */
4198 if (PCIR_IS_BIOS(&dinfo->cfg, *rid))
4199 mapsize = pci_romsize(testval);
4200 else
4201 mapsize = pci_mapsize(testval);
4202 if (mapsize == 0)
4203 goto out;
4204 pm = pci_add_bar(child, *rid, map, mapsize);
4205 }
4206
4207 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) {
4208 if (type != SYS_RES_MEMORY) {
4209 if (bootverbose)
4210 device_printf(dev,
4211 "child %s requested type %d for rid %#x,"
4212 " but the BAR says it is an memio\n",
4213 device_get_nameunit(child), type, *rid);
4214 goto out;
4215 }
4216 } else {
4217 if (type != SYS_RES_IOPORT) {
4218 if (bootverbose)
4219 device_printf(dev,
4220 "child %s requested type %d for rid %#x,"
4221 " but the BAR says it is an ioport\n",
4222 device_get_nameunit(child), type, *rid);
4223 goto out;
4224 }
4225 }
4226
4227 /*
4228 * For real BARs, we need to override the size that
4229 * the driver requests, because that's what the BAR
4230 * actually uses and we would otherwise have a
4231 * situation where we might allocate the excess to
4232 * another driver, which won't work.
4233 */
4234 count = (pci_addr_t)1 << mapsize;
4235 if (RF_ALIGNMENT(flags) < mapsize)
4236 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
4237 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH))
4238 flags |= RF_PREFETCHABLE;
4239
4240 /*
4241 * Allocate enough resource, and then write back the
4242 * appropriate BAR for that resource.
4243 */
4244 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
4245 start, end, count, flags & ~RF_ACTIVE);
4246 if (res == NULL) {
4247 device_printf(child,
4248 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
4249 count, *rid, type, start, end);
4250 goto out;
4251 }
4252 resource_list_add(rl, type, *rid, start, end, count);
4253 rle = resource_list_find(rl, type, *rid);
4254 if (rle == NULL)
4255 panic("pci_reserve_map: unexpectedly can't find resource.");
4256 rle->res = res;
4257 rle->start = rman_get_start(res);
4258 rle->end = rman_get_end(res);
4259 rle->count = count;
4260 rle->flags = RLE_RESERVED;
4261 if (bootverbose)
4262 device_printf(child,
4263 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
4264 count, *rid, type, rman_get_start(res));
4265 map = rman_get_start(res);
4266 pci_write_bar(child, pm, map);
4267out:
4268 return (res);
4269}
4270
4271struct resource *
4272pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
4273 u_long start, u_long end, u_long count, u_int flags)
4274{
4275 struct pci_devinfo *dinfo = device_get_ivars(child);
4276 struct resource_list *rl = &dinfo->resources;
4277 struct resource_list_entry *rle;
4278 struct resource *res;
4279 pcicfgregs *cfg = &dinfo->cfg;
4280
4281 if (device_get_parent(child) != dev)
4282 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
4283 type, rid, start, end, count, flags));
4284
4285 /*
4286 * Perform lazy resource allocation
4287 */
4288 switch (type) {
4289 case SYS_RES_IRQ:
4290 /*
4291 * Can't alloc legacy interrupt once MSI messages have
4292 * been allocated.
4293 */
4294 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
4295 cfg->msix.msix_alloc > 0))
4296 return (NULL);
4297
4298 /*
4299 * If the child device doesn't have an interrupt
4300 * routed and is deserving of an interrupt, try to
4301 * assign it one.
4302 */
4303 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
4304 (cfg->intpin != 0))
4305 pci_assign_interrupt(dev, child, 0);
4306 break;
4307 case SYS_RES_IOPORT:
4308 case SYS_RES_MEMORY:
4309#ifdef NEW_PCIB
4310 /*
4311 * PCI-PCI bridge I/O window resources are not BARs.
4312 * For those allocations just pass the request up the
4313 * tree.
4314 */
4315 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) {
4316 switch (*rid) {
4317 case PCIR_IOBASEL_1:
4318 case PCIR_MEMBASE_1:
4319 case PCIR_PMBASEL_1:
4320 /*
4321 * XXX: Should we bother creating a resource
4322 * list entry?
4323 */
4324 return (bus_generic_alloc_resource(dev, child,
4325 type, rid, start, end, count, flags));
4326 }
4327 }
4328#endif
4329 /* Reserve resources for this BAR if needed. */
4330 rle = resource_list_find(rl, type, *rid);
4331 if (rle == NULL) {
4332 res = pci_reserve_map(dev, child, type, rid, start, end,
4333 count, flags);
4334 if (res == NULL)
4335 return (NULL);
4336 }
4337 }
4338 return (resource_list_alloc(rl, dev, child, type, rid,
4339 start, end, count, flags));
4340}
4341
4342int
4343pci_activate_resource(device_t dev, device_t child, int type, int rid,
4344 struct resource *r)
4345{
4346 struct pci_devinfo *dinfo;
4347 int error;
4348
4349 error = bus_generic_activate_resource(dev, child, type, rid, r);
4350 if (error)
4351 return (error);
4352
4353 /* Enable decoding in the command register when activating BARs. */
4354 if (device_get_parent(child) == dev) {
4355 /* Device ROMs need their decoding explicitly enabled. */
4356 dinfo = device_get_ivars(child);
4357 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
4358 pci_write_bar(child, pci_find_bar(child, rid),
4359 rman_get_start(r) | PCIM_BIOS_ENABLE);
4360 switch (type) {
4361 case SYS_RES_IOPORT:
4362 case SYS_RES_MEMORY:
4363 error = PCI_ENABLE_IO(dev, child, type);
4364 break;
4365 }
4366 }
4367 return (error);
4368}
4369
4370int
4371pci_deactivate_resource(device_t dev, device_t child, int type,
4372 int rid, struct resource *r)
4373{
4374 struct pci_devinfo *dinfo;
4375 int error;
4376
4377 error = bus_generic_deactivate_resource(dev, child, type, rid, r);
4378 if (error)
4379 return (error);
4380
4381 /* Disable decoding for device ROMs. */
4382 if (device_get_parent(child) == dev) {
4383 dinfo = device_get_ivars(child);
4384 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
4385 pci_write_bar(child, pci_find_bar(child, rid),
4386 rman_get_start(r));
4387 }
4388 return (0);
4389}
4390
4391void
4392pci_delete_child(device_t dev, device_t child)
4393{
4394 struct resource_list_entry *rle;
4395 struct resource_list *rl;
4396 struct pci_devinfo *dinfo;
4397
4398 dinfo = device_get_ivars(child);
4399 rl = &dinfo->resources;
4400
4401 if (device_is_attached(child))
4402 device_detach(child);
4403
4404 /* Turn off access to resources we're about to free */
4405 pci_write_config(child, PCIR_COMMAND, pci_read_config(child,
4406 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2);
4407
4408 /* Free all allocated resources */
4409 STAILQ_FOREACH(rle, rl, link) {
4410 if (rle->res) {
4411 if (rman_get_flags(rle->res) & RF_ACTIVE ||
4412 resource_list_busy(rl, rle->type, rle->rid)) {
4413 pci_printf(&dinfo->cfg,
4414 "Resource still owned, oops. "
4415 "(type=%d, rid=%d, addr=%lx)\n",
4416 rle->type, rle->rid,
4417 rman_get_start(rle->res));
4418 bus_release_resource(child, rle->type, rle->rid,
4419 rle->res);
4420 }
4421 resource_list_unreserve(rl, dev, child, rle->type,
4422 rle->rid);
4423 }
4424 }
4425 resource_list_free(rl);
4426
4427 device_delete_child(dev, child);
4428 pci_freecfg(dinfo);
4429}
4430
4431void
4432pci_delete_resource(device_t dev, device_t child, int type, int rid)
4433{
4434 struct pci_devinfo *dinfo;
4435 struct resource_list *rl;
4436 struct resource_list_entry *rle;
4437
4438 if (device_get_parent(child) != dev)
4439 return;
4440
4441 dinfo = device_get_ivars(child);
4442 rl = &dinfo->resources;
4443 rle = resource_list_find(rl, type, rid);
4444 if (rle == NULL)
4445 return;
4446
4447 if (rle->res) {
4448 if (rman_get_flags(rle->res) & RF_ACTIVE ||
4449 resource_list_busy(rl, type, rid)) {
4450 device_printf(dev, "delete_resource: "
4451 "Resource still owned by child, oops. "
4452 "(type=%d, rid=%d, addr=%lx)\n",
4453 type, rid, rman_get_start(rle->res));
4454 return;
4455 }
4456 resource_list_unreserve(rl, dev, child, type, rid);
4457 }
4458 resource_list_delete(rl, type, rid);
4459}
4460
4461struct resource_list *
4462pci_get_resource_list (device_t dev, device_t child)
4463{
4464 struct pci_devinfo *dinfo = device_get_ivars(child);
4465
4466 return (&dinfo->resources);
4467}
4468
4469bus_dma_tag_t
4470pci_get_dma_tag(device_t bus, device_t dev)
4471{
4472 struct pci_softc *sc = device_get_softc(bus);
4473
4474 return (sc->sc_dma_tag);
4475}
4476
4477uint32_t
4478pci_read_config_method(device_t dev, device_t child, int reg, int width)
4479{
4480 struct pci_devinfo *dinfo = device_get_ivars(child);
4481 pcicfgregs *cfg = &dinfo->cfg;
4482
4483 return (PCIB_READ_CONFIG(device_get_parent(dev),
4484 cfg->bus, cfg->slot, cfg->func, reg, width));
4485}
4486
4487void
4488pci_write_config_method(device_t dev, device_t child, int reg,
4489 uint32_t val, int width)
4490{
4491 struct pci_devinfo *dinfo = device_get_ivars(child);
4492 pcicfgregs *cfg = &dinfo->cfg;
4493
4494 PCIB_WRITE_CONFIG(device_get_parent(dev),
4495 cfg->bus, cfg->slot, cfg->func, reg, val, width);
4496}
4497
4498int
4499pci_child_location_str_method(device_t dev, device_t child, char *buf,
4500 size_t buflen)
4501{
4502
4503 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
4504 pci_get_function(child));
4505 return (0);
4506}
4507
4508int
4509pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
4510 size_t buflen)
4511{
4512 struct pci_devinfo *dinfo;
4513 pcicfgregs *cfg;
4514
4515 dinfo = device_get_ivars(child);
4516 cfg = &dinfo->cfg;
4517 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
4518 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
4519 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
4520 cfg->progif);
4521 return (0);
4522}
4523
4524int
4525pci_assign_interrupt_method(device_t dev, device_t child)
4526{
4527 struct pci_devinfo *dinfo = device_get_ivars(child);
4528 pcicfgregs *cfg = &dinfo->cfg;
4529
4530 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
4531 cfg->intpin));
4532}
4533
4534static int
4535pci_modevent(module_t mod, int what, void *arg)
4536{
4537 static struct cdev *pci_cdev;
4538
4539 switch (what) {
4540 case MOD_LOAD:
4541 STAILQ_INIT(&pci_devq);
4542 pci_generation = 0;
4543 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
4544 "pci");
4545 pci_load_vendor_data();
4546 break;
4547
4548 case MOD_UNLOAD:
4549 destroy_dev(pci_cdev);
4550 break;
4551 }
4552
4553 return (0);
4554}
4555
4556static void
4557pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo)
4558{
4559#define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2)
4560 struct pcicfg_pcie *cfg;
4561 int version, pos;
4562
4563 cfg = &dinfo->cfg.pcie;
4564 pos = cfg->pcie_location;
4565
4566 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
4567
4568 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl);
4569
4570 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4571 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
4572 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
4573 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl);
4574
4575 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4576 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
4577 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
4578 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl);
4579
4580 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4581 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
4582 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl);
4583
4584 if (version > 1) {
4585 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2);
4586 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2);
4587 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2);
4588 }
4589#undef WREG
4590}
4591
4592static void
4593pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo)
4594{
4595 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND,
4596 dinfo->cfg.pcix.pcix_command, 2);
4597}
4598
4599void
4600pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
4601{
4602
4603 /*
4604 * Only do header type 0 devices. Type 1 devices are bridges,
4605 * which we know need special treatment. Type 2 devices are
4606 * cardbus bridges which also require special treatment.
4607 * Other types are unknown, and we err on the side of safety
4608 * by ignoring them.
4609 */
4610 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
4611 return;
4612
4613 /*
4614 * Restore the device to full power mode. We must do this
4615 * before we restore the registers because moving from D3 to
4616 * D0 will cause the chip's BARs and some other registers to
4617 * be reset to some unknown power on reset values. Cut down
4618 * the noise on boot by doing nothing if we are already in
4619 * state D0.
4620 */
4621 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0)
4622 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4623 pci_restore_bars(dev);
4624 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
4625 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
4626 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
4627 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
4628 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
4629 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
4630 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
4631 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
4632 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
4633
4634 /*
4635 * Restore extended capabilities for PCI-Express and PCI-X
4636 */
4637 if (dinfo->cfg.pcie.pcie_location != 0)
4638 pci_cfg_restore_pcie(dev, dinfo);
4639 if (dinfo->cfg.pcix.pcix_location != 0)
4640 pci_cfg_restore_pcix(dev, dinfo);
4641
4642 /* Restore MSI and MSI-X configurations if they are present. */
4643 if (dinfo->cfg.msi.msi_location != 0)
4644 pci_resume_msi(dev);
4645 if (dinfo->cfg.msix.msix_location != 0)
4646 pci_resume_msix(dev);
4647}
4648
4649static void
4650pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo)
4651{
4652#define RREG(n) pci_read_config(dev, pos + (n), 2)
4653 struct pcicfg_pcie *cfg;
4654 int version, pos;
4655
4656 cfg = &dinfo->cfg.pcie;
4657 pos = cfg->pcie_location;
4658
4659 cfg->pcie_flags = RREG(PCIER_FLAGS);
4660
4661 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
4662
4663 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL);
4664
4665 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4666 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
4667 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
4668 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL);
4669
4670 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4671 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
4672 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
4673 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL);
4674
4675 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4676 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
4677 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL);
4678
4679 if (version > 1) {
4680 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2);
4681 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2);
4682 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2);
4683 }
4684#undef RREG
4685}
4686
4687static void
4688pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo)
4689{
4690 dinfo->cfg.pcix.pcix_command = pci_read_config(dev,
4691 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2);
4692}
4693
4694void
4695pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
4696{
4697 uint32_t cls;
4698 int ps;
4699
4700 /*
4701 * Only do header type 0 devices. Type 1 devices are bridges, which
4702 * we know need special treatment. Type 2 devices are cardbus bridges
4703 * which also require special treatment. Other types are unknown, and
4704 * we err on the side of safety by ignoring them. Powering down
4705 * bridges should not be undertaken lightly.
4706 */
4707 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
4708 return;
4709
4710 /*
4711 * Some drivers apparently write to these registers w/o updating our
4712 * cached copy. No harm happens if we update the copy, so do so here
4713 * so we can restore them. The COMMAND register is modified by the
4714 * bus w/o updating the cache. This should represent the normally
4715 * writable portion of the 'defined' part of type 0 headers. In
4716 * theory we also need to save/restore the PCI capability structures
4717 * we know about, but apart from power we don't know any that are
4718 * writable.
4719 */
4720 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4721 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4722 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4723 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4724 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4725 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4726 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4727 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4728 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4729 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4730 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4731 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4732 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4733 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4734 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4735
4736 if (dinfo->cfg.pcie.pcie_location != 0)
4737 pci_cfg_save_pcie(dev, dinfo);
4738
4739 if (dinfo->cfg.pcix.pcix_location != 0)
4740 pci_cfg_save_pcix(dev, dinfo);
4741
4742 /*
4743 * don't set the state for display devices, base peripherals and
4744 * memory devices since bad things happen when they are powered down.
4745 * We should (a) have drivers that can easily detach and (b) use
4746 * generic drivers for these devices so that some device actually
4747 * attaches. We need to make sure that when we implement (a) we don't
4748 * power the device down on a reattach.
4749 */
4750 cls = pci_get_class(dev);
4751 if (!setstate)
4752 return;
4753 switch (pci_do_power_nodriver)
4754 {
4755 case 0: /* NO powerdown at all */
4756 return;
4757 case 1: /* Conservative about what to power down */
4758 if (cls == PCIC_STORAGE)
4759 return;
4760 /*FALLTHROUGH*/
4761 case 2: /* Agressive about what to power down */
4762 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4763 cls == PCIC_BASEPERIPH)
4764 return;
4765 /*FALLTHROUGH*/
4766 case 3: /* Power down everything */
4767 break;
4768 }
4769 /*
4770 * PCI spec says we can only go into D3 state from D0 state.
4771 * Transition from D[12] into D0 before going to D3 state.
4772 */
4773 ps = pci_get_powerstate(dev);
4774 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4775 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4776 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4777 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
4778}
4779
4780/* Wrapper APIs suitable for device driver use. */
4781void
4782pci_save_state(device_t dev)
4783{
4784 struct pci_devinfo *dinfo;
4785
4786 dinfo = device_get_ivars(dev);
4787 pci_cfg_save(dev, dinfo, 0);
4788}
4789
4790void
4791pci_restore_state(device_t dev)
4792{
4793 struct pci_devinfo *dinfo;
4794
4795 dinfo = device_get_ivars(dev);
4796 pci_cfg_restore(dev, dinfo);
4797}
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