1/*-
2 * Copyright (C) 2012 Intel Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/dev/nvme/nvme_private.h 252271 2013-06-26 23:27:17Z jimharris $
27 */
28
29#ifndef __NVME_PRIVATE_H__
30#define __NVME_PRIVATE_H__
31
32#include <sys/param.h>
33#include <sys/bio.h>
34#include <sys/bus.h>

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55#ifdef CHATHAM2
56#define CHATHAM_PCI_ID 0x20118086
57#define CHATHAM_CONTROL_BAR 0
58#endif
59
60#define IDT32_PCI_ID 0x80d0111d /* 32 channel board */
61#define IDT8_PCI_ID 0x80d2111d /* 8 channel board */
62
63/*
64 * For commands requiring more than 2 PRP entries, one PRP will be
65 * embedded in the command (prp1), and the rest of the PRP entries
66 * will be in a list pointed to by the command (prp2). This means
67 * that real max number of PRP entries we support is 32+1, which
68 * results in a max xfer size of 32*PAGE_SIZE.
69 */
70#define NVME_MAX_PRP_LIST_ENTRIES (NVME_MAX_XFER_SIZE / PAGE_SIZE)
71
72#define NVME_ADMIN_TRACKERS (16)
73#define NVME_ADMIN_ENTRIES (128)
74/* min and max are defined in admin queue attributes section of spec */
75#define NVME_MIN_ADMIN_ENTRIES (2)
76#define NVME_MAX_ADMIN_ENTRIES (4096)
77
78/*

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187 uint32_t id;
188 uint32_t phase;
189
190 uint16_t vector;
191 int rid;
192 struct resource *res;
193 void *tag;
194
195 uint32_t num_entries;
196 uint32_t num_trackers;
197 uint32_t sq_tdbl_off;
198 uint32_t cq_hdbl_off;
199
200 uint32_t sq_head;
201 uint32_t sq_tail;
202 uint32_t cq_head;

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438 struct nvme_request *req);
439void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr,
440 struct nvme_request *req);
441void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr,
442 struct nvme_request *req);
443
444void nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id,
445 uint16_t vector, uint32_t num_entries,
446 uint32_t num_trackers,
447 struct nvme_controller *ctrlr);
448void nvme_qpair_submit_tracker(struct nvme_qpair *qpair,
449 struct nvme_tracker *tr);
450void nvme_qpair_process_completions(struct nvme_qpair *qpair);
451void nvme_qpair_submit_request(struct nvme_qpair *qpair,
452 struct nvme_request *req);
453void nvme_qpair_reset(struct nvme_qpair *qpair);
454void nvme_qpair_fail(struct nvme_qpair *qpair);

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