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mrsas.c (275976) mrsas.c (284267)
1/*
1/*
2 * Copyright (c) 2015, AVAGO Tech. All rights reserved. Author: Marian Choy
2 * Copyright (c) 2014, LSI Corp. All rights reserved. Author: Marian Choy
3 * Copyright (c) 2014, LSI Corp. All rights reserved. Author: Marian Choy
3 * Support: freebsdraid@lsi.com
4 * Support: freebsdraid@avagotech.com
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met:
8 *
9 * 1. Redistributions of source code must retain the above copyright notice,
10 * this list of conditions and the following disclaimer. 2. Redistributions
11 * in binary form must reproduce the above copyright notice, this list of

--- 14 unchanged lines hidden (view full) ---

26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 *
30 * The views and conclusions contained in the software and documentation are
31 * those of the authors and should not be interpreted as representing
32 * official policies,either expressed or implied, of the FreeBSD Project.
33 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer. 2. Redistributions
12 * in binary form must reproduce the above copyright notice, this list of

--- 14 unchanged lines hidden (view full) ---

27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 * The views and conclusions contained in the software and documentation are
32 * those of the authors and should not be interpreted as representing
33 * official policies,either expressed or implied, of the FreeBSD Project.
34 *
34 * Send feedback to: <megaraidfbsd@lsi.com> Mail to: LSI Corporation, 1621
35 * Send feedback to: <megaraidfbsd@avagotech.com> Mail to: AVAGO TECHNOLOGIES 1621
35 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD
36 *
37 */
38
39#include <sys/cdefs.h>
36 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD
37 *
38 */
39
40#include <sys/cdefs.h>
40__FBSDID("$FreeBSD: stable/10/sys/dev/mrsas/mrsas.c 275976 2014-12-21 02:35:22Z smh $");
41__FBSDID("$FreeBSD: stable/10/sys/dev/mrsas/mrsas.c 284267 2015-06-11 14:11:41Z kadesai $");
41
42#include <dev/mrsas/mrsas.h>
43#include <dev/mrsas/mrsas_ioctl.h>
44
45#include <cam/cam.h>
46#include <cam/cam_ccb.h>
47
48#include <sys/sysctl.h>

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76static int mrsas_get_pd_list(struct mrsas_softc *sc);
77static int mrsas_get_ld_list(struct mrsas_softc *sc);
78static int mrsas_setup_irq(struct mrsas_softc *sc);
79static int mrsas_alloc_mem(struct mrsas_softc *sc);
80static int mrsas_init_fw(struct mrsas_softc *sc);
81static int mrsas_setup_raidmap(struct mrsas_softc *sc);
82static int mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t MSIxIndex);
83static int mrsas_clear_intr(struct mrsas_softc *sc);
42
43#include <dev/mrsas/mrsas.h>
44#include <dev/mrsas/mrsas_ioctl.h>
45
46#include <cam/cam.h>
47#include <cam/cam_ccb.h>
48
49#include <sys/sysctl.h>

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77static int mrsas_get_pd_list(struct mrsas_softc *sc);
78static int mrsas_get_ld_list(struct mrsas_softc *sc);
79static int mrsas_setup_irq(struct mrsas_softc *sc);
80static int mrsas_alloc_mem(struct mrsas_softc *sc);
81static int mrsas_init_fw(struct mrsas_softc *sc);
82static int mrsas_setup_raidmap(struct mrsas_softc *sc);
83static int mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t MSIxIndex);
84static int mrsas_clear_intr(struct mrsas_softc *sc);
84static int
85mrsas_get_ctrl_info(struct mrsas_softc *sc,
86 struct mrsas_ctrl_info *ctrl_info);
87static int
85static int mrsas_get_ctrl_info(struct mrsas_softc *sc);
86static void mrsas_update_ext_vd_details(struct mrsas_softc *sc);
87static int
88mrsas_issue_blocked_abort_cmd(struct mrsas_softc *sc,
89 struct mrsas_mfi_cmd *cmd_to_abort);
88mrsas_issue_blocked_abort_cmd(struct mrsas_softc *sc,
89 struct mrsas_mfi_cmd *cmd_to_abort);
90static struct mrsas_softc *
91mrsas_get_softc_instance(struct cdev *dev,
92 u_long cmd, caddr_t arg);
90u_int32_t mrsas_read_reg(struct mrsas_softc *sc, int offset);
93u_int32_t mrsas_read_reg(struct mrsas_softc *sc, int offset);
91u_int8_t
94u_int8_t
92mrsas_build_mptmfi_passthru(struct mrsas_softc *sc,
93 struct mrsas_mfi_cmd *mfi_cmd);
95mrsas_build_mptmfi_passthru(struct mrsas_softc *sc,
96 struct mrsas_mfi_cmd *mfi_cmd);
97void mrsas_complete_outstanding_ioctls(struct mrsas_softc *sc);
94int mrsas_transition_to_ready(struct mrsas_softc *sc, int ocr);
95int mrsas_init_adapter(struct mrsas_softc *sc);
96int mrsas_alloc_mpt_cmds(struct mrsas_softc *sc);
97int mrsas_alloc_ioc_cmd(struct mrsas_softc *sc);
98int mrsas_alloc_ctlr_info_cmd(struct mrsas_softc *sc);
99int mrsas_ioc_init(struct mrsas_softc *sc);
100int mrsas_bus_scan(struct mrsas_softc *sc);
101int mrsas_issue_dcmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
102int mrsas_issue_polled(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
103int mrsas_reset_ctrl(struct mrsas_softc *sc);
104int mrsas_wait_for_outstanding(struct mrsas_softc *sc);
98int mrsas_transition_to_ready(struct mrsas_softc *sc, int ocr);
99int mrsas_init_adapter(struct mrsas_softc *sc);
100int mrsas_alloc_mpt_cmds(struct mrsas_softc *sc);
101int mrsas_alloc_ioc_cmd(struct mrsas_softc *sc);
102int mrsas_alloc_ctlr_info_cmd(struct mrsas_softc *sc);
103int mrsas_ioc_init(struct mrsas_softc *sc);
104int mrsas_bus_scan(struct mrsas_softc *sc);
105int mrsas_issue_dcmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
106int mrsas_issue_polled(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
107int mrsas_reset_ctrl(struct mrsas_softc *sc);
108int mrsas_wait_for_outstanding(struct mrsas_softc *sc);
105int
109int
106mrsas_issue_blocked_cmd(struct mrsas_softc *sc,
107 struct mrsas_mfi_cmd *cmd);
110mrsas_issue_blocked_cmd(struct mrsas_softc *sc,
111 struct mrsas_mfi_cmd *cmd);
108int
112int
109mrsas_alloc_tmp_dcmd(struct mrsas_softc *sc, struct mrsas_tmp_dcmd *tcmd,
110 int size);
111void mrsas_release_mfi_cmd(struct mrsas_mfi_cmd *cmd);
112void mrsas_wakeup(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
113void mrsas_complete_aen(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
114void mrsas_complete_abort(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
115void mrsas_disable_intr(struct mrsas_softc *sc);
116void mrsas_enable_intr(struct mrsas_softc *sc);
117void mrsas_free_ioc_cmd(struct mrsas_softc *sc);
118void mrsas_free_mem(struct mrsas_softc *sc);
119void mrsas_free_tmp_dcmd(struct mrsas_tmp_dcmd *tmp);
120void mrsas_isr(void *arg);
121void mrsas_teardown_intr(struct mrsas_softc *sc);
122void mrsas_addr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
123void mrsas_kill_hba(struct mrsas_softc *sc);
124void mrsas_aen_handler(struct mrsas_softc *sc);
113mrsas_alloc_tmp_dcmd(struct mrsas_softc *sc, struct mrsas_tmp_dcmd *tcmd,
114 int size);
115void mrsas_release_mfi_cmd(struct mrsas_mfi_cmd *cmd);
116void mrsas_wakeup(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
117void mrsas_complete_aen(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
118void mrsas_complete_abort(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
119void mrsas_disable_intr(struct mrsas_softc *sc);
120void mrsas_enable_intr(struct mrsas_softc *sc);
121void mrsas_free_ioc_cmd(struct mrsas_softc *sc);
122void mrsas_free_mem(struct mrsas_softc *sc);
123void mrsas_free_tmp_dcmd(struct mrsas_tmp_dcmd *tmp);
124void mrsas_isr(void *arg);
125void mrsas_teardown_intr(struct mrsas_softc *sc);
126void mrsas_addr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
127void mrsas_kill_hba(struct mrsas_softc *sc);
128void mrsas_aen_handler(struct mrsas_softc *sc);
125void
129void
126mrsas_write_reg(struct mrsas_softc *sc, int offset,
127 u_int32_t value);
130mrsas_write_reg(struct mrsas_softc *sc, int offset,
131 u_int32_t value);
128void
132void
129mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo,
130 u_int32_t req_desc_hi);
131void mrsas_free_ctlr_info_cmd(struct mrsas_softc *sc);
133mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo,
134 u_int32_t req_desc_hi);
135void mrsas_free_ctlr_info_cmd(struct mrsas_softc *sc);
132void
136void
133mrsas_complete_mptmfi_passthru(struct mrsas_softc *sc,
134 struct mrsas_mfi_cmd *cmd, u_int8_t status);
137mrsas_complete_mptmfi_passthru(struct mrsas_softc *sc,
138 struct mrsas_mfi_cmd *cmd, u_int8_t status);
135void
139void
136mrsas_map_mpt_cmd_status(struct mrsas_mpt_cmd *cmd, u_int8_t status,
137 u_int8_t extStatus);
138struct mrsas_mfi_cmd *mrsas_get_mfi_cmd(struct mrsas_softc *sc);
139
140MRSAS_REQUEST_DESCRIPTOR_UNION *mrsas_build_mpt_cmd
141 (struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
142
143extern int mrsas_cam_attach(struct mrsas_softc *sc);

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170 uint16_t vendor;
171 uint16_t device;
172 uint16_t subvendor;
173 uint16_t subdevice;
174 const char *desc;
175} MRSAS_CTLR_ID;
176
177MRSAS_CTLR_ID device_table[] = {
140mrsas_map_mpt_cmd_status(struct mrsas_mpt_cmd *cmd, u_int8_t status,
141 u_int8_t extStatus);
142struct mrsas_mfi_cmd *mrsas_get_mfi_cmd(struct mrsas_softc *sc);
143
144MRSAS_REQUEST_DESCRIPTOR_UNION *mrsas_build_mpt_cmd
145 (struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd);
146
147extern int mrsas_cam_attach(struct mrsas_softc *sc);

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174 uint16_t vendor;
175 uint16_t device;
176 uint16_t subvendor;
177 uint16_t subdevice;
178 const char *desc;
179} MRSAS_CTLR_ID;
180
181MRSAS_CTLR_ID device_table[] = {
178 {0x1000, MRSAS_TBOLT, 0xffff, 0xffff, "LSI Thunderbolt SAS Controller"},
179 {0x1000, MRSAS_INVADER, 0xffff, 0xffff, "LSI Invader SAS Controller"},
180 {0x1000, MRSAS_FURY, 0xffff, 0xffff, "LSI Fury SAS Controller"},
182 {0x1000, MRSAS_TBOLT, 0xffff, 0xffff, "AVAGO Thunderbolt SAS Controller"},
183 {0x1000, MRSAS_INVADER, 0xffff, 0xffff, "AVAGO Invader SAS Controller"},
184 {0x1000, MRSAS_FURY, 0xffff, 0xffff, "AVAGO Fury SAS Controller"},
181 {0, 0, 0, 0, NULL}
182};
183
184/*
185 * Character device entry points
186 *
187 */
188static struct cdevsw mrsas_cdevsw = {

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267 *
268 */
269void
270mrsas_disable_intr(struct mrsas_softc *sc)
271{
272 u_int32_t mask = 0xFFFFFFFF;
273 u_int32_t status;
274
185 {0, 0, 0, 0, NULL}
186};
187
188/*
189 * Character device entry points
190 *
191 */
192static struct cdevsw mrsas_cdevsw = {

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271 *
272 */
273void
274mrsas_disable_intr(struct mrsas_softc *sc)
275{
276 u_int32_t mask = 0xFFFFFFFF;
277 u_int32_t status;
278
279 sc->mask_interrupts = 1;
275 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask), mask);
276 /* Dummy read to force pci flush */
277 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask));
278}
279
280void
281mrsas_enable_intr(struct mrsas_softc *sc)
282{
283 u_int32_t mask = MFI_FUSION_ENABLE_INTERRUPT_MASK;
284 u_int32_t status;
285
280 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask), mask);
281 /* Dummy read to force pci flush */
282 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask));
283}
284
285void
286mrsas_enable_intr(struct mrsas_softc *sc)
287{
288 u_int32_t mask = MFI_FUSION_ENABLE_INTERRUPT_MASK;
289 u_int32_t status;
290
291 sc->mask_interrupts = 0;
286 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status), ~0);
287 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status));
288
289 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask), ~mask);
290 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask));
291}
292
293static int

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347static int
348mrsas_probe(device_t dev)
349{
350 static u_int8_t first_ctrl = 1;
351 struct mrsas_ident *id;
352
353 if ((id = mrsas_find_ident(dev)) != NULL) {
354 if (first_ctrl) {
292 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status), ~0);
293 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status));
294
295 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask), ~mask);
296 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask));
297}
298
299static int

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353static int
354mrsas_probe(device_t dev)
355{
356 static u_int8_t first_ctrl = 1;
357 struct mrsas_ident *id;
358
359 if ((id = mrsas_find_ident(dev)) != NULL) {
360 if (first_ctrl) {
355 printf("LSI MegaRAID SAS FreeBSD mrsas driver version: %s\n",
361 printf("AVAGO MegaRAID SAS FreeBSD mrsas driver version: %s\n",
356 MRSAS_VERSION);
357 first_ctrl = 0;
358 }
359 device_set_desc(dev, id->desc);
360 /* between BUS_PROBE_DEFAULT and BUS_PROBE_LOW_PRIORITY */
361 return (-30);
362 }
363 return (ENXIO);

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455 sc->reset_count = 0;
456 sc->reset_in_progress = 0;
457
458 /*
459 * Grab the global variables.
460 */
461 TUNABLE_INT_FETCH("hw.mrsas.debug_level", &sc->mrsas_debug);
462
362 MRSAS_VERSION);
363 first_ctrl = 0;
364 }
365 device_set_desc(dev, id->desc);
366 /* between BUS_PROBE_DEFAULT and BUS_PROBE_LOW_PRIORITY */
367 return (-30);
368 }
369 return (ENXIO);

--- 91 unchanged lines hidden (view full) ---

461 sc->reset_count = 0;
462 sc->reset_in_progress = 0;
463
464 /*
465 * Grab the global variables.
466 */
467 TUNABLE_INT_FETCH("hw.mrsas.debug_level", &sc->mrsas_debug);
468
469 /*
470 * Grab the global variables.
471 */
472 TUNABLE_INT_FETCH("hw.mrsas.lb_pending_cmds", &sc->lb_pending_cmds);
473
463 /* Grab the unit-instance variables */
464 snprintf(tmpstr, sizeof(tmpstr), "dev.mrsas.%d.debug_level",
465 device_get_unit(sc->mrsas_dev));
466 TUNABLE_INT_FETCH(tmpstr, &sc->mrsas_debug);
467}
468
469/*
470 * mrsas_alloc_evt_log_info cmd: Allocates memory to get event log information.

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1158 free(sc->req_desc, M_MRSAS);
1159 sc->req_desc = NULL;
1160
1161 /*
1162 * Destroy parent tag
1163 */
1164 if (sc->mrsas_parent_tag != NULL)
1165 bus_dma_tag_destroy(sc->mrsas_parent_tag);
474 /* Grab the unit-instance variables */
475 snprintf(tmpstr, sizeof(tmpstr), "dev.mrsas.%d.debug_level",
476 device_get_unit(sc->mrsas_dev));
477 TUNABLE_INT_FETCH(tmpstr, &sc->mrsas_debug);
478}
479
480/*
481 * mrsas_alloc_evt_log_info cmd: Allocates memory to get event log information.

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1169 free(sc->req_desc, M_MRSAS);
1170 sc->req_desc = NULL;
1171
1172 /*
1173 * Destroy parent tag
1174 */
1175 if (sc->mrsas_parent_tag != NULL)
1176 bus_dma_tag_destroy(sc->mrsas_parent_tag);
1177
1178 /*
1179 * Free ctrl_info memory
1180 */
1181 if (sc->ctrl_info != NULL)
1182 free(sc->ctrl_info, M_MRSAS);
1166}
1167
1168/*
1169 * mrsas_teardown_intr: Teardown interrupt
1170 * input: Adapter instance soft state
1171 *
1172 * This function is called from mrsas_detach() to teardown and release bus
1173 * interrupt resourse.

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1226mrsas_resume(device_t dev)
1227{
1228 struct mrsas_softc *sc;
1229
1230 sc = device_get_softc(dev);
1231 return (0);
1232}
1233
1183}
1184
1185/*
1186 * mrsas_teardown_intr: Teardown interrupt
1187 * input: Adapter instance soft state
1188 *
1189 * This function is called from mrsas_detach() to teardown and release bus
1190 * interrupt resourse.

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1243mrsas_resume(device_t dev)
1244{
1245 struct mrsas_softc *sc;
1246
1247 sc = device_get_softc(dev);
1248 return (0);
1249}
1250
1251/**
1252 * mrsas_get_softc_instance: Find softc instance based on cmd type
1253 *
1254 * This function will return softc instance based on cmd type.
1255 * In some case, application fire ioctl on required management instance and
1256 * do not provide host_no. Use cdev->si_drv1 to get softc instance for those
1257 * case, else get the softc instance from host_no provided by application in
1258 * user data.
1259 */
1260
1261static struct mrsas_softc *
1262mrsas_get_softc_instance(struct cdev *dev, u_long cmd, caddr_t arg)
1263{
1264 struct mrsas_softc *sc = NULL;
1265 struct mrsas_iocpacket *user_ioc = (struct mrsas_iocpacket *)arg;
1266
1267 if (cmd == MRSAS_IOC_GET_PCI_INFO) {
1268 sc = dev->si_drv1;
1269 } else {
1270 /*
1271 * get the Host number & the softc from data sent by the
1272 * Application
1273 */
1274 sc = mrsas_mgmt_info.sc_ptr[user_ioc->host_no];
1275 if ((user_ioc->host_no >= mrsas_mgmt_info.max_index) || (sc == NULL)) {
1276 if (sc == NULL)
1277 mrsas_dprint(sc, MRSAS_FAULT,
1278 "There is no Controller number %d .\n", user_ioc->host_no);
1279 else
1280 mrsas_dprint(sc, MRSAS_FAULT,
1281 "Invalid Controller number %d .\n", user_ioc->host_no);
1282 }
1283 }
1284
1285 return sc;
1286}
1287
1234/*
1235 * mrsas_ioctl: IOCtl commands entry point.
1236 *
1237 * This function is the entry point for IOCtls from the OS. It calls the
1238 * appropriate function for processing depending on the command received.
1239 */
1240static int
1241mrsas_ioctl(struct cdev *dev, u_long cmd, caddr_t arg, int flag, d_thread_t *td)
1242{
1243 struct mrsas_softc *sc;
1244 int ret = 0, i = 0;
1288/*
1289 * mrsas_ioctl: IOCtl commands entry point.
1290 *
1291 * This function is the entry point for IOCtls from the OS. It calls the
1292 * appropriate function for processing depending on the command received.
1293 */
1294static int
1295mrsas_ioctl(struct cdev *dev, u_long cmd, caddr_t arg, int flag, d_thread_t *td)
1296{
1297 struct mrsas_softc *sc;
1298 int ret = 0, i = 0;
1299 MRSAS_DRV_PCI_INFORMATION *pciDrvInfo;
1245
1300
1246 struct mrsas_iocpacket *user_ioc = (struct mrsas_iocpacket *)arg;
1247
1248 /* get the Host number & the softc from data sent by the Application */
1249 sc = mrsas_mgmt_info.sc_ptr[user_ioc->host_no];
1250
1251 if ((mrsas_mgmt_info.max_index == user_ioc->host_no) || (sc == NULL)) {
1252 printf("Please check the controller number\n");
1253 if (sc == NULL)
1254 printf("There is NO such Host no. %d\n", user_ioc->host_no);
1255
1301 sc = mrsas_get_softc_instance(dev, cmd, arg);
1302 if (!sc)
1256 return ENOENT;
1303 return ENOENT;
1257 }
1304
1258 if (sc->remove_in_progress) {
1259 mrsas_dprint(sc, MRSAS_INFO,
1260 "Driver remove or shutdown called.\n");
1261 return ENOENT;
1262 }
1263 mtx_lock_spin(&sc->ioctl_lock);
1264 if (!sc->reset_in_progress) {
1265 mtx_unlock_spin(&sc->ioctl_lock);

--- 27 unchanged lines hidden (view full) ---

1293
1294 /* Increment the Ioctl counting semaphore value */
1295 sema_post(&sc->ioctl_count_sema);
1296
1297 break;
1298 case MRSAS_IOC_SCAN_BUS:
1299 ret = mrsas_bus_scan(sc);
1300 break;
1305 if (sc->remove_in_progress) {
1306 mrsas_dprint(sc, MRSAS_INFO,
1307 "Driver remove or shutdown called.\n");
1308 return ENOENT;
1309 }
1310 mtx_lock_spin(&sc->ioctl_lock);
1311 if (!sc->reset_in_progress) {
1312 mtx_unlock_spin(&sc->ioctl_lock);

--- 27 unchanged lines hidden (view full) ---

1340
1341 /* Increment the Ioctl counting semaphore value */
1342 sema_post(&sc->ioctl_count_sema);
1343
1344 break;
1345 case MRSAS_IOC_SCAN_BUS:
1346 ret = mrsas_bus_scan(sc);
1347 break;
1348
1349 case MRSAS_IOC_GET_PCI_INFO:
1350 pciDrvInfo = (MRSAS_DRV_PCI_INFORMATION *) arg;
1351 memset(pciDrvInfo, 0, sizeof(MRSAS_DRV_PCI_INFORMATION));
1352 pciDrvInfo->busNumber = pci_get_bus(sc->mrsas_dev);
1353 pciDrvInfo->deviceNumber = pci_get_slot(sc->mrsas_dev);
1354 pciDrvInfo->functionNumber = pci_get_function(sc->mrsas_dev);
1355 pciDrvInfo->domainID = pci_get_domain(sc->mrsas_dev);
1356 mrsas_dprint(sc, MRSAS_INFO, "pci bus no: %d,"
1357 "pci device no: %d, pci function no: %d,"
1358 "pci domain ID: %d\n",
1359 pciDrvInfo->busNumber, pciDrvInfo->deviceNumber,
1360 pciDrvInfo->functionNumber, pciDrvInfo->domainID);
1361 ret = 0;
1362 break;
1363
1301 default:
1302 mrsas_dprint(sc, MRSAS_TRACE, "IOCTL command 0x%lx is not handled\n", cmd);
1303 ret = ENOENT;
1304 }
1305
1306 return (ret);
1307}
1308

--- 13 unchanged lines hidden (view full) ---

1322
1323 if (poll_events & (POLLIN | POLLRDNORM)) {
1324 if (sc->mrsas_aen_triggered) {
1325 revents |= poll_events & (POLLIN | POLLRDNORM);
1326 }
1327 }
1328 if (revents == 0) {
1329 if (poll_events & (POLLIN | POLLRDNORM)) {
1364 default:
1365 mrsas_dprint(sc, MRSAS_TRACE, "IOCTL command 0x%lx is not handled\n", cmd);
1366 ret = ENOENT;
1367 }
1368
1369 return (ret);
1370}
1371

--- 13 unchanged lines hidden (view full) ---

1385
1386 if (poll_events & (POLLIN | POLLRDNORM)) {
1387 if (sc->mrsas_aen_triggered) {
1388 revents |= poll_events & (POLLIN | POLLRDNORM);
1389 }
1390 }
1391 if (revents == 0) {
1392 if (poll_events & (POLLIN | POLLRDNORM)) {
1393 mtx_lock(&sc->aen_lock);
1330 sc->mrsas_poll_waiting = 1;
1331 selrecord(td, &sc->mrsas_select);
1394 sc->mrsas_poll_waiting = 1;
1395 selrecord(td, &sc->mrsas_select);
1396 mtx_unlock(&sc->aen_lock);
1332 }
1333 }
1334 return revents;
1335}
1336
1337/*
1338 * mrsas_setup_irq: Set up interrupt
1339 * input: Adapter instance soft state

--- 41 unchanged lines hidden (view full) ---

1381 */
1382void
1383mrsas_isr(void *arg)
1384{
1385 struct mrsas_irq_context *irq_context = (struct mrsas_irq_context *)arg;
1386 struct mrsas_softc *sc = irq_context->sc;
1387 int status = 0;
1388
1397 }
1398 }
1399 return revents;
1400}
1401
1402/*
1403 * mrsas_setup_irq: Set up interrupt
1404 * input: Adapter instance soft state

--- 41 unchanged lines hidden (view full) ---

1446 */
1447void
1448mrsas_isr(void *arg)
1449{
1450 struct mrsas_irq_context *irq_context = (struct mrsas_irq_context *)arg;
1451 struct mrsas_softc *sc = irq_context->sc;
1452 int status = 0;
1453
1454 if (sc->mask_interrupts)
1455 return;
1456
1389 if (!sc->msix_vectors) {
1390 status = mrsas_clear_intr(sc);
1391 if (!status)
1392 return;
1393 }
1394 /* If we are resetting, bail */
1395 if (mrsas_test_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags)) {
1396 printf(" Entered into ISR when OCR is going active. \n");

--- 21 unchanged lines hidden (view full) ---

1418static int
1419mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t MSIxIndex)
1420{
1421 Mpi2ReplyDescriptorsUnion_t *desc;
1422 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR *reply_desc;
1423 MRSAS_RAID_SCSI_IO_REQUEST *scsi_io_req;
1424 struct mrsas_mpt_cmd *cmd_mpt;
1425 struct mrsas_mfi_cmd *cmd_mfi;
1457 if (!sc->msix_vectors) {
1458 status = mrsas_clear_intr(sc);
1459 if (!status)
1460 return;
1461 }
1462 /* If we are resetting, bail */
1463 if (mrsas_test_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags)) {
1464 printf(" Entered into ISR when OCR is going active. \n");

--- 21 unchanged lines hidden (view full) ---

1486static int
1487mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t MSIxIndex)
1488{
1489 Mpi2ReplyDescriptorsUnion_t *desc;
1490 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR *reply_desc;
1491 MRSAS_RAID_SCSI_IO_REQUEST *scsi_io_req;
1492 struct mrsas_mpt_cmd *cmd_mpt;
1493 struct mrsas_mfi_cmd *cmd_mfi;
1426 u_int8_t arm, reply_descript_type;
1494 u_int8_t reply_descript_type;
1427 u_int16_t smid, num_completed;
1428 u_int8_t status, extStatus;
1429 union desc_value desc_val;
1430 PLD_LOAD_BALANCE_INFO lbinfo;
1431 u_int32_t device_id;
1432 int threshold_reply_count = 0;
1433
1434

--- 21 unchanged lines hidden (view full) ---

1456 status = scsi_io_req->RaidContext.status;
1457 extStatus = scsi_io_req->RaidContext.exStatus;
1458
1459 switch (scsi_io_req->Function) {
1460 case MPI2_FUNCTION_SCSI_IO_REQUEST: /* Fast Path IO. */
1461 device_id = cmd_mpt->ccb_ptr->ccb_h.target_id;
1462 lbinfo = &sc->load_balance_info[device_id];
1463 if (cmd_mpt->load_balance == MRSAS_LOAD_BALANCE_FLAG) {
1495 u_int16_t smid, num_completed;
1496 u_int8_t status, extStatus;
1497 union desc_value desc_val;
1498 PLD_LOAD_BALANCE_INFO lbinfo;
1499 u_int32_t device_id;
1500 int threshold_reply_count = 0;
1501
1502

--- 21 unchanged lines hidden (view full) ---

1524 status = scsi_io_req->RaidContext.status;
1525 extStatus = scsi_io_req->RaidContext.exStatus;
1526
1527 switch (scsi_io_req->Function) {
1528 case MPI2_FUNCTION_SCSI_IO_REQUEST: /* Fast Path IO. */
1529 device_id = cmd_mpt->ccb_ptr->ccb_h.target_id;
1530 lbinfo = &sc->load_balance_info[device_id];
1531 if (cmd_mpt->load_balance == MRSAS_LOAD_BALANCE_FLAG) {
1464 arm = lbinfo->raid1DevHandle[0] == scsi_io_req->DevHandle ? 0 : 1;
1465 mrsas_atomic_dec(&lbinfo->scsi_pending_cmds[arm]);
1532 mrsas_atomic_dec(&lbinfo->scsi_pending_cmds[cmd_mpt->pd_r1_lb]);
1466 cmd_mpt->load_balance &= ~MRSAS_LOAD_BALANCE_FLAG;
1467 }
1468 /* Fall thru and complete IO */
1469 case MRSAS_MPI2_FUNCTION_LD_IO_REQUEST:
1470 mrsas_map_mpt_cmd_status(cmd_mpt, status, extStatus);
1471 mrsas_cmd_done(sc, cmd_mpt);
1472 scsi_io_req->RaidContext.status = 0;
1473 scsi_io_req->RaidContext.exStatus = 0;

--- 128 unchanged lines hidden (view full) ---

1602 *
1603 * This function creates the parent DMA tag and allocates DMAable memory. DMA
1604 * tag describes constraints of DMA mapping. Memory allocated is mapped into
1605 * Kernel virtual address. Callback argument is physical memory address.
1606 */
1607static int
1608mrsas_alloc_mem(struct mrsas_softc *sc)
1609{
1533 cmd_mpt->load_balance &= ~MRSAS_LOAD_BALANCE_FLAG;
1534 }
1535 /* Fall thru and complete IO */
1536 case MRSAS_MPI2_FUNCTION_LD_IO_REQUEST:
1537 mrsas_map_mpt_cmd_status(cmd_mpt, status, extStatus);
1538 mrsas_cmd_done(sc, cmd_mpt);
1539 scsi_io_req->RaidContext.status = 0;
1540 scsi_io_req->RaidContext.exStatus = 0;

--- 128 unchanged lines hidden (view full) ---

1669 *
1670 * This function creates the parent DMA tag and allocates DMAable memory. DMA
1671 * tag describes constraints of DMA mapping. Memory allocated is mapped into
1672 * Kernel virtual address. Callback argument is physical memory address.
1673 */
1674static int
1675mrsas_alloc_mem(struct mrsas_softc *sc)
1676{
1610 u_int32_t verbuf_size, io_req_size, reply_desc_size, sense_size, chain_frame_size,
1611 evt_detail_size, count;
1677 u_int32_t verbuf_size, io_req_size, reply_desc_size, sense_size,
1678 chain_frame_size, evt_detail_size, count;
1612
1613 /*
1614 * Allocate parent DMA tag
1615 */
1616 if (bus_dma_tag_create(NULL, /* parent */
1617 1, /* alignment */
1618 0, /* boundary */
1619 BUS_SPACE_MAXADDR, /* lowaddr */

--- 235 unchanged lines hidden (view full) ---

1855 *
1856 * Allocate DMA memory for the RAID maps and perform setup.
1857 */
1858static int
1859mrsas_setup_raidmap(struct mrsas_softc *sc)
1860{
1861 int i;
1862
1679
1680 /*
1681 * Allocate parent DMA tag
1682 */
1683 if (bus_dma_tag_create(NULL, /* parent */
1684 1, /* alignment */
1685 0, /* boundary */
1686 BUS_SPACE_MAXADDR, /* lowaddr */

--- 235 unchanged lines hidden (view full) ---

1922 *
1923 * Allocate DMA memory for the RAID maps and perform setup.
1924 */
1925static int
1926mrsas_setup_raidmap(struct mrsas_softc *sc)
1927{
1928 int i;
1929
1863 sc->drv_supported_vd_count =
1864 MRSAS_MAX_LD_CHANNELS * MRSAS_MAX_DEV_PER_CHANNEL;
1865 sc->drv_supported_pd_count =
1866 MRSAS_MAX_PD_CHANNELS * MRSAS_MAX_DEV_PER_CHANNEL;
1867
1868 if (sc->max256vdSupport) {
1869 sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES_EXT;
1870 sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES;
1871 } else {
1872 sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES;
1873 sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES;
1874 }
1875
1876#if VD_EXT_DEBUG
1877 device_printf(sc->mrsas_dev, "FW supports: max256vdSupport = %s\n",
1878 sc->max256vdSupport ? "YES" : "NO");
1879 device_printf(sc->mrsas_dev, "FW supports %dVDs %dPDs\n"
1880 "DRIVER supports %dVDs %dPDs \n",
1881 sc->fw_supported_vd_count, sc->fw_supported_pd_count,
1882 sc->drv_supported_vd_count, sc->drv_supported_pd_count);
1883#endif
1884
1885 sc->old_map_sz = sizeof(MR_FW_RAID_MAP) +
1886 (sizeof(MR_LD_SPAN_MAP) * (sc->fw_supported_vd_count - 1));
1887 sc->new_map_sz = sizeof(MR_FW_RAID_MAP_EXT);
1888 sc->drv_map_sz = sizeof(MR_DRV_RAID_MAP) +
1889 (sizeof(MR_LD_SPAN_MAP) * (sc->drv_supported_vd_count - 1));
1890
1891 for (i = 0; i < 2; i++) {
1892 sc->ld_drv_map[i] =
1893 (void *)malloc(sc->drv_map_sz, M_MRSAS, M_NOWAIT);
1894 /* Do Error handling */
1895 if (!sc->ld_drv_map[i]) {
1896 device_printf(sc->mrsas_dev, "Could not allocate memory for local map");
1897
1898 if (i == 1)
1899 free(sc->ld_drv_map[0], M_MRSAS);
1900 /* ABORT driver initialization */
1901 goto ABORT;
1902 }
1903 }
1904
1930 for (i = 0; i < 2; i++) {
1931 sc->ld_drv_map[i] =
1932 (void *)malloc(sc->drv_map_sz, M_MRSAS, M_NOWAIT);
1933 /* Do Error handling */
1934 if (!sc->ld_drv_map[i]) {
1935 device_printf(sc->mrsas_dev, "Could not allocate memory for local map");
1936
1937 if (i == 1)
1938 free(sc->ld_drv_map[0], M_MRSAS);
1939 /* ABORT driver initialization */
1940 goto ABORT;
1941 }
1942 }
1943
1905 sc->max_map_sz = max(sc->old_map_sz, sc->new_map_sz);
1906
1907 if (sc->max256vdSupport)
1908 sc->current_map_sz = sc->new_map_sz;
1909 else
1910 sc->current_map_sz = sc->old_map_sz;
1911
1912
1913 for (int i = 0; i < 2; i++) {
1914 if (bus_dma_tag_create(sc->mrsas_parent_tag,
1915 4, 0,
1916 BUS_SPACE_MAXADDR_32BIT,
1917 BUS_SPACE_MAXADDR,
1918 NULL, NULL,
1919 sc->max_map_sz,
1920 1,

--- 43 unchanged lines hidden (view full) ---

1964 *
1965 * Calls transition_to_ready() to make sure Firmware is in operational state and
1966 * calls mrsas_init_adapter() to send IOC_INIT command to Firmware. It
1967 * issues internal commands to get the controller info after the IOC_INIT
1968 * command response is received by Firmware. Note: code relating to
1969 * get_pdlist, get_ld_list and max_sectors are currently not being used, it
1970 * is left here as placeholder.
1971 */
1944 for (int i = 0; i < 2; i++) {
1945 if (bus_dma_tag_create(sc->mrsas_parent_tag,
1946 4, 0,
1947 BUS_SPACE_MAXADDR_32BIT,
1948 BUS_SPACE_MAXADDR,
1949 NULL, NULL,
1950 sc->max_map_sz,
1951 1,

--- 43 unchanged lines hidden (view full) ---

1995 *
1996 * Calls transition_to_ready() to make sure Firmware is in operational state and
1997 * calls mrsas_init_adapter() to send IOC_INIT command to Firmware. It
1998 * issues internal commands to get the controller info after the IOC_INIT
1999 * command response is received by Firmware. Note: code relating to
2000 * get_pdlist, get_ld_list and max_sectors are currently not being used, it
2001 * is left here as placeholder.
2002 */
1972static int
2003static int
1973mrsas_init_fw(struct mrsas_softc *sc)
1974{
1975
1976 int ret, loop, ocr = 0;
1977 u_int32_t max_sectors_1;
1978 u_int32_t max_sectors_2;
1979 u_int32_t tmp_sectors;
2004mrsas_init_fw(struct mrsas_softc *sc)
2005{
2006
2007 int ret, loop, ocr = 0;
2008 u_int32_t max_sectors_1;
2009 u_int32_t max_sectors_2;
2010 u_int32_t tmp_sectors;
1980 struct mrsas_ctrl_info *ctrl_info;
1981 u_int32_t scratch_pad_2;
1982 int msix_enable = 0;
1983 int fw_msix_count = 0;
1984
1985 /* Make sure Firmware is ready */
1986 ret = mrsas_transition_to_ready(sc, ocr);
1987 if (ret != SUCCESS) {
1988 return (ret);

--- 45 unchanged lines hidden (view full) ---

2034 device_printf(sc->mrsas_dev, "Adapter initialize Fail.\n");
2035 return (1);
2036 }
2037 /* Allocate internal commands for pass-thru */
2038 if (mrsas_alloc_mfi_cmds(sc) != SUCCESS) {
2039 device_printf(sc->mrsas_dev, "Allocate MFI cmd failed.\n");
2040 return (1);
2041 }
2011 u_int32_t scratch_pad_2;
2012 int msix_enable = 0;
2013 int fw_msix_count = 0;
2014
2015 /* Make sure Firmware is ready */
2016 ret = mrsas_transition_to_ready(sc, ocr);
2017 if (ret != SUCCESS) {
2018 return (ret);

--- 45 unchanged lines hidden (view full) ---

2064 device_printf(sc->mrsas_dev, "Adapter initialize Fail.\n");
2065 return (1);
2066 }
2067 /* Allocate internal commands for pass-thru */
2068 if (mrsas_alloc_mfi_cmds(sc) != SUCCESS) {
2069 device_printf(sc->mrsas_dev, "Allocate MFI cmd failed.\n");
2070 return (1);
2071 }
2072 sc->ctrl_info = malloc(sizeof(struct mrsas_ctrl_info), M_MRSAS, M_NOWAIT);
2073 if (!sc->ctrl_info) {
2074 device_printf(sc->mrsas_dev, "Malloc for ctrl_info failed.\n");
2075 return (1);
2076 }
2042 /*
2043 * Get the controller info from FW, so that the MAX VD support
2044 * availability can be decided.
2045 */
2077 /*
2078 * Get the controller info from FW, so that the MAX VD support
2079 * availability can be decided.
2080 */
2046 ctrl_info = malloc(sizeof(struct mrsas_ctrl_info), M_MRSAS, M_NOWAIT);
2047 if (!ctrl_info)
2048 device_printf(sc->mrsas_dev, "Malloc for ctrl_info failed.\n");
2049
2050 if (mrsas_get_ctrl_info(sc, ctrl_info)) {
2081 if (mrsas_get_ctrl_info(sc)) {
2051 device_printf(sc->mrsas_dev, "Unable to get FW ctrl_info.\n");
2082 device_printf(sc->mrsas_dev, "Unable to get FW ctrl_info.\n");
2083 return (1);
2052 }
2084 }
2053 sc->max256vdSupport =
2054 (u_int8_t)ctrl_info->adapterOperations3.supportMaxExtLDs;
2085 sc->secure_jbod_support =
2086 (u_int8_t)sc->ctrl_info->adapterOperations3.supportSecurityonJBOD;
2055
2087
2056 if (ctrl_info->max_lds > 64) {
2057 sc->max256vdSupport = 1;
2058 }
2088 if (sc->secure_jbod_support)
2089 device_printf(sc->mrsas_dev, "FW supports SED \n");
2090
2059 if (mrsas_setup_raidmap(sc) != SUCCESS) {
2060 device_printf(sc->mrsas_dev, "Set up RAID map failed.\n");
2061 return (1);
2062 }
2063 /* For pass-thru, get PD/LD list and controller info */
2064 memset(sc->pd_list, 0,
2065 MRSAS_MAX_PD * sizeof(struct mrsas_pd_list));
2066 mrsas_get_pd_list(sc);

--- 7 unchanged lines hidden (view full) ---

2074 * two.
2075 *
2076 * 1 << stripe_sz_ops.min = max sectors per strip
2077 *
2078 * Note that older firmwares ( < FW ver 30) didn't report information to
2079 * calculate max_sectors_1. So the number ended up as zero always.
2080 */
2081 tmp_sectors = 0;
2091 if (mrsas_setup_raidmap(sc) != SUCCESS) {
2092 device_printf(sc->mrsas_dev, "Set up RAID map failed.\n");
2093 return (1);
2094 }
2095 /* For pass-thru, get PD/LD list and controller info */
2096 memset(sc->pd_list, 0,
2097 MRSAS_MAX_PD * sizeof(struct mrsas_pd_list));
2098 mrsas_get_pd_list(sc);

--- 7 unchanged lines hidden (view full) ---

2106 * two.
2107 *
2108 * 1 << stripe_sz_ops.min = max sectors per strip
2109 *
2110 * Note that older firmwares ( < FW ver 30) didn't report information to
2111 * calculate max_sectors_1. So the number ended up as zero always.
2112 */
2113 tmp_sectors = 0;
2082 max_sectors_1 = (1 << ctrl_info->stripe_sz_ops.min) *
2083 ctrl_info->max_strips_per_io;
2084 max_sectors_2 = ctrl_info->max_request_size;
2114 max_sectors_1 = (1 << sc->ctrl_info->stripe_sz_ops.min) *
2115 sc->ctrl_info->max_strips_per_io;
2116 max_sectors_2 = sc->ctrl_info->max_request_size;
2085 tmp_sectors = min(max_sectors_1, max_sectors_2);
2086 sc->max_sectors_per_req = sc->max_num_sge * MRSAS_PAGE_SIZE / 512;
2087
2088 if (tmp_sectors && (sc->max_sectors_per_req > tmp_sectors))
2089 sc->max_sectors_per_req = tmp_sectors;
2090
2091 sc->disableOnlineCtrlReset =
2117 tmp_sectors = min(max_sectors_1, max_sectors_2);
2118 sc->max_sectors_per_req = sc->max_num_sge * MRSAS_PAGE_SIZE / 512;
2119
2120 if (tmp_sectors && (sc->max_sectors_per_req > tmp_sectors))
2121 sc->max_sectors_per_req = tmp_sectors;
2122
2123 sc->disableOnlineCtrlReset =
2092 ctrl_info->properties.OnOffProperties.disableOnlineCtrlReset;
2124 sc->ctrl_info->properties.OnOffProperties.disableOnlineCtrlReset;
2093 sc->UnevenSpanSupport =
2125 sc->UnevenSpanSupport =
2094 ctrl_info->adapterOperations2.supportUnevenSpans;
2126 sc->ctrl_info->adapterOperations2.supportUnevenSpans;
2095 if (sc->UnevenSpanSupport) {
2096 device_printf(sc->mrsas_dev, "FW supports: UnevenSpanSupport=%x\n\n",
2097 sc->UnevenSpanSupport);
2098
2099 if (MR_ValidateMapInfo(sc))
2100 sc->fast_path_io = 1;
2101 else
2102 sc->fast_path_io = 0;
2103 }
2127 if (sc->UnevenSpanSupport) {
2128 device_printf(sc->mrsas_dev, "FW supports: UnevenSpanSupport=%x\n\n",
2129 sc->UnevenSpanSupport);
2130
2131 if (MR_ValidateMapInfo(sc))
2132 sc->fast_path_io = 1;
2133 else
2134 sc->fast_path_io = 0;
2135 }
2104 if (ctrl_info)
2105 free(ctrl_info, M_MRSAS);
2106
2107 return (0);
2108}
2109
2110/*
2111 * mrsas_init_adapter: Initializes the adapter/controller
2112 * input: Adapter soft state
2113 *
2114 * Prepares for the issuing of the IOC Init cmd to FW for initializing the

--- 15 unchanged lines hidden (view full) ---

2130 /* Get operational params from status register */
2131 sc->max_fw_cmds = status & MRSAS_FWSTATE_MAXCMD_MASK;
2132
2133 /* Decrement the max supported by 1, to correlate with FW */
2134 sc->max_fw_cmds = sc->max_fw_cmds - 1;
2135 max_cmd = sc->max_fw_cmds;
2136
2137 /* Determine allocation size of command frames */
2136 return (0);
2137}
2138
2139/*
2140 * mrsas_init_adapter: Initializes the adapter/controller
2141 * input: Adapter soft state
2142 *
2143 * Prepares for the issuing of the IOC Init cmd to FW for initializing the

--- 15 unchanged lines hidden (view full) ---

2159 /* Get operational params from status register */
2160 sc->max_fw_cmds = status & MRSAS_FWSTATE_MAXCMD_MASK;
2161
2162 /* Decrement the max supported by 1, to correlate with FW */
2163 sc->max_fw_cmds = sc->max_fw_cmds - 1;
2164 max_cmd = sc->max_fw_cmds;
2165
2166 /* Determine allocation size of command frames */
2138 sc->reply_q_depth = ((max_cmd + 1 + 15) / 16 * 16);
2167 sc->reply_q_depth = ((max_cmd + 1 + 15) / 16 * 16) * 2;
2139 sc->request_alloc_sz = sizeof(MRSAS_REQUEST_DESCRIPTOR_UNION) * max_cmd;
2140 sc->reply_alloc_sz = sizeof(MPI2_REPLY_DESCRIPTORS_UNION) * (sc->reply_q_depth);
2141 sc->io_frames_alloc_sz = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE + (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * (max_cmd + 1));
2142 sc->chain_frames_alloc_sz = 1024 * max_cmd;
2143 sc->max_sge_in_main_msg = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE -
2144 offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL)) / 16;
2145
2146 sc->max_sge_in_chain = MRSAS_MAX_SZ_CHAIN_FRAME / sizeof(MPI2_SGE_IO_UNION);

--- 128 unchanged lines hidden (view full) ---

2275 mfi_capabilities.support_additional_msix = 1;
2276 }
2277 if (sc->verbuf_mem) {
2278 snprintf((char *)sc->verbuf_mem, strlen(MRSAS_VERSION) + 2, "%s\n",
2279 MRSAS_VERSION);
2280 init_frame->driver_ver_lo = (bus_addr_t)sc->verbuf_phys_addr;
2281 init_frame->driver_ver_hi = 0;
2282 }
2168 sc->request_alloc_sz = sizeof(MRSAS_REQUEST_DESCRIPTOR_UNION) * max_cmd;
2169 sc->reply_alloc_sz = sizeof(MPI2_REPLY_DESCRIPTORS_UNION) * (sc->reply_q_depth);
2170 sc->io_frames_alloc_sz = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE + (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * (max_cmd + 1));
2171 sc->chain_frames_alloc_sz = 1024 * max_cmd;
2172 sc->max_sge_in_main_msg = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE -
2173 offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL)) / 16;
2174
2175 sc->max_sge_in_chain = MRSAS_MAX_SZ_CHAIN_FRAME / sizeof(MPI2_SGE_IO_UNION);

--- 128 unchanged lines hidden (view full) ---

2304 mfi_capabilities.support_additional_msix = 1;
2305 }
2306 if (sc->verbuf_mem) {
2307 snprintf((char *)sc->verbuf_mem, strlen(MRSAS_VERSION) + 2, "%s\n",
2308 MRSAS_VERSION);
2309 init_frame->driver_ver_lo = (bus_addr_t)sc->verbuf_phys_addr;
2310 init_frame->driver_ver_hi = 0;
2311 }
2312 init_frame->driver_operations.mfi_capabilities.support_ndrive_r1_lb = 1;
2283 init_frame->driver_operations.mfi_capabilities.support_max_255lds = 1;
2313 init_frame->driver_operations.mfi_capabilities.support_max_255lds = 1;
2314 init_frame->driver_operations.mfi_capabilities.security_protocol_cmds_fw = 1;
2284 phys_addr = (bus_addr_t)sc->ioc_init_phys_mem + 1024;
2285 init_frame->queue_info_new_phys_addr_lo = phys_addr;
2286 init_frame->data_xfer_len = sizeof(Mpi2IOCInitRequest_t);
2287
2288 req_desc.addr.Words = (bus_addr_t)sc->ioc_init_phys_mem;
2289 req_desc.MFAIo.RequestFlags =
2290 (MRSAS_REQ_DESCRIPT_FLAGS_MFA << MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT);
2291

--- 125 unchanged lines hidden (view full) ---

2417 * mrsas_fire_cmd: Sends command to FW
2418 * input: Adapter softstate
2419 * request descriptor address low
2420 * request descriptor address high
2421 *
2422 * This functions fires the command to Firmware by writing to the
2423 * inbound_low_queue_port and inbound_high_queue_port.
2424 */
2315 phys_addr = (bus_addr_t)sc->ioc_init_phys_mem + 1024;
2316 init_frame->queue_info_new_phys_addr_lo = phys_addr;
2317 init_frame->data_xfer_len = sizeof(Mpi2IOCInitRequest_t);
2318
2319 req_desc.addr.Words = (bus_addr_t)sc->ioc_init_phys_mem;
2320 req_desc.MFAIo.RequestFlags =
2321 (MRSAS_REQ_DESCRIPT_FLAGS_MFA << MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT);
2322

--- 125 unchanged lines hidden (view full) ---

2448 * mrsas_fire_cmd: Sends command to FW
2449 * input: Adapter softstate
2450 * request descriptor address low
2451 * request descriptor address high
2452 *
2453 * This functions fires the command to Firmware by writing to the
2454 * inbound_low_queue_port and inbound_high_queue_port.
2455 */
2425void
2456void
2426mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo,
2427 u_int32_t req_desc_hi)
2428{
2429 mtx_lock(&sc->pci_lock);
2430 mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_low_queue_port),
2431 req_desc_lo);
2432 mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_high_queue_port),
2433 req_desc_hi);

--- 263 unchanged lines hidden (view full) ---

2697 outbound_scratch_pad));
2698 abs_state = status_reg & MFI_STATE_MASK;
2699 reset_adapter = status_reg & MFI_RESET_ADAPTER;
2700 if (sc->disableOnlineCtrlReset ||
2701 (abs_state == MFI_STATE_FAULT && !reset_adapter)) {
2702 /* Reset not supported, kill adapter */
2703 mrsas_dprint(sc, MRSAS_OCR, "Reset not supported, killing adapter.\n");
2704 mrsas_kill_hba(sc);
2457mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo,
2458 u_int32_t req_desc_hi)
2459{
2460 mtx_lock(&sc->pci_lock);
2461 mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_low_queue_port),
2462 req_desc_lo);
2463 mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_high_queue_port),
2464 req_desc_hi);

--- 263 unchanged lines hidden (view full) ---

2728 outbound_scratch_pad));
2729 abs_state = status_reg & MFI_STATE_MASK;
2730 reset_adapter = status_reg & MFI_RESET_ADAPTER;
2731 if (sc->disableOnlineCtrlReset ||
2732 (abs_state == MFI_STATE_FAULT && !reset_adapter)) {
2733 /* Reset not supported, kill adapter */
2734 mrsas_dprint(sc, MRSAS_OCR, "Reset not supported, killing adapter.\n");
2735 mrsas_kill_hba(sc);
2705 sc->adprecovery = MRSAS_HW_CRITICAL_ERROR;
2706 retval = FAIL;
2707 goto out;
2708 }
2709 /* Now try to reset the chip */
2710 for (i = 0; i < MRSAS_FUSION_MAX_RESET_TRIES; i++) {
2711 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset),
2712 MPI2_WRSEQ_FLUSH_KEY_VALUE);
2713 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset),

--- 68 unchanged lines hidden (view full) ---

2782 "mrsas: Failed to transition controller to ready.\n");
2783 continue;
2784 }
2785 mrsas_reset_reply_desc(sc);
2786 if (mrsas_ioc_init(sc)) {
2787 mrsas_dprint(sc, MRSAS_OCR, "mrsas_ioc_init() failed!\n");
2788 continue;
2789 }
2736 retval = FAIL;
2737 goto out;
2738 }
2739 /* Now try to reset the chip */
2740 for (i = 0; i < MRSAS_FUSION_MAX_RESET_TRIES; i++) {
2741 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset),
2742 MPI2_WRSEQ_FLUSH_KEY_VALUE);
2743 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset),

--- 68 unchanged lines hidden (view full) ---

2812 "mrsas: Failed to transition controller to ready.\n");
2813 continue;
2814 }
2815 mrsas_reset_reply_desc(sc);
2816 if (mrsas_ioc_init(sc)) {
2817 mrsas_dprint(sc, MRSAS_OCR, "mrsas_ioc_init() failed!\n");
2818 continue;
2819 }
2790 mrsas_clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags);
2791 mrsas_enable_intr(sc);
2792 sc->adprecovery = MRSAS_HBA_OPERATIONAL;
2793
2794 /* Re-fire management commands */
2795 for (j = 0; j < sc->max_fw_cmds; j++) {
2796 mpt_cmd = sc->mpt_cmd_list[j];
2797 if (mpt_cmd->sync_cmd_idx != (u_int32_t)MRSAS_ULONG_MAX) {
2798 mfi_cmd = sc->mfi_cmd_list[mpt_cmd->sync_cmd_idx];
2799 if (mfi_cmd->frame->dcmd.opcode ==
2800 MR_DCMD_LD_MAP_GET_INFO) {
2801 mrsas_release_mfi_cmd(mfi_cmd);

--- 13 unchanged lines hidden (view full) ---

2815 }
2816 }
2817 }
2818
2819 /* Reset load balance info */
2820 memset(sc->load_balance_info, 0,
2821 sizeof(LD_LOAD_BALANCE_INFO) * MAX_LOGICAL_DRIVES_EXT);
2822
2820 /* Re-fire management commands */
2821 for (j = 0; j < sc->max_fw_cmds; j++) {
2822 mpt_cmd = sc->mpt_cmd_list[j];
2823 if (mpt_cmd->sync_cmd_idx != (u_int32_t)MRSAS_ULONG_MAX) {
2824 mfi_cmd = sc->mfi_cmd_list[mpt_cmd->sync_cmd_idx];
2825 if (mfi_cmd->frame->dcmd.opcode ==
2826 MR_DCMD_LD_MAP_GET_INFO) {
2827 mrsas_release_mfi_cmd(mfi_cmd);

--- 13 unchanged lines hidden (view full) ---

2841 }
2842 }
2843 }
2844
2845 /* Reset load balance info */
2846 memset(sc->load_balance_info, 0,
2847 sizeof(LD_LOAD_BALANCE_INFO) * MAX_LOGICAL_DRIVES_EXT);
2848
2849 if (mrsas_get_ctrl_info(sc)) {
2850 mrsas_kill_hba(sc);
2851 retval = FAIL;
2852 goto out;
2853 }
2823 if (!mrsas_get_map_info(sc))
2824 mrsas_sync_map_info(sc);
2825
2854 if (!mrsas_get_map_info(sc))
2855 mrsas_sync_map_info(sc);
2856
2857 mrsas_clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags);
2858 mrsas_enable_intr(sc);
2859 sc->adprecovery = MRSAS_HBA_OPERATIONAL;
2860
2826 /* Adapter reset completed successfully */
2827 device_printf(sc->mrsas_dev, "Reset successful\n");
2828 retval = SUCCESS;
2829 goto out;
2830 }
2831 /* Reset failed, kill the adapter */
2832 device_printf(sc->mrsas_dev, "Reset failed, killing adapter.\n");
2833 mrsas_kill_hba(sc);

--- 14 unchanged lines hidden (view full) ---

2848 * mrsas_kill_hba: Kill HBA when OCR is not supported
2849 * input: Adapter Context.
2850 *
2851 * This function will kill HBA when OCR is not supported.
2852 */
2853void
2854mrsas_kill_hba(struct mrsas_softc *sc)
2855{
2861 /* Adapter reset completed successfully */
2862 device_printf(sc->mrsas_dev, "Reset successful\n");
2863 retval = SUCCESS;
2864 goto out;
2865 }
2866 /* Reset failed, kill the adapter */
2867 device_printf(sc->mrsas_dev, "Reset failed, killing adapter.\n");
2868 mrsas_kill_hba(sc);

--- 14 unchanged lines hidden (view full) ---

2883 * mrsas_kill_hba: Kill HBA when OCR is not supported
2884 * input: Adapter Context.
2885 *
2886 * This function will kill HBA when OCR is not supported.
2887 */
2888void
2889mrsas_kill_hba(struct mrsas_softc *sc)
2890{
2891 sc->adprecovery = MRSAS_HW_CRITICAL_ERROR;
2892 pause("mrsas_kill_hba", 1000);
2856 mrsas_dprint(sc, MRSAS_OCR, "%s\n", __func__);
2857 mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell),
2858 MFI_STOP_ADP);
2859 /* Flush */
2860 mrsas_read_reg(sc, offsetof(mrsas_reg_set, doorbell));
2893 mrsas_dprint(sc, MRSAS_OCR, "%s\n", __func__);
2894 mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell),
2895 MFI_STOP_ADP);
2896 /* Flush */
2897 mrsas_read_reg(sc, offsetof(mrsas_reg_set, doorbell));
2898 mrsas_complete_outstanding_ioctls(sc);
2861}
2862
2899}
2900
2901/**
2902 * mrsas_complete_outstanding_ioctls Complete pending IOCTLS after kill_hba
2903 * input: Controller softc
2904 *
2905 * Returns void
2906 */
2907void
2908mrsas_complete_outstanding_ioctls(struct mrsas_softc *sc)
2909{
2910 int i;
2911 struct mrsas_mpt_cmd *cmd_mpt;
2912 struct mrsas_mfi_cmd *cmd_mfi;
2913 u_int32_t count, MSIxIndex;
2914
2915 count = sc->msix_vectors > 0 ? sc->msix_vectors : 1;
2916 for (i = 0; i < sc->max_fw_cmds; i++) {
2917 cmd_mpt = sc->mpt_cmd_list[i];
2918
2919 if (cmd_mpt->sync_cmd_idx != (u_int32_t)MRSAS_ULONG_MAX) {
2920 cmd_mfi = sc->mfi_cmd_list[cmd_mpt->sync_cmd_idx];
2921 if (cmd_mfi->sync_cmd && cmd_mfi->frame->hdr.cmd != MFI_CMD_ABORT) {
2922 for (MSIxIndex = 0; MSIxIndex < count; MSIxIndex++)
2923 mrsas_complete_mptmfi_passthru(sc, cmd_mfi,
2924 cmd_mpt->io_request->RaidContext.status);
2925 }
2926 }
2927 }
2928}
2929
2863/*
2864 * mrsas_wait_for_outstanding: Wait for outstanding commands
2865 * input: Adapter Context.
2866 *
2867 * This function will wait for 180 seconds for outstanding commands to be
2868 * completed.
2869 */
2870int

--- 68 unchanged lines hidden (view full) ---

2939 * input: Adapter soft state
2940 * Controller information structure
2941 *
2942 * Issues an internal command (DCMD) to get the FW's controller structure. This
2943 * information is mainly used to find out the maximum IO transfer per command
2944 * supported by the FW.
2945 */
2946static int
2930/*
2931 * mrsas_wait_for_outstanding: Wait for outstanding commands
2932 * input: Adapter Context.
2933 *
2934 * This function will wait for 180 seconds for outstanding commands to be
2935 * completed.
2936 */
2937int

--- 68 unchanged lines hidden (view full) ---

3006 * input: Adapter soft state
3007 * Controller information structure
3008 *
3009 * Issues an internal command (DCMD) to get the FW's controller structure. This
3010 * information is mainly used to find out the maximum IO transfer per command
3011 * supported by the FW.
3012 */
3013static int
2947mrsas_get_ctrl_info(struct mrsas_softc *sc,
2948 struct mrsas_ctrl_info *ctrl_info)
3014mrsas_get_ctrl_info(struct mrsas_softc *sc)
2949{
2950 int retcode = 0;
2951 struct mrsas_mfi_cmd *cmd;
2952 struct mrsas_dcmd_frame *dcmd;
2953
2954 cmd = mrsas_get_mfi_cmd(sc);
2955
2956 if (!cmd) {

--- 16 unchanged lines hidden (view full) ---

2973 dcmd->timeout = 0;
2974 dcmd->pad_0 = 0;
2975 dcmd->data_xfer_len = sizeof(struct mrsas_ctrl_info);
2976 dcmd->opcode = MR_DCMD_CTRL_GET_INFO;
2977 dcmd->sgl.sge32[0].phys_addr = sc->ctlr_info_phys_addr;
2978 dcmd->sgl.sge32[0].length = sizeof(struct mrsas_ctrl_info);
2979
2980 if (!mrsas_issue_polled(sc, cmd))
3015{
3016 int retcode = 0;
3017 struct mrsas_mfi_cmd *cmd;
3018 struct mrsas_dcmd_frame *dcmd;
3019
3020 cmd = mrsas_get_mfi_cmd(sc);
3021
3022 if (!cmd) {

--- 16 unchanged lines hidden (view full) ---

3039 dcmd->timeout = 0;
3040 dcmd->pad_0 = 0;
3041 dcmd->data_xfer_len = sizeof(struct mrsas_ctrl_info);
3042 dcmd->opcode = MR_DCMD_CTRL_GET_INFO;
3043 dcmd->sgl.sge32[0].phys_addr = sc->ctlr_info_phys_addr;
3044 dcmd->sgl.sge32[0].length = sizeof(struct mrsas_ctrl_info);
3045
3046 if (!mrsas_issue_polled(sc, cmd))
2981 memcpy(ctrl_info, sc->ctlr_info_mem, sizeof(struct mrsas_ctrl_info));
3047 memcpy(sc->ctrl_info, sc->ctlr_info_mem, sizeof(struct mrsas_ctrl_info));
2982 else
2983 retcode = 1;
2984
3048 else
3049 retcode = 1;
3050
3051 mrsas_update_ext_vd_details(sc);
3052
2985 mrsas_free_ctlr_info_cmd(sc);
2986 mrsas_release_mfi_cmd(cmd);
2987 return (retcode);
2988}
2989
2990/*
3053 mrsas_free_ctlr_info_cmd(sc);
3054 mrsas_release_mfi_cmd(cmd);
3055 return (retcode);
3056}
3057
3058/*
3059 * mrsas_update_ext_vd_details : Update details w.r.t Extended VD
3060 * input:
3061 * sc - Controller's softc
3062*/
3063static void
3064mrsas_update_ext_vd_details(struct mrsas_softc *sc)
3065{
3066 sc->max256vdSupport =
3067 sc->ctrl_info->adapterOperations3.supportMaxExtLDs;
3068 /* Below is additional check to address future FW enhancement */
3069 if (sc->ctrl_info->max_lds > 64)
3070 sc->max256vdSupport = 1;
3071
3072 sc->drv_supported_vd_count = MRSAS_MAX_LD_CHANNELS
3073 * MRSAS_MAX_DEV_PER_CHANNEL;
3074 sc->drv_supported_pd_count = MRSAS_MAX_PD_CHANNELS
3075 * MRSAS_MAX_DEV_PER_CHANNEL;
3076 if (sc->max256vdSupport) {
3077 sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES_EXT;
3078 sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES;
3079 } else {
3080 sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES;
3081 sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES;
3082 }
3083
3084 sc->old_map_sz = sizeof(MR_FW_RAID_MAP) +
3085 (sizeof(MR_LD_SPAN_MAP) *
3086 (sc->fw_supported_vd_count - 1));
3087 sc->new_map_sz = sizeof(MR_FW_RAID_MAP_EXT);
3088 sc->drv_map_sz = sizeof(MR_DRV_RAID_MAP) +
3089 (sizeof(MR_LD_SPAN_MAP) *
3090 (sc->drv_supported_vd_count - 1));
3091
3092 sc->max_map_sz = max(sc->old_map_sz, sc->new_map_sz);
3093
3094 if (sc->max256vdSupport)
3095 sc->current_map_sz = sc->new_map_sz;
3096 else
3097 sc->current_map_sz = sc->old_map_sz;
3098}
3099
3100/*
2991 * mrsas_alloc_ctlr_info_cmd: Allocates memory for controller info command
2992 * input: Adapter soft state
2993 *
2994 * Allocates DMAable memory for the controller info internal command.
2995 */
2996int
2997mrsas_alloc_ctlr_info_cmd(struct mrsas_softc *sc)
2998{

--- 758 unchanged lines hidden (view full) ---

3757/*
3758 * mrsas_alloc_tmp_dcmd: Allocates memory for temporary command input:
3759 * Adapter soft state Temp command Size of alloction
3760 *
3761 * Allocates DMAable memory for a temporary internal command. The allocated
3762 * memory is initialized to all zeros upon successful loading of the dma
3763 * mapped memory.
3764 */
3101 * mrsas_alloc_ctlr_info_cmd: Allocates memory for controller info command
3102 * input: Adapter soft state
3103 *
3104 * Allocates DMAable memory for the controller info internal command.
3105 */
3106int
3107mrsas_alloc_ctlr_info_cmd(struct mrsas_softc *sc)
3108{

--- 758 unchanged lines hidden (view full) ---

3867/*
3868 * mrsas_alloc_tmp_dcmd: Allocates memory for temporary command input:
3869 * Adapter soft state Temp command Size of alloction
3870 *
3871 * Allocates DMAable memory for a temporary internal command. The allocated
3872 * memory is initialized to all zeros upon successful loading of the dma
3873 * mapped memory.
3874 */
3765int
3875int
3766mrsas_alloc_tmp_dcmd(struct mrsas_softc *sc,
3767 struct mrsas_tmp_dcmd *tcmd, int size)
3768{
3769 if (bus_dma_tag_create(sc->mrsas_parent_tag,
3770 1, 0,
3771 BUS_SPACE_MAXADDR_32BIT,
3772 BUS_SPACE_MAXADDR,
3773 NULL, NULL,

--- 216 unchanged lines hidden (view full) ---

3990mrsas_complete_aen(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd)
3991{
3992 /*
3993 * Don't signal app if it is just an aborted previously registered
3994 * aen
3995 */
3996 if ((!cmd->abort_aen) && (sc->remove_in_progress == 0)) {
3997 sc->mrsas_aen_triggered = 1;
3876mrsas_alloc_tmp_dcmd(struct mrsas_softc *sc,
3877 struct mrsas_tmp_dcmd *tcmd, int size)
3878{
3879 if (bus_dma_tag_create(sc->mrsas_parent_tag,
3880 1, 0,
3881 BUS_SPACE_MAXADDR_32BIT,
3882 BUS_SPACE_MAXADDR,
3883 NULL, NULL,

--- 216 unchanged lines hidden (view full) ---

4100mrsas_complete_aen(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd)
4101{
4102 /*
4103 * Don't signal app if it is just an aborted previously registered
4104 * aen
4105 */
4106 if ((!cmd->abort_aen) && (sc->remove_in_progress == 0)) {
4107 sc->mrsas_aen_triggered = 1;
4108 mtx_lock(&sc->aen_lock);
3998 if (sc->mrsas_poll_waiting) {
3999 sc->mrsas_poll_waiting = 0;
4000 selwakeup(&sc->mrsas_select);
4001 }
4109 if (sc->mrsas_poll_waiting) {
4110 sc->mrsas_poll_waiting = 0;
4111 selwakeup(&sc->mrsas_select);
4112 }
4113 mtx_unlock(&sc->aen_lock);
4002 } else
4003 cmd->abort_aen = 0;
4004
4005 sc->aen_cmd = NULL;
4006 mrsas_release_mfi_cmd(cmd);
4007
4008 if (!sc->remove_in_progress)
4009 taskqueue_enqueue(sc->ev_tq, &sc->ev_task);

--- 25 unchanged lines hidden --- 		4114 } else
4115 cmd->abort_aen = 0;
4116
4117 sc->aen_cmd = NULL;
4118 mrsas_release_mfi_cmd(cmd);
4119
4120 if (!sc->remove_in_progress)
4121 taskqueue_enqueue(sc->ev_tq, &sc->ev_task);

--- 25 unchanged lines hidden ---