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mpi_cnfg.h (147883) mpi_cnfg.h (154603)
1/* $FreeBSD: head/sys/dev/mpt/mpilib/mpi_cnfg.h 147883 2005-07-10 15:05:39Z scottl $ */
1/* $FreeBSD: head/sys/dev/mpt/mpilib/mpi_cnfg.h 154603 2006-01-21 00:29:52Z mjacob $ */
2/*-
3 * Copyright (c) 2000-2005, LSI Logic Corporation and its contributors.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:
9 * 1. Redistributions of source code must retain the above copyright

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24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT
30 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
2/*-
3 * Copyright (c) 2000-2005, LSI Logic Corporation and its contributors.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:
9 * 1. Redistributions of source code must retain the above copyright

--- 14 unchanged lines hidden (view full) ---

24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT
30 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 *
33 * Name: MPI_CNFG.H
32 * Name: mpi_cnfg.h
34 * Title: MPI Config message, structures, and Pages
35 * Creation Date: July 27, 2000
36 *
33 * Title: MPI Config message, structures, and Pages
34 * Creation Date: July 27, 2000
35 *
37 * MPI_CNFG.H Version: 01.02.13
36 * mpi_cnfg.h Version: 01.05.10
38 *
39 * Version History
40 * ---------------
41 *
42 * Date Version Description
43 * -------- -------- ------------------------------------------------------
44 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000.
45 * 06-06-00 01.00.01 Update version number for 1.0 release.

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174 * with ADISCHardALPA.
175 * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define.
176 * 01-16-04 01.02.13 Added InitiatorDeviceTimeout and InitiatorIoPendTimeout
177 * fields and related defines to CONFIG_PAGE_FC_PORT_1.
178 * Added define for
179 * MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK.
180 * Added new fields to the substructures of
181 * CONFIG_PAGE_FC_PORT_10.
37 *
38 * Version History
39 * ---------------
40 *
41 * Date Version Description
42 * -------- -------- ------------------------------------------------------
43 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000.
44 * 06-06-00 01.00.01 Update version number for 1.0 release.

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173 * with ADISCHardALPA.
174 * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define.
175 * 01-16-04 01.02.13 Added InitiatorDeviceTimeout and InitiatorIoPendTimeout
176 * fields and related defines to CONFIG_PAGE_FC_PORT_1.
177 * Added define for
178 * MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK.
179 * Added new fields to the substructures of
180 * CONFIG_PAGE_FC_PORT_10.
181 * 04-29-04 01.02.14 Added define for IDP bit for CONFIG_PAGE_SCSI_PORT_0,
182 * CONFIG_PAGE_SCSI_DEVICE_0, and
183 * CONFIG_PAGE_SCSI_DEVICE_1. Also bumped Page Version for
184 * these pages.
185 * 05-11-04 01.03.01 Added structure for CONFIG_PAGE_INBAND_0.
186 * 08-19-04 01.05.01 Modified MSG_CONFIG request to support extended config
187 * pages.
188 * Added a new structure for extended config page header.
189 * Added new extended config pages types and structures for
190 * SAS IO Unit, SAS Expander, SAS Device, and SAS PHY.
191 * Replaced a reserved byte in CONFIG_PAGE_MANUFACTURING_4
192 * to add a Flags field.
193 * Two new Manufacturing config pages (5 and 6).
194 * Two new bits defined for IO Unit Page 1 Flags field.
195 * Modified CONFIG_PAGE_IO_UNIT_2 to add three new fields
196 * to specify the BIOS boot device.
197 * Four new Flags bits defined for IO Unit Page 2.
198 * Added IO Unit Page 4.
199 * Added EEDP Flags settings to IOC Page 1.
200 * Added new BIOS Page 1 config page.
201 * 10-05-04 01.05.02 Added define for
202 * MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE.
203 * Added new Flags field to CONFIG_PAGE_MANUFACTURING_5 and
204 * associated defines.
205 * Added more defines for SAS IO Unit Page 0
206 * DiscoveryStatus field.
207 * Added define for MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK
208 * and MPI_SAS_IOUNIT0_DS_TABLE_LINK.
209 * Added defines for Physical Mapping Modes to SAS IO Unit
210 * Page 2.
211 * Added define for
212 * MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH.
213 * 10-27-04 01.05.03 Added defines for new SAS PHY page addressing mode.
214 * Added defines for MaxTargetSpinUp to BIOS Page 1.
215 * Added 5 new ControlFlags defines for SAS IO Unit
216 * Page 1.
217 * Added MaxNumPhysicalMappedIDs field to SAS IO Unit
218 * Page 2.
219 * Added AccessStatus field to SAS Device Page 0 and added
220 * new Flags bits for supported SATA features.
221 * 12-07-04 01.05.04 Added config page structures for BIOS Page 2, RAID
222 * Volume Page 1, and RAID Physical Disk Page 1.
223 * Replaced IO Unit Page 1 BootTargetID,BootBus, and
224 * BootAdapterNum with reserved field.
225 * Added DataScrubRate and ResyncRate to RAID Volume
226 * Page 0.
227 * Added MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT
228 * define.
229 * 12-09-04 01.05.05 Added Target Mode Large CDB Enable to FC Port Page 1
230 * Flags field.
231 * Added Auto Port Config flag define for SAS IOUNIT
232 * Page 1 ControlFlags.
233 * Added Disabled bad Phy define to Expander Page 1
234 * Discovery Info field.
235 * Added SAS/SATA device support to SAS IOUnit Page 1
236 * ControlFlags.
237 * Added Unsupported device to SAS Dev Page 0 Flags field
238 * Added disable use SATA Hash Address for SAS IOUNIT
239 * page 1 in ControlFields.
240 * 01-15-05 01.05.06 Added defaults for data scrub rate and resync rate to
241 * Manufacturing Page 4.
242 * Added new defines for BIOS Page 1 IOCSettings field.
243 * Added ExtDiskIdentifier field to RAID Physical Disk
244 * Page 0.
245 * Added new defines for SAS IO Unit Page 1 ControlFlags
246 * and to SAS Device Page 0 Flags to control SATA devices.
247 * Added defines and structures for the new Log Page 0, a
248 * new type of configuration page.
249 * 02-09-05 01.05.07 Added InactiveStatus field to RAID Volume Page 0.
250 * Added WWID field to RAID Volume Page 1.
251 * Added PhysicalPort field to SAS Expander pages 0 and 1.
252 * 03-11-05 01.05.08 Removed the EEDP flags from IOC Page 1.
253 * Added Enclosure/Slot boot device format to BIOS Page 2.
254 * New status value for RAID Volume Page 0 VolumeStatus
255 * (VolumeState subfield).
256 * New value for RAID Physical Page 0 InactiveStatus.
257 * Added Inactive Volume Member flag RAID Physical Disk
258 * Page 0 PhysDiskStatus field.
259 * New physical mapping mode in SAS IO Unit Page 2.
260 * Added CONFIG_PAGE_SAS_ENCLOSURE_0.
261 * Added Slot and Enclosure fields to SAS Device Page 0.
262 * 06-24-05 01.05.09 Added EEDP defines to IOC Page 1.
263 * Added more RAID type defines to IOC Page 2.
264 * Added Port Enable Delay settings to BIOS Page 1.
265 * Added Bad Block Table Full define to RAID Volume Page 0.
266 * Added Previous State defines to RAID Physical Disk
267 * Page 0.
268 * Added Max Sata Targets define for DiscoveryStatus field
269 * of SAS IO Unit Page 0.
270 * Added Device Self Test to Control Flags of SAS IO Unit
271 * Page 1.
272 * Added Direct Attach Starting Slot Number define for SAS
273 * IO Unit Page 2.
274 * Added new fields in SAS Device Page 2 for enclosure
275 * mapping.
276 * Added OwnerDevHandle and Flags field to SAS PHY Page 0.
277 * Added IOC GPIO Flags define to SAS Enclosure Page 0.
278 * Fixed the value for MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT.
279 * 08-03-05 01.05.10 Removed ISDataScrubRate and ISResyncRate from
280 * Manufacturing Page 4.
281 * Added MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE bit.
282 * Added NumDevsPerEnclosure field to SAS IO Unit page 2.
283 * Added MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP
284 * define.
285 * Added EnclosureHandle field to SAS Expander page 0.
286 * Removed redundant NumTableEntriesProg field from SAS
287 * Expander Page 1.
182 * --------------------------------------------------------------------------
183 */
184
185#ifndef MPI_CNFG_H
186#define MPI_CNFG_H
187
188
189/*****************************************************************************

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205{
206 ConfigPageHeader_t Struct;
207 U8 Bytes[4];
208 U16 Word16[2];
209 U32 Word32;
210} ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion,
211 CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION;
212
288 * --------------------------------------------------------------------------
289 */
290
291#ifndef MPI_CNFG_H
292#define MPI_CNFG_H
293
294
295/*****************************************************************************

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311{
312 ConfigPageHeader_t Struct;
313 U8 Bytes[4];
314 U16 Word16[2];
315 U32 Word32;
316} ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion,
317 CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION;
318
319typedef struct _CONFIG_EXTENDED_PAGE_HEADER
320{
321 U8 PageVersion; /* 00h */
322 U8 Reserved1; /* 01h */
323 U8 PageNumber; /* 02h */
324 U8 PageType; /* 03h */
325 U16 ExtPageLength; /* 04h */
326 U8 ExtPageType; /* 06h */
327 U8 Reserved2; /* 07h */
328} CONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER,
329 ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t;
213
330
331
332
214/****************************************************************************
215* PageType field values
216****************************************************************************/
217#define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00)
218#define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10)
219#define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20)
220#define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30)
221#define MPI_CONFIG_PAGEATTR_MASK (0xF0)

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226#define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03)
227#define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04)
228#define MPI_CONFIG_PAGETYPE_FC_PORT (0x05)
229#define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06)
230#define MPI_CONFIG_PAGETYPE_LAN (0x07)
231#define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
232#define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09)
233#define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
333/****************************************************************************
334* PageType field values
335****************************************************************************/
336#define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00)
337#define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10)
338#define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20)
339#define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30)
340#define MPI_CONFIG_PAGEATTR_MASK (0xF0)

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345#define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03)
346#define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04)
347#define MPI_CONFIG_PAGETYPE_FC_PORT (0x05)
348#define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06)
349#define MPI_CONFIG_PAGETYPE_LAN (0x07)
350#define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
351#define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09)
352#define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
353#define MPI_CONFIG_PAGETYPE_INBAND (0x0B)
354#define MPI_CONFIG_PAGETYPE_EXTENDED (0x0F)
234#define MPI_CONFIG_PAGETYPE_MASK (0x0F)
235
236#define MPI_CONFIG_TYPENUM_MASK (0x0FFF)
237
238
239/****************************************************************************
355#define MPI_CONFIG_PAGETYPE_MASK (0x0F)
356
357#define MPI_CONFIG_TYPENUM_MASK (0x0FFF)
358
359
360/****************************************************************************
361* ExtPageType field values
362****************************************************************************/
363#define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
364#define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
365#define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
366#define MPI_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
367#define MPI_CONFIG_EXTPAGETYPE_LOG (0x14)
368#define MPI_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
369
370
371/****************************************************************************
240* PageAddress field values
241****************************************************************************/
242#define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF)
243
372* PageAddress field values
373****************************************************************************/
374#define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF)
375
376#define MPI_SCSI_DEVICE_FORM_MASK (0xF0000000)
377#define MPI_SCSI_DEVICE_FORM_BUS_TID (0x00000000)
244#define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF)
245#define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0)
246#define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00)
247#define MPI_SCSI_DEVICE_BUS_SHIFT (8)
378#define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF)
379#define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0)
380#define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00)
381#define MPI_SCSI_DEVICE_BUS_SHIFT (8)
382#define MPI_SCSI_DEVICE_FORM_TARGET_MODE (0x10000000)
383#define MPI_SCSI_DEVICE_TM_RESPOND_ID_MASK (0x000000FF)
384#define MPI_SCSI_DEVICE_TM_RESPOND_ID_SHIFT (0)
385#define MPI_SCSI_DEVICE_TM_BUS_MASK (0x0000FF00)
386#define MPI_SCSI_DEVICE_TM_BUS_SHIFT (8)
387#define MPI_SCSI_DEVICE_TM_INIT_ID_MASK (0x00FF0000)
388#define MPI_SCSI_DEVICE_TM_INIT_ID_SHIFT (16)
248
249#define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000)
250#define MPI_FC_PORT_PGAD_PORT_SHIFT (28)
251#define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000)
252#define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000)
253#define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF)
254#define MPI_FC_PORT_PGAD_INDEX_SHIFT (0)
255

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265#define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
266#define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8)
267#define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
268#define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0)
269
270#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
271#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0)
272
389
390#define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000)
391#define MPI_FC_PORT_PGAD_PORT_SHIFT (28)
392#define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000)
393#define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000)
394#define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF)
395#define MPI_FC_PORT_PGAD_INDEX_SHIFT (0)
396

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406#define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
407#define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8)
408#define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
409#define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0)
410
411#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
412#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0)
413
414#define MPI_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
415#define MPI_SAS_EXPAND_PGAD_FORM_SHIFT (28)
416#define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
417#define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x00000001)
418#define MPI_SAS_EXPAND_PGAD_FORM_HANDLE (0x00000002)
419#define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE (0x0000FFFF)
420#define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE (0)
421#define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY (0x00FF0000)
422#define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY (16)
423#define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE (0x0000FFFF)
424#define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE (0)
425#define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE (0x0000FFFF)
426#define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE (0)
273
427
428#define MPI_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
429#define MPI_SAS_DEVICE_PGAD_FORM_SHIFT (28)
430#define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
431#define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID (0x00000001)
432#define MPI_SAS_DEVICE_PGAD_FORM_HANDLE (0x00000002)
433#define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK (0x0000FFFF)
434#define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT (0)
435#define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
436#define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT (8)
437#define MPI_SAS_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
438#define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT (0)
439#define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK (0x0000FFFF)
440#define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT (0)
274
441
442#define MPI_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
443#define MPI_SAS_PHY_PGAD_FORM_SHIFT (28)
444#define MPI_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x0)
445#define MPI_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x1)
446#define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
447#define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0)
448#define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
449#define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_SHIFT (0)
450
451#define MPI_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
452#define MPI_SAS_ENCLOS_PGAD_FORM_SHIFT (28)
453#define MPI_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
454#define MPI_SAS_ENCLOS_PGAD_FORM_HANDLE (0x00000001)
455#define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_MASK (0x0000FFFF)
456#define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_SHIFT (0)
457#define MPI_SAS_ENCLOS_PGAD_H_HANDLE_MASK (0x0000FFFF)
458#define MPI_SAS_ENCLOS_PGAD_H_HANDLE_SHIFT (0)
459
460
461
275/****************************************************************************
276* Config Request Message
277****************************************************************************/
278typedef struct _MSG_CONFIG
279{
280 U8 Action; /* 00h */
281 U8 Reserved; /* 01h */
282 U8 ChainOffset; /* 02h */
283 U8 Function; /* 03h */
462/****************************************************************************
463* Config Request Message
464****************************************************************************/
465typedef struct _MSG_CONFIG
466{
467 U8 Action; /* 00h */
468 U8 Reserved; /* 01h */
469 U8 ChainOffset; /* 02h */
470 U8 Function; /* 03h */
284 U8 Reserved1[3]; /* 04h */
471 U16 ExtPageLength; /* 04h */
472 U8 ExtPageType; /* 06h */
285 U8 MsgFlags; /* 07h */
286 U32 MsgContext; /* 08h */
287 U8 Reserved2[8]; /* 0Ch */
288 CONFIG_PAGE_HEADER Header; /* 14h */
289 U32 PageAddress; /* 18h */
290 SGE_IO_UNION PageBufferSGE; /* 1Ch */
291} MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG,
292 Config_t, MPI_POINTER pConfig_t;

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306
307/* Config Reply Message */
308typedef struct _MSG_CONFIG_REPLY
309{
310 U8 Action; /* 00h */
311 U8 Reserved; /* 01h */
312 U8 MsgLength; /* 02h */
313 U8 Function; /* 03h */
473 U8 MsgFlags; /* 07h */
474 U32 MsgContext; /* 08h */
475 U8 Reserved2[8]; /* 0Ch */
476 CONFIG_PAGE_HEADER Header; /* 14h */
477 U32 PageAddress; /* 18h */
478 SGE_IO_UNION PageBufferSGE; /* 1Ch */
479} MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG,
480 Config_t, MPI_POINTER pConfig_t;

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494
495/* Config Reply Message */
496typedef struct _MSG_CONFIG_REPLY
497{
498 U8 Action; /* 00h */
499 U8 Reserved; /* 01h */
500 U8 MsgLength; /* 02h */
501 U8 Function; /* 03h */
314 U8 Reserved1[3]; /* 04h */
502 U16 ExtPageLength; /* 04h */
503 U8 ExtPageType; /* 06h */
315 U8 MsgFlags; /* 07h */
316 U32 MsgContext; /* 08h */
317 U8 Reserved2[2]; /* 0Ch */
318 U16 IOCStatus; /* 0Eh */
319 U32 IOCLogInfo; /* 10h */
320 CONFIG_PAGE_HEADER Header; /* 14h */
321} MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY,
322 ConfigReply_t, MPI_POINTER pConfigReply_t;

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328* C o n f i g u r a t i o n P a g e s
329*
330*****************************************************************************/
331
332/****************************************************************************
333* Manufacturing Config pages
334****************************************************************************/
335#define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000)
504 U8 MsgFlags; /* 07h */
505 U32 MsgContext; /* 08h */
506 U8 Reserved2[2]; /* 0Ch */
507 U16 IOCStatus; /* 0Eh */
508 U32 IOCLogInfo; /* 10h */
509 CONFIG_PAGE_HEADER Header; /* 14h */
510} MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY,
511 ConfigReply_t, MPI_POINTER pConfigReply_t;

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517* C o n f i g u r a t i o n P a g e s
518*
519*****************************************************************************/
520
521/****************************************************************************
522* Manufacturing Config pages
523****************************************************************************/
524#define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000)
336#define MPI_MANUFACTPAGE_VENDORID_TREBIA (0x1783)
337
525/* Fibre Channel */
338#define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621)
339#define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624)
340#define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622)
341#define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628)
342#define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626)
526#define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621)
527#define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624)
528#define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622)
529#define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628)
530#define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626)
343
531#define MPI_MANUFACTPAGE_DEVICEID_FC939X (0x0642)
532#define MPI_MANUFACTPAGE_DEVICEID_FC949X (0x0640)
533#define MPI_MANUFACTPAGE_DEVICEID_FC949ES (0x0646)
534/* SCSI */
344#define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030)
345#define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031)
346#define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032)
347#define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033)
348#define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040)
349#define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041)
535#define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030)
536#define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031)
537#define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032)
538#define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033)
539#define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040)
540#define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041)
541/* SAS */
542#define MPI_MANUFACTPAGE_DEVID_SAS1064 (0x0050)
543#define MPI_MANUFACTPAGE_DEVID_SAS1064A (0x005C)
544#define MPI_MANUFACTPAGE_DEVID_SAS1064E (0x0056)
545#define MPI_MANUFACTPAGE_DEVID_SAS1066 (0x005E)
546#define MPI_MANUFACTPAGE_DEVID_SAS1066E (0x005A)
547#define MPI_MANUFACTPAGE_DEVID_SAS1068 (0x0054)
548#define MPI_MANUFACTPAGE_DEVID_SAS1068E (0x0058)
549#define MPI_MANUFACTPAGE_DEVID_SAS1078 (0x0060)
350
550
351#define MPI_MANUFACTPAGE_DEVID_SA2010 (0x0804)
352#define MPI_MANUFACTPAGE_DEVID_SA2010ZC (0x0805)
353#define MPI_MANUFACTPAGE_DEVID_SA2020 (0x0806)
354#define MPI_MANUFACTPAGE_DEVID_SA2020ZC (0x0807)
355
551
356#define MPI_MANUFACTPAGE_DEVID_SNP1000 (0x0010)
357#define MPI_MANUFACTPAGE_DEVID_SNP500 (0x0020)
358
359
360
361typedef struct _CONFIG_PAGE_MANUFACTURING_0
362{
363 CONFIG_PAGE_HEADER Header; /* 00h */
364 U8 ChipName[16]; /* 04h */
365 U8 ChipRevision[8]; /* 14h */
366 U8 BoardName[16]; /* 1Ch */
367 U8 BoardAssembly[16]; /* 2Ch */
368 U8 BoardTracerNumber[16]; /* 3Ch */

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434{
435 CONFIG_PAGE_HEADER Header; /* 00h */
436 U32 Reserved1; /* 04h */
437 U8 InfoOffset0; /* 08h */
438 U8 InfoSize0; /* 09h */
439 U8 InfoOffset1; /* 0Ah */
440 U8 InfoSize1; /* 0Bh */
441 U8 InquirySize; /* 0Ch */
552typedef struct _CONFIG_PAGE_MANUFACTURING_0
553{
554 CONFIG_PAGE_HEADER Header; /* 00h */
555 U8 ChipName[16]; /* 04h */
556 U8 ChipRevision[8]; /* 14h */
557 U8 BoardName[16]; /* 1Ch */
558 U8 BoardAssembly[16]; /* 2Ch */
559 U8 BoardTracerNumber[16]; /* 3Ch */

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625{
626 CONFIG_PAGE_HEADER Header; /* 00h */
627 U32 Reserved1; /* 04h */
628 U8 InfoOffset0; /* 08h */
629 U8 InfoSize0; /* 09h */
630 U8 InfoOffset1; /* 0Ah */
631 U8 InfoSize1; /* 0Bh */
632 U8 InquirySize; /* 0Ch */
442 U8 Reserved2; /* 0Dh */
443 U16 Reserved3; /* 0Eh */
633 U8 Flags; /* 0Dh */
634 U16 Reserved2; /* 0Eh */
444 U8 InquiryData[56]; /* 10h */
445 U32 ISVolumeSettings; /* 48h */
446 U32 IMEVolumeSettings; /* 4Ch */
447 U32 IMVolumeSettings; /* 50h */
635 U8 InquiryData[56]; /* 10h */
636 U32 ISVolumeSettings; /* 48h */
637 U32 IMEVolumeSettings; /* 4Ch */
638 U32 IMVolumeSettings; /* 50h */
639 U32 Reserved3; /* 54h */
640 U32 Reserved4; /* 58h */
641 U32 Reserved5; /* 5Ch */
642 U8 IMEDataScrubRate; /* 60h */
643 U8 IMEResyncRate; /* 61h */
644 U16 Reserved6; /* 62h */
645 U8 IMDataScrubRate; /* 64h */
646 U8 IMResyncRate; /* 65h */
647 U16 Reserved7; /* 66h */
648 U32 Reserved8; /* 68h */
649 U32 Reserved9; /* 6Ch */
448} CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4,
449 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t;
450
650} CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4,
651 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t;
652
451#define MPI_MANUFACTURING4_PAGEVERSION (0x00)
653#define MPI_MANUFACTURING4_PAGEVERSION (0x02)
452
654
655/* defines for the Flags field */
656#define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01)
453
657
658
659typedef struct _CONFIG_PAGE_MANUFACTURING_5
660{
661 CONFIG_PAGE_HEADER Header; /* 00h */
662 U64 BaseWWID; /* 04h */
663 U8 Flags; /* 0Ch */
664 U8 Reserved1; /* 0Dh */
665 U16 Reserved2; /* 0Eh */
666} CONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5,
667 ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t;
668
669#define MPI_MANUFACTURING5_PAGEVERSION (0x01)
670
671/* defines for the Flags field */
672#define MPI_MANPAGE5_TWO_WWID_PER_PHY (0x01)
673
674
675typedef struct _CONFIG_PAGE_MANUFACTURING_6
676{
677 CONFIG_PAGE_HEADER Header; /* 00h */
678 U32 ProductSpecificInfo;/* 04h */
679} CONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6,
680 ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t;
681
682#define MPI_MANUFACTURING6_PAGEVERSION (0x00)
683
684
454/****************************************************************************
455* IO Unit Config Pages
456****************************************************************************/
457
458typedef struct _CONFIG_PAGE_IO_UNIT_0
459{
460 CONFIG_PAGE_HEADER Header; /* 00h */
461 U64 UniqueValue; /* 04h */

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467
468typedef struct _CONFIG_PAGE_IO_UNIT_1
469{
470 CONFIG_PAGE_HEADER Header; /* 00h */
471 U32 Flags; /* 04h */
472} CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1,
473 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t;
474
685/****************************************************************************
686* IO Unit Config Pages
687****************************************************************************/
688
689typedef struct _CONFIG_PAGE_IO_UNIT_0
690{
691 CONFIG_PAGE_HEADER Header; /* 00h */
692 U64 UniqueValue; /* 04h */

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698
699typedef struct _CONFIG_PAGE_IO_UNIT_1
700{
701 CONFIG_PAGE_HEADER Header; /* 00h */
702 U32 Flags; /* 04h */
703} CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1,
704 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t;
705
475#define MPI_IOUNITPAGE1_PAGEVERSION (0x00)
706#define MPI_IOUNITPAGE1_PAGEVERSION (0x02)
476
477/* IO Unit Page 1 Flags defines */
707
708/* IO Unit Page 1 Flags defines */
478
479#define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000)
480#define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001)
481#define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002)
482#define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
483#define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
709#define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000)
710#define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001)
711#define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002)
712#define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
713#define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
714#define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020)
484#define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040)
485#define MPI_IOUNITPAGE1_FORCE_32 (0x00000080)
715#define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040)
716#define MPI_IOUNITPAGE1_FORCE_32 (0x00000080)
717#define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
718#define MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE (0x00000200)
486
719
487
488typedef struct _MPI_ADAPTER_INFO
489{
490 U8 PciBusNumber; /* 00h */
491 U8 PciDeviceAndFunctionNumber; /* 01h */
492 U16 AdapterFlags; /* 02h */
493} MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO,
494 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t;
495
496#define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
497#define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
498
499typedef struct _CONFIG_PAGE_IO_UNIT_2
500{
501 CONFIG_PAGE_HEADER Header; /* 00h */
502 U32 Flags; /* 04h */
503 U32 BiosVersion; /* 08h */
504 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */
720typedef struct _MPI_ADAPTER_INFO
721{
722 U8 PciBusNumber; /* 00h */
723 U8 PciDeviceAndFunctionNumber; /* 01h */
724 U16 AdapterFlags; /* 02h */
725} MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO,
726 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t;
727
728#define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
729#define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
730
731typedef struct _CONFIG_PAGE_IO_UNIT_2
732{
733 CONFIG_PAGE_HEADER Header; /* 00h */
734 U32 Flags; /* 04h */
735 U32 BiosVersion; /* 08h */
736 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */
737 U32 Reserved1; /* 1Ch */
505} CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2,
506 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t;
507
738} CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2,
739 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t;
740
508#define MPI_IOUNITPAGE2_PAGEVERSION (0x00)
741#define MPI_IOUNITPAGE2_PAGEVERSION (0x02)
509
510#define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002)
511#define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004)
512#define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008)
513#define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010)
514
742
743#define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002)
744#define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004)
745#define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008)
746#define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010)
747
748#define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
749#define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
750#define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020)
751#define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
515
752
753
516/*
517 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
518 * one and check Header.PageLength at runtime.
519 */
520#ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX
521#define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
522#endif
523

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534#define MPI_IOUNITPAGE3_PAGEVERSION (0x01)
535
536#define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC)
537#define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
538#define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00)
539#define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01)
540
541
754/*
755 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
756 * one and check Header.PageLength at runtime.
757 */
758#ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX
759#define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
760#endif
761

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772#define MPI_IOUNITPAGE3_PAGEVERSION (0x01)
773
774#define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC)
775#define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
776#define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00)
777#define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01)
778
779
780typedef struct _CONFIG_PAGE_IO_UNIT_4
781{
782 CONFIG_PAGE_HEADER Header; /* 00h */
783 U32 Reserved1; /* 04h */
784 SGE_SIMPLE_UNION FWImageSGE; /* 08h */
785} CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4,
786 IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t;
787
788#define MPI_IOUNITPAGE4_PAGEVERSION (0x00)
789
790
542/****************************************************************************
543* IOC Config Pages
544****************************************************************************/
545
546typedef struct _CONFIG_PAGE_IOC_0
547{
548 CONFIG_PAGE_HEADER Header; /* 00h */
549 U32 TotalNVStore; /* 04h */

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567 U32 Flags; /* 04h */
568 U32 CoalescingTimeout; /* 08h */
569 U8 CoalescingDepth; /* 0Ch */
570 U8 PCISlotNum; /* 0Dh */
571 U8 Reserved[2]; /* 0Eh */
572} CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1,
573 IOCPage1_t, MPI_POINTER pIOCPage1_t;
574
791/****************************************************************************
792* IOC Config Pages
793****************************************************************************/
794
795typedef struct _CONFIG_PAGE_IOC_0
796{
797 CONFIG_PAGE_HEADER Header; /* 00h */
798 U32 TotalNVStore; /* 04h */

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816 U32 Flags; /* 04h */
817 U32 CoalescingTimeout; /* 08h */
818 U8 CoalescingDepth; /* 0Ch */
819 U8 PCISlotNum; /* 0Dh */
820 U8 Reserved[2]; /* 0Eh */
821} CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1,
822 IOCPage1_t, MPI_POINTER pIOCPage1_t;
823
575#define MPI_IOCPAGE1_PAGEVERSION (0x01)
824#define MPI_IOCPAGE1_PAGEVERSION (0x03)
576
825
826/* defines for the Flags field */
827#define MPI_IOCPAGE1_EEDP_MODE_MASK (0x07000000)
828#define MPI_IOCPAGE1_EEDP_MODE_OFF (0x00000000)
829#define MPI_IOCPAGE1_EEDP_MODE_T10 (0x01000000)
830#define MPI_IOCPAGE1_EEDP_MODE_LSI_1 (0x02000000)
831#define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE (0x00000010)
577#define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001)
578
579#define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
580
581
582typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL
583{
584 U8 VolumeID; /* 00h */

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591} CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL,
592 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t;
593
594/* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */
595
596#define MPI_RAID_VOL_TYPE_IS (0x00)
597#define MPI_RAID_VOL_TYPE_IME (0x01)
598#define MPI_RAID_VOL_TYPE_IM (0x02)
832#define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001)
833
834#define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
835
836
837typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL
838{
839 U8 VolumeID; /* 00h */

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846} CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL,
847 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t;
848
849/* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */
850
851#define MPI_RAID_VOL_TYPE_IS (0x00)
852#define MPI_RAID_VOL_TYPE_IME (0x01)
853#define MPI_RAID_VOL_TYPE_IM (0x02)
854#define MPI_RAID_VOL_TYPE_RAID_5 (0x03)
855#define MPI_RAID_VOL_TYPE_RAID_6 (0x04)
856#define MPI_RAID_VOL_TYPE_RAID_10 (0x05)
857#define MPI_RAID_VOL_TYPE_RAID_50 (0x06)
858#define MPI_RAID_VOL_TYPE_UNKNOWN (0xFF)
599
600/* IOC Page 2 Volume Flags values */
601
602#define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08)
603
604/*
605 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
606 * one and check Header.PageLength at runtime.

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616 U8 NumActiveVolumes; /* 08h */
617 U8 MaxVolumes; /* 09h */
618 U8 NumActivePhysDisks; /* 0Ah */
619 U8 MaxPhysDisks; /* 0Bh */
620 CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */
621} CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2,
622 IOCPage2_t, MPI_POINTER pIOCPage2_t;
623
859
860/* IOC Page 2 Volume Flags values */
861
862#define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08)
863
864/*
865 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
866 * one and check Header.PageLength at runtime.

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876 U8 NumActiveVolumes; /* 08h */
877 U8 MaxVolumes; /* 09h */
878 U8 NumActivePhysDisks; /* 0Ah */
879 U8 MaxPhysDisks; /* 0Bh */
880 CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */
881} CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2,
882 IOCPage2_t, MPI_POINTER pIOCPage2_t;
883
624#define MPI_IOCPAGE2_PAGEVERSION (0x02)
884#define MPI_IOCPAGE2_PAGEVERSION (0x03)
625
626/* IOC Page 2 Capabilities flags */
627
628#define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001)
629#define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002)
630#define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004)
885
886/* IOC Page 2 Capabilities flags */
887
888#define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001)
889#define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002)
890#define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004)
891#define MPI_IOCPAGE2_CAP_FLAGS_RAID_5_SUPPORT (0x00000008)
892#define MPI_IOCPAGE2_CAP_FLAGS_RAID_6_SUPPORT (0x00000010)
893#define MPI_IOCPAGE2_CAP_FLAGS_RAID_10_SUPPORT (0x00000020)
894#define MPI_IOCPAGE2_CAP_FLAGS_RAID_50_SUPPORT (0x00000040)
631#define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000)
632#define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000)
633#define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000)
634
635
636typedef struct _IOC_3_PHYS_DISK
637{
638 U8 PhysDiskID; /* 00h */

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721 U16 Reserved3; /* 0Ah */
722 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */
723} CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5,
724 IOCPage5_t, MPI_POINTER pIOCPage5_t;
725
726#define MPI_IOCPAGE5_PAGEVERSION (0x00)
727
728
895#define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000)
896#define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000)
897#define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000)
898
899
900typedef struct _IOC_3_PHYS_DISK
901{
902 U8 PhysDiskID; /* 00h */

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985 U16 Reserved3; /* 0Ah */
986 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */
987} CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5,
988 IOCPage5_t, MPI_POINTER pIOCPage5_t;
989
990#define MPI_IOCPAGE5_PAGEVERSION (0x00)
991
992
993/****************************************************************************
994* BIOS Config Pages
995****************************************************************************/
729
996
997typedef struct _CONFIG_PAGE_BIOS_1
998{
999 CONFIG_PAGE_HEADER Header; /* 00h */
1000 U32 BiosOptions; /* 04h */
1001 U32 IOCSettings; /* 08h */
1002 U32 Reserved1; /* 0Ch */
1003 U32 DeviceSettings; /* 10h */
1004 U16 NumberOfDevices; /* 14h */
1005 U16 Reserved2; /* 16h */
1006 U16 IOTimeoutBlockDevicesNonRM; /* 18h */
1007 U16 IOTimeoutSequential; /* 1Ah */
1008 U16 IOTimeoutOther; /* 1Ch */
1009 U16 IOTimeoutBlockDevicesRM; /* 1Eh */
1010} CONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1,
1011 BIOSPage1_t, MPI_POINTER pBIOSPage1_t;
1012
1013#define MPI_BIOSPAGE1_PAGEVERSION (0x02)
1014
1015/* values for the BiosOptions field */
1016#define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400)
1017#define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200)
1018#define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100)
1019#define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1020
1021/* values for the IOCSettings field */
1022#define MPI_BIOSPAGE1_IOCSET_MASK_PORT_ENABLE_DELAY (0x00F00000)
1023#define MPI_BIOSPAGE1_IOCSET_SHIFT_PORT_ENABLE_DELAY (20)
1024#define MPI_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1025#define MPI_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1026#define MPI_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1027
1028#define MPI_BIOSPAGE1_IOCSET_MASK_MAX_TARGET_SPIN_UP (0x0000F000)
1029#define MPI_BIOSPAGE1_IOCSET_SHIFT_MAX_TARGET_SPIN_UP (12)
1030
1031#define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00)
1032#define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8)
1033
1034#define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1035#define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1036#define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1037#define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1038
1039#define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1040#define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1041#define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1042#define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1043#define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1044
1045#define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1046
1047/* values for the DeviceSettings field */
1048#define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1049#define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1050#define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1051#define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1052
1053typedef struct _MPI_BOOT_DEVICE_ADAPTER_ORDER
1054{
1055 U32 Reserved1; /* 00h */
1056 U32 Reserved2; /* 04h */
1057 U32 Reserved3; /* 08h */
1058 U32 Reserved4; /* 0Ch */
1059 U32 Reserved5; /* 10h */
1060 U32 Reserved6; /* 14h */
1061 U32 Reserved7; /* 18h */
1062 U32 Reserved8; /* 1Ch */
1063 U32 Reserved9; /* 20h */
1064 U32 Reserved10; /* 24h */
1065 U32 Reserved11; /* 28h */
1066 U32 Reserved12; /* 2Ch */
1067 U32 Reserved13; /* 30h */
1068 U32 Reserved14; /* 34h */
1069 U32 Reserved15; /* 38h */
1070 U32 Reserved16; /* 3Ch */
1071 U32 Reserved17; /* 40h */
1072} MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER;
1073
1074typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER
1075{
1076 U8 TargetID; /* 00h */
1077 U8 Bus; /* 01h */
1078 U8 AdapterNumber; /* 02h */
1079 U8 Reserved1; /* 03h */
1080 U32 Reserved2; /* 04h */
1081 U32 Reserved3; /* 08h */
1082 U32 Reserved4; /* 0Ch */
1083 U8 LUN[8]; /* 10h */
1084 U32 Reserved5; /* 18h */
1085 U32 Reserved6; /* 1Ch */
1086 U32 Reserved7; /* 20h */
1087 U32 Reserved8; /* 24h */
1088 U32 Reserved9; /* 28h */
1089 U32 Reserved10; /* 2Ch */
1090 U32 Reserved11; /* 30h */
1091 U32 Reserved12; /* 34h */
1092 U32 Reserved13; /* 38h */
1093 U32 Reserved14; /* 3Ch */
1094 U32 Reserved15; /* 40h */
1095} MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER;
1096
1097typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS
1098{
1099 U8 TargetID; /* 00h */
1100 U8 Bus; /* 01h */
1101 U16 PCIAddress; /* 02h */
1102 U32 Reserved1; /* 04h */
1103 U32 Reserved2; /* 08h */
1104 U32 Reserved3; /* 0Ch */
1105 U8 LUN[8]; /* 10h */
1106 U32 Reserved4; /* 18h */
1107 U32 Reserved5; /* 1Ch */
1108 U32 Reserved6; /* 20h */
1109 U32 Reserved7; /* 24h */
1110 U32 Reserved8; /* 28h */
1111 U32 Reserved9; /* 2Ch */
1112 U32 Reserved10; /* 30h */
1113 U32 Reserved11; /* 34h */
1114 U32 Reserved12; /* 38h */
1115 U32 Reserved13; /* 3Ch */
1116 U32 Reserved14; /* 40h */
1117} MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS;
1118
1119typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER
1120{
1121 U8 TargetID; /* 00h */
1122 U8 Bus; /* 01h */
1123 U8 PCISlotNumber; /* 02h */
1124 U8 Reserved1; /* 03h */
1125 U32 Reserved2; /* 04h */
1126 U32 Reserved3; /* 08h */
1127 U32 Reserved4; /* 0Ch */
1128 U8 LUN[8]; /* 10h */
1129 U32 Reserved5; /* 18h */
1130 U32 Reserved6; /* 1Ch */
1131 U32 Reserved7; /* 20h */
1132 U32 Reserved8; /* 24h */
1133 U32 Reserved9; /* 28h */
1134 U32 Reserved10; /* 2Ch */
1135 U32 Reserved11; /* 30h */
1136 U32 Reserved12; /* 34h */
1137 U32 Reserved13; /* 38h */
1138 U32 Reserved14; /* 3Ch */
1139 U32 Reserved15; /* 40h */
1140} MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER;
1141
1142typedef struct _MPI_BOOT_DEVICE_FC_WWN
1143{
1144 U64 WWPN; /* 00h */
1145 U32 Reserved1; /* 08h */
1146 U32 Reserved2; /* 0Ch */
1147 U8 LUN[8]; /* 10h */
1148 U32 Reserved3; /* 18h */
1149 U32 Reserved4; /* 1Ch */
1150 U32 Reserved5; /* 20h */
1151 U32 Reserved6; /* 24h */
1152 U32 Reserved7; /* 28h */
1153 U32 Reserved8; /* 2Ch */
1154 U32 Reserved9; /* 30h */
1155 U32 Reserved10; /* 34h */
1156 U32 Reserved11; /* 38h */
1157 U32 Reserved12; /* 3Ch */
1158 U32 Reserved13; /* 40h */
1159} MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN;
1160
1161typedef struct _MPI_BOOT_DEVICE_SAS_WWN
1162{
1163 U64 SASAddress; /* 00h */
1164 U32 Reserved1; /* 08h */
1165 U32 Reserved2; /* 0Ch */
1166 U8 LUN[8]; /* 10h */
1167 U32 Reserved3; /* 18h */
1168 U32 Reserved4; /* 1Ch */
1169 U32 Reserved5; /* 20h */
1170 U32 Reserved6; /* 24h */
1171 U32 Reserved7; /* 28h */
1172 U32 Reserved8; /* 2Ch */
1173 U32 Reserved9; /* 30h */
1174 U32 Reserved10; /* 34h */
1175 U32 Reserved11; /* 38h */
1176 U32 Reserved12; /* 3Ch */
1177 U32 Reserved13; /* 40h */
1178} MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN;
1179
1180typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT
1181{
1182 U64 EnclosureLogicalID; /* 00h */
1183 U32 Reserved1; /* 08h */
1184 U32 Reserved2; /* 0Ch */
1185 U8 LUN[8]; /* 10h */
1186 U16 SlotNumber; /* 18h */
1187 U16 Reserved3; /* 1Ah */
1188 U32 Reserved4; /* 1Ch */
1189 U32 Reserved5; /* 20h */
1190 U32 Reserved6; /* 24h */
1191 U32 Reserved7; /* 28h */
1192 U32 Reserved8; /* 2Ch */
1193 U32 Reserved9; /* 30h */
1194 U32 Reserved10; /* 34h */
1195 U32 Reserved11; /* 38h */
1196 U32 Reserved12; /* 3Ch */
1197 U32 Reserved13; /* 40h */
1198} MPI_BOOT_DEVICE_ENCLOSURE_SLOT,
1199 MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT;
1200
1201typedef union _MPI_BIOSPAGE2_BOOT_DEVICE
1202{
1203 MPI_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1204 MPI_BOOT_DEVICE_ADAPTER_NUMBER AdapterNumber;
1205 MPI_BOOT_DEVICE_PCI_ADDRESS PCIAddress;
1206 MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber;
1207 MPI_BOOT_DEVICE_FC_WWN FcWwn;
1208 MPI_BOOT_DEVICE_SAS_WWN SasWwn;
1209 MPI_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1210} MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE;
1211
1212typedef struct _CONFIG_PAGE_BIOS_2
1213{
1214 CONFIG_PAGE_HEADER Header; /* 00h */
1215 U32 Reserved1; /* 04h */
1216 U32 Reserved2; /* 08h */
1217 U32 Reserved3; /* 0Ch */
1218 U32 Reserved4; /* 10h */
1219 U32 Reserved5; /* 14h */
1220 U32 Reserved6; /* 18h */
1221 U8 BootDeviceForm; /* 1Ch */
1222 U8 Reserved7; /* 1Dh */
1223 U16 Reserved8; /* 1Eh */
1224 MPI_BIOSPAGE2_BOOT_DEVICE BootDevice; /* 20h */
1225} CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2,
1226 BIOSPage2_t, MPI_POINTER pBIOSPage2_t;
1227
1228#define MPI_BIOSPAGE2_PAGEVERSION (0x01)
1229
1230#define MPI_BIOSPAGE2_FORM_MASK (0x0F)
1231#define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER (0x00)
1232#define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER (0x01)
1233#define MPI_BIOSPAGE2_FORM_PCI_ADDRESS (0x02)
1234#define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER (0x03)
1235#define MPI_BIOSPAGE2_FORM_FC_WWN (0x04)
1236#define MPI_BIOSPAGE2_FORM_SAS_WWN (0x05)
1237#define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1238
1239
730/****************************************************************************
731* SCSI Port Config Pages
732****************************************************************************/
733
734typedef struct _CONFIG_PAGE_SCSI_PORT_0
735{
736 CONFIG_PAGE_HEADER Header; /* 00h */
737 U32 Capabilities; /* 04h */
738 U32 PhysicalInterface; /* 08h */
739} CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0,
740 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t;
741
1240/****************************************************************************
1241* SCSI Port Config Pages
1242****************************************************************************/
1243
1244typedef struct _CONFIG_PAGE_SCSI_PORT_0
1245{
1246 CONFIG_PAGE_HEADER Header; /* 00h */
1247 U32 Capabilities; /* 04h */
1248 U32 PhysicalInterface; /* 08h */
1249} CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0,
1250 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t;
1251
742#define MPI_SCSIPORTPAGE0_PAGEVERSION (0x01)
1252#define MPI_SCSIPORTPAGE0_PAGEVERSION (0x02)
743
744#define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001)
745#define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002)
746#define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004)
747#define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1253
1254#define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001)
1255#define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002)
1256#define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004)
1257#define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1258#define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00)
1259#define MPI_SCSIPORTPAGE0_SYNC_5 (0x32)
1260#define MPI_SCSIPORTPAGE0_SYNC_10 (0x19)
1261#define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C)
1262#define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B)
1263#define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A)
1264#define MPI_SCSIPORTPAGE0_SYNC_80 (0x09)
1265#define MPI_SCSIPORTPAGE0_SYNC_160 (0x08)
1266#define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF)
1267
1268#define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8)
1269#define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \
1270 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MASK_MIN_SYNC_PERIOD) \
1271 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \
1272 )
748#define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1273#define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1274#define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16)
1275#define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \
1276 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MASK_MAX_SYNC_OFFSET) \
1277 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \
1278 )
1279#define MPI_SCSIPORTPAGE0_CAP_IDP (0x08000000)
749#define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000)
750#define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000)
751
752#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003)
753#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01)
754#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02)
755#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03)
756#define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000)

--- 13 unchanged lines hidden (view full) ---

770} CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1,
771 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;
772
773#define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03)
774
775/* Configuration values */
776#define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF)
777#define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000)
1280#define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000)
1281#define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000)
1282
1283#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003)
1284#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01)
1285#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02)
1286#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03)
1287#define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000)

--- 13 unchanged lines hidden (view full) ---

1301} CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1,
1302 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;
1303
1304#define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03)
1305
1306/* Configuration values */
1307#define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF)
1308#define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000)
1309#define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16)
778
779/* TargetConfig values */
780#define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01)
781#define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02)
782
783
784typedef struct _MPI_DEVICE_INFO
785{

--- 20 unchanged lines hidden (view full) ---

806#define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
807#define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010)
808
809#define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060)
810#define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000)
811#define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020)
812#define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060)
813
1310
1311/* TargetConfig values */
1312#define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01)
1313#define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02)
1314
1315
1316typedef struct _MPI_DEVICE_INFO
1317{

--- 20 unchanged lines hidden (view full) ---

1338#define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
1339#define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010)
1340
1341#define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060)
1342#define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000)
1343#define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020)
1344#define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060)
1345
1346
814/* PortSettings values */
815#define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F)
816#define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030)
817#define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000)
818#define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010)
819#define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020)
820#define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030)
821#define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0)
1347/* PortSettings values */
1348#define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F)
1349#define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030)
1350#define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000)
1351#define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010)
1352#define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020)
1353#define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030)
1354#define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0)
1355#define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000)
1356#define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040)
1357#define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080)
822#define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00)
1358#define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00)
1359#define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8)
823#define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000)
824#define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000)
825#define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000)
826#define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000)
827
828#define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001)
829#define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002)
830#define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004)

--- 9 unchanged lines hidden (view full) ---

840typedef struct _CONFIG_PAGE_SCSI_DEVICE_0
841{
842 CONFIG_PAGE_HEADER Header; /* 00h */
843 U32 NegotiatedParameters; /* 04h */
844 U32 Information; /* 08h */
845} CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0,
846 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t;
847
1360#define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000)
1361#define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000)
1362#define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000)
1363#define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000)
1364
1365#define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001)
1366#define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002)
1367#define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004)

--- 9 unchanged lines hidden (view full) ---

1377typedef struct _CONFIG_PAGE_SCSI_DEVICE_0
1378{
1379 CONFIG_PAGE_HEADER Header; /* 00h */
1380 U32 NegotiatedParameters; /* 04h */
1381 U32 Information; /* 08h */
1382} CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0,
1383 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t;
1384
848#define MPI_SCSIDEVPAGE0_PAGEVERSION (0x03)
1385#define MPI_SCSIDEVPAGE0_PAGEVERSION (0x04)
849
850#define MPI_SCSIDEVPAGE0_NP_IU (0x00000001)
851#define MPI_SCSIDEVPAGE0_NP_DT (0x00000002)
852#define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004)
853#define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008)
854#define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010)
855#define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020)
856#define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040)
857#define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080)
858#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00)
1386
1387#define MPI_SCSIDEVPAGE0_NP_IU (0x00000001)
1388#define MPI_SCSIDEVPAGE0_NP_DT (0x00000002)
1389#define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004)
1390#define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008)
1391#define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010)
1392#define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020)
1393#define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040)
1394#define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080)
1395#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00)
1396#define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8)
859#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000)
1397#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000)
1398#define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16)
1399#define MPI_SCSIDEVPAGE0_NP_IDP (0x08000000)
860#define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000)
861#define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000)
862
863#define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001)
864#define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002)
865#define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004)
866#define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008)
867
868
869typedef struct _CONFIG_PAGE_SCSI_DEVICE_1
870{
871 CONFIG_PAGE_HEADER Header; /* 00h */
872 U32 RequestedParameters; /* 04h */
873 U32 Reserved; /* 08h */
874 U32 Configuration; /* 0Ch */
875} CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1,
876 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t;
877
1400#define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000)
1401#define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000)
1402
1403#define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001)
1404#define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002)
1405#define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004)
1406#define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008)
1407
1408
1409typedef struct _CONFIG_PAGE_SCSI_DEVICE_1
1410{
1411 CONFIG_PAGE_HEADER Header; /* 00h */
1412 U32 RequestedParameters; /* 04h */
1413 U32 Reserved; /* 08h */
1414 U32 Configuration; /* 0Ch */
1415} CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1,
1416 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t;
1417
878#define MPI_SCSIDEVPAGE1_PAGEVERSION (0x04)
1418#define MPI_SCSIDEVPAGE1_PAGEVERSION (0x05)
879
880#define MPI_SCSIDEVPAGE1_RP_IU (0x00000001)
881#define MPI_SCSIDEVPAGE1_RP_DT (0x00000002)
882#define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004)
883#define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008)
884#define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010)
885#define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020)
886#define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040)
887#define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080)
888#define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1419
1420#define MPI_SCSIDEVPAGE1_RP_IU (0x00000001)
1421#define MPI_SCSIDEVPAGE1_RP_DT (0x00000002)
1422#define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004)
1423#define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008)
1424#define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010)
1425#define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020)
1426#define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040)
1427#define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080)
1428#define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1429#define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8)
889#define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1430#define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1431#define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16)
1432#define MPI_SCSIDEVPAGE1_RP_IDP (0x08000000)
890#define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000)
891#define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000)
892
893#define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002)
894#define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004)
895#define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008)
896#define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010)
897

--- 129 unchanged lines hidden (view full) ---

1027#define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */
1028#define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */
1029#define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */
1030
1031#define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001)
1032#define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002)
1033#define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004)
1034
1433#define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000)
1434#define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000)
1435
1436#define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002)
1437#define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004)
1438#define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008)
1439#define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010)
1440

--- 129 unchanged lines hidden (view full) ---

1570#define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */
1571#define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */
1572#define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */
1573
1574#define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001)
1575#define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002)
1576#define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004)
1577
1578#define MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0 Unknown - transceiver incapable of reporting */
1035#define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */
1036#define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */
1037#define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */
1579#define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */
1580#define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */
1581#define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */
1582#define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT 8 4 GBit/sec */
1038
1583
1584#define MPI_FCPORTPAGE0_CURRENT_SPEED_UKNOWN MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN
1039#define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED
1040#define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED
1041#define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED
1585#define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED
1586#define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED
1587#define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED
1588#define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED
1589#define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED (0x00008000) /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */
1042
1043
1044typedef struct _CONFIG_PAGE_FC_PORT_1
1045{
1046 CONFIG_PAGE_HEADER Header; /* 00h */
1047 U32 Flags; /* 04h */
1048 U64 NoSEEPROMWWNN; /* 08h */
1049 U64 NoSEEPROMWWPN; /* 10h */

--- 12 unchanged lines hidden (view full) ---

1062
1063#define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000)
1064#define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000)
1065#define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000)
1066#define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000)
1067#define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000)
1068#define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000)
1069#define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000)
1590
1591
1592typedef struct _CONFIG_PAGE_FC_PORT_1
1593{
1594 CONFIG_PAGE_HEADER Header; /* 00h */
1595 U32 Flags; /* 04h */
1596 U64 NoSEEPROMWWNN; /* 08h */
1597 U64 NoSEEPROMWWPN; /* 10h */

--- 12 unchanged lines hidden (view full) ---

1610
1611#define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000)
1612#define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000)
1613#define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000)
1614#define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000)
1615#define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000)
1616#define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000)
1617#define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000)
1618#define MPI_FCPORTPAGE1_FLAGS_TARGET_LARGE_CDB_ENABLE (0x00000080)
1070#define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070)
1071#define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008)
1072#define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004)
1073#define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002)
1074#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001)
1075#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000)
1076
1077#define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000)

--- 393 unchanged lines hidden (view full) ---

1471{
1472 U8 Flags; /* 00h */
1473 U8 State; /* 01h */
1474 U16 Reserved; /* 02h */
1475} RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS,
1476 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t;
1477
1478/* RAID Volume Page 0 VolumeStatus defines */
1619#define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070)
1620#define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008)
1621#define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004)
1622#define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002)
1623#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001)
1624#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000)
1625
1626#define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000)

--- 393 unchanged lines hidden (view full) ---

2020{
2021 U8 Flags; /* 00h */
2022 U8 State; /* 01h */
2023 U16 Reserved; /* 02h */
2024} RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS,
2025 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t;
2026
2027/* RAID Volume Page 0 VolumeStatus defines */
1479
1480#define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01)
1481#define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02)
1482#define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04)
1483#define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08)
2028#define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01)
2029#define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02)
2030#define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04)
2031#define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08)
2032#define MPI_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x10)
1484
1485#define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00)
1486#define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01)
1487#define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02)
2033
2034#define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00)
2035#define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01)
2036#define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02)
2037#define MPI_RAIDVOL0_STATUS_STATE_MISSING (0x03)
1488
1489typedef struct _RAID_VOL0_SETTINGS
1490{
1491 U16 Settings; /* 00h */
1492 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */
1493 U8 Reserved; /* 02h */
1494} RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS,
1495 RaidVol0Settings, MPI_POINTER pRaidVol0Settings;
1496
1497/* RAID Volume Page 0 VolumeSettings defines */
2038
2039typedef struct _RAID_VOL0_SETTINGS
2040{
2041 U16 Settings; /* 00h */
2042 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */
2043 U8 Reserved; /* 02h */
2044} RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS,
2045 RaidVol0Settings, MPI_POINTER pRaidVol0Settings;
2046
2047/* RAID Volume Page 0 VolumeSettings defines */
1498
1499#define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001)
1500#define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002)
1501#define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004)
1502#define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008)
2048#define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001)
2049#define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002)
2050#define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004)
2051#define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008)
2052#define MPI_RAIDVOL0_SETTING_FAST_DATA_SCRUBBING_0102 (0x0020) /* obsolete */
1503#define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010)
1504#define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000)
1505
1506/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1507#define MPI_RAID_HOT_SPARE_POOL_0 (0x01)
1508#define MPI_RAID_HOT_SPARE_POOL_1 (0x02)
1509#define MPI_RAID_HOT_SPARE_POOL_2 (0x04)
1510#define MPI_RAID_HOT_SPARE_POOL_3 (0x08)

--- 27 unchanged lines hidden (view full) ---

1538 U8 NumPhysDisks; /* 24h */
1539 U8 DataScrubRate; /* 25h */
1540 U8 ResyncRate; /* 26h */
1541 U8 InactiveStatus; /* 27h */
1542 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */
1543} CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0,
1544 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t;
1545
2053#define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010)
2054#define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000)
2055
2056/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
2057#define MPI_RAID_HOT_SPARE_POOL_0 (0x01)
2058#define MPI_RAID_HOT_SPARE_POOL_1 (0x02)
2059#define MPI_RAID_HOT_SPARE_POOL_2 (0x04)
2060#define MPI_RAID_HOT_SPARE_POOL_3 (0x08)

--- 27 unchanged lines hidden (view full) ---

2088 U8 NumPhysDisks; /* 24h */
2089 U8 DataScrubRate; /* 25h */
2090 U8 ResyncRate; /* 26h */
2091 U8 InactiveStatus; /* 27h */
2092 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */
2093} CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0,
2094 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t;
2095
1546#define MPI_RAIDVOLPAGE0_PAGEVERSION (0x01)
2096#define MPI_RAIDVOLPAGE0_PAGEVERSION (0x05)
1547
2097
2098/* values for RAID Volume Page 0 InactiveStatus field */
2099#define MPI_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
2100#define MPI_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
2101#define MPI_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
2102#define MPI_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
2103#define MPI_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
2104#define MPI_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
2105#define MPI_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1548
2106
2107
2108typedef struct _CONFIG_PAGE_RAID_VOL_1
2109{
2110 CONFIG_PAGE_HEADER Header; /* 00h */
2111 U8 VolumeID; /* 01h */
2112 U8 VolumeBus; /* 02h */
2113 U8 VolumeIOC; /* 03h */
2114 U8 Reserved0; /* 04h */
2115 U8 GUID[24]; /* 05h */
2116 U8 Name[32]; /* 20h */
2117 U64 WWID; /* 40h */
2118 U32 Reserved1; /* 48h */
2119 U32 Reserved2; /* 4Ch */
2120} CONFIG_PAGE_RAID_VOL_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_1,
2121 RaidVolumePage1_t, MPI_POINTER pRaidVolumePage1_t;
2122
2123#define MPI_RAIDVOLPAGE1_PAGEVERSION (0x01)
2124
2125
1549/****************************************************************************
1550* RAID Physical Disk Config Pages
1551****************************************************************************/
1552
1553typedef struct _RAID_PHYS_DISK0_ERROR_DATA
1554{
1555 U8 ErrorCdbByte; /* 00h */
1556 U8 ErrorSenseKey; /* 01h */

--- 32 unchanged lines hidden (view full) ---

1589 U16 Reserved; /* 02h */
1590} RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS,
1591 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t;
1592
1593/* RAID Volume 2 IM Physical Disk DiskStatus flags */
1594
1595#define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01)
1596#define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02)
2126/****************************************************************************
2127* RAID Physical Disk Config Pages
2128****************************************************************************/
2129
2130typedef struct _RAID_PHYS_DISK0_ERROR_DATA
2131{
2132 U8 ErrorCdbByte; /* 00h */
2133 U8 ErrorSenseKey; /* 01h */

--- 32 unchanged lines hidden (view full) ---

2166 U16 Reserved; /* 02h */
2167} RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS,
2168 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t;
2169
2170/* RAID Volume 2 IM Physical Disk DiskStatus flags */
2171
2172#define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01)
2173#define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02)
2174#define MPI_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x04)
2175#define MPI_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00)
2176#define MPI_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x08)
1597
1598#define MPI_PHYSDISK0_STATUS_ONLINE (0x00)
1599#define MPI_PHYSDISK0_STATUS_MISSING (0x01)
1600#define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02)
1601#define MPI_PHYSDISK0_STATUS_FAILED (0x03)
1602#define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04)
1603#define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05)
1604#define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06)
1605#define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF)
1606
1607typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0
1608{
1609 CONFIG_PAGE_HEADER Header; /* 00h */
1610 U8 PhysDiskID; /* 04h */
1611 U8 PhysDiskBus; /* 05h */
1612 U8 PhysDiskIOC; /* 06h */
1613 U8 PhysDiskNum; /* 07h */
1614 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */
1615 U32 Reserved1; /* 0Ch */
2177
2178#define MPI_PHYSDISK0_STATUS_ONLINE (0x00)
2179#define MPI_PHYSDISK0_STATUS_MISSING (0x01)
2180#define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02)
2181#define MPI_PHYSDISK0_STATUS_FAILED (0x03)
2182#define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04)
2183#define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05)
2184#define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06)
2185#define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF)
2186
2187typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0
2188{
2189 CONFIG_PAGE_HEADER Header; /* 00h */
2190 U8 PhysDiskID; /* 04h */
2191 U8 PhysDiskBus; /* 05h */
2192 U8 PhysDiskIOC; /* 06h */
2193 U8 PhysDiskNum; /* 07h */
2194 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */
2195 U32 Reserved1; /* 0Ch */
1616 U32 Reserved2; /* 10h */
1617 U32 Reserved3; /* 14h */
2196 U8 ExtDiskIdentifier[8]; /* 10h */
1618 U8 DiskIdentifier[16]; /* 18h */
1619 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */
1620 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */
1621 U32 MaxLBA; /* 68h */
1622 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */
1623} CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0,
1624 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t;
1625
2197 U8 DiskIdentifier[16]; /* 18h */
2198 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */
2199 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */
2200 U32 MaxLBA; /* 68h */
2201 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */
2202} CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0,
2203 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t;
2204
1626#define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x00)
2205#define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x02)
1627
1628
2206
2207
2208typedef struct _RAID_PHYS_DISK1_PATH
2209{
2210 U8 PhysDiskID; /* 00h */
2211 U8 PhysDiskBus; /* 01h */
2212 U16 Reserved1; /* 02h */
2213 U64 WWID; /* 04h */
2214 U64 OwnerWWID; /* 0Ch */
2215 U8 OwnerIdentifier; /* 14h */
2216 U8 Reserved2; /* 15h */
2217 U16 Flags; /* 16h */
2218} RAID_PHYS_DISK1_PATH, MPI_POINTER PTR_RAID_PHYS_DISK1_PATH,
2219 RaidPhysDisk1Path_t, MPI_POINTER pRaidPhysDisk1Path_t;
2220
2221/* RAID Physical Disk Page 1 Flags field defines */
2222#define MPI_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
2223#define MPI_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
2224
2225typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1
2226{
2227 CONFIG_PAGE_HEADER Header; /* 00h */
2228 U8 NumPhysDiskPaths; /* 04h */
2229 U8 PhysDiskNum; /* 05h */
2230 U16 Reserved2; /* 06h */
2231 U32 Reserved1; /* 08h */
2232 RAID_PHYS_DISK1_PATH Path[1]; /* 0Ch */
2233} CONFIG_PAGE_RAID_PHYS_DISK_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_1,
2234 RaidPhysDiskPage1_t, MPI_POINTER pRaidPhysDiskPage1_t;
2235
2236#define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION (0x00)
2237
2238
1629/****************************************************************************
1630* LAN Config Pages
1631****************************************************************************/
1632
1633typedef struct _CONFIG_PAGE_LAN_0
1634{
1635 ConfigPageHeader_t Header; /* 00h */
1636 U16 TxRxModes; /* 04h */

--- 27 unchanged lines hidden (view full) ---

1664} CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1,
1665 LANPage1_t, MPI_POINTER pLANPage1_t;
1666
1667#define MPI_LAN_PAGE1_PAGEVERSION (0x03)
1668
1669#define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00)
1670#define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01)
1671
2239/****************************************************************************
2240* LAN Config Pages
2241****************************************************************************/
2242
2243typedef struct _CONFIG_PAGE_LAN_0
2244{
2245 ConfigPageHeader_t Header; /* 00h */
2246 U16 TxRxModes; /* 04h */

--- 27 unchanged lines hidden (view full) ---

2274} CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1,
2275 LANPage1_t, MPI_POINTER pLANPage1_t;
2276
2277#define MPI_LAN_PAGE1_PAGEVERSION (0x03)
2278
2279#define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00)
2280#define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01)
2281
2282
2283/****************************************************************************
2284* Inband Config Pages
2285****************************************************************************/
2286
2287typedef struct _CONFIG_PAGE_INBAND_0
2288{
2289 CONFIG_PAGE_HEADER Header; /* 00h */
2290 MPI_VERSION_FORMAT InbandVersion; /* 04h */
2291 U16 MaximumBuffers; /* 08h */
2292 U16 Reserved1; /* 0Ah */
2293} CONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0,
2294 InbandPage0_t, MPI_POINTER pInbandPage0_t;
2295
2296#define MPI_INBAND_PAGEVERSION (0x00)
2297
2298
2299
2300/****************************************************************************
2301* SAS IO Unit Config Pages
2302****************************************************************************/
2303
2304typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA
2305{
2306 U8 Port; /* 00h */
2307 U8 PortFlags; /* 01h */
2308 U8 PhyFlags; /* 02h */
2309 U8 NegotiatedLinkRate; /* 03h */
2310 U32 ControllerPhyDeviceInfo;/* 04h */
2311 U16 AttachedDeviceHandle; /* 08h */
2312 U16 ControllerDevHandle; /* 0Ah */
2313 U32 DiscoveryStatus; /* 0Ch */
2314} MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA,
2315 SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData;
2316
2317/*
2318 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2319 * one and check Header.PageLength at runtime.
2320 */
2321#ifndef MPI_SAS_IOUNIT0_PHY_MAX
2322#define MPI_SAS_IOUNIT0_PHY_MAX (1)
1672#endif
1673
2323#endif
2324
2325typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0
2326{
2327 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2328 U32 Reserved1; /* 08h */
2329 U8 NumPhys; /* 0Ch */
2330 U8 Reserved2; /* 0Dh */
2331 U16 Reserved3; /* 0Eh */
2332 MPI_SAS_IO_UNIT0_PHY_DATA PhyData[MPI_SAS_IOUNIT0_PHY_MAX]; /* 10h */
2333} CONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0,
2334 SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t;
2335
2336#define MPI_SASIOUNITPAGE0_PAGEVERSION (0x03)
2337
2338/* values for SAS IO Unit Page 0 PortFlags */
2339#define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS (0x08)
2340#define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
2341#define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
2342#define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2343
2344/* values for SAS IO Unit Page 0 PhyFlags */
2345#define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED (0x04)
2346#define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT (0x02)
2347#define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT (0x01)
2348
2349/* values for SAS IO Unit Page 0 NegotiatedLinkRate */
2350#define MPI_SAS_IOUNIT0_RATE_UNKNOWN (0x00)
2351#define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED (0x01)
2352#define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION (0x02)
2353#define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE (0x03)
2354#define MPI_SAS_IOUNIT0_RATE_1_5 (0x08)
2355#define MPI_SAS_IOUNIT0_RATE_3_0 (0x09)
2356
2357/* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2358
2359/* values for SAS IO Unit Page 0 DiscoveryStatus */
2360#define MPI_SAS_IOUNIT0_DS_LOOP_DETECTED (0x00000001)
2361#define MPI_SAS_IOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2362#define MPI_SAS_IOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
2363#define MPI_SAS_IOUNIT0_DS_EXPANDER_ERR (0x00000008)
2364#define MPI_SAS_IOUNIT0_DS_SMP_TIMEOUT (0x00000010)
2365#define MPI_SAS_IOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2366#define MPI_SAS_IOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
2367#define MPI_SAS_IOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
2368#define MPI_SAS_IOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
2369#define MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
2370#define MPI_SAS_IOUNIT0_DS_TABLE_LINK (0x00000400)
2371#define MPI_SAS_IOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
2372#define MPI_SAS_IOUNIT0_DS_MAX_SATA_TARGETS (0x00001000)
2373
2374
2375typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA
2376{
2377 U8 Port; /* 00h */
2378 U8 PortFlags; /* 01h */
2379 U8 PhyFlags; /* 02h */
2380 U8 MaxMinLinkRate; /* 03h */
2381 U32 ControllerPhyDeviceInfo;/* 04h */
2382 U32 Reserved1; /* 08h */
2383} MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA,
2384 SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData;
2385
2386/*
2387 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2388 * one and check Header.PageLength at runtime.
2389 */
2390#ifndef MPI_SAS_IOUNIT1_PHY_MAX
2391#define MPI_SAS_IOUNIT1_PHY_MAX (1)
2392#endif
2393
2394typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1
2395{
2396 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2397 U16 ControlFlags; /* 08h */
2398 U16 MaxNumSATATargets; /* 0Ah */
2399 U32 Reserved1; /* 0Ch */
2400 U8 NumPhys; /* 10h */
2401 U8 SATAMaxQDepth; /* 11h */
2402 U16 Reserved2; /* 12h */
2403 MPI_SAS_IO_UNIT1_PHY_DATA PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; /* 14h */
2404} CONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1,
2405 SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t;
2406
2407#define MPI_SASIOUNITPAGE1_PAGEVERSION (0x04)
2408
2409/* values for SAS IO Unit Page 1 ControlFlags */
2410#define MPI_SAS_IOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
2411#define MPI_SAS_IOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
2412#define MPI_SAS_IOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
2413#define MPI_SAS_IOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
2414#define MPI_SAS_IOUNIT1_CONTROL_DISABLE_SAS_HASH (0x0800)
2415
2416#define MPI_SAS_IOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
2417#define MPI_SAS_IOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
2418#define MPI_SAS_IOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x00)
2419#define MPI_SAS_IOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x01)
2420#define MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x02)
2421
2422#define MPI_SAS_IOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
2423#define MPI_SAS_IOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
2424#define MPI_SAS_IOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
2425#define MPI_SAS_IOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
2426#define MPI_SAS_IOUNIT1_CONTROL_PHY_ENABLE_ORDER_HIGH (0x0008)
2427#define MPI_SAS_IOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
2428#define MPI_SAS_IOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
2429#define MPI_SAS_IOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
2430
2431/* values for SAS IO Unit Page 1 PortFlags */
2432#define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
2433#define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
2434#define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2435
2436/* values for SAS IO Unit Page 0 PhyFlags */
2437#define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE (0x04)
2438#define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT (0x02)
2439#define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT (0x01)
2440
2441/* values for SAS IO Unit Page 0 MaxMinLinkRate */
2442#define MPI_SAS_IOUNIT1_MAX_RATE_MASK (0xF0)
2443#define MPI_SAS_IOUNIT1_MAX_RATE_1_5 (0x80)
2444#define MPI_SAS_IOUNIT1_MAX_RATE_3_0 (0x90)
2445#define MPI_SAS_IOUNIT1_MIN_RATE_MASK (0x0F)
2446#define MPI_SAS_IOUNIT1_MIN_RATE_1_5 (0x08)
2447#define MPI_SAS_IOUNIT1_MIN_RATE_3_0 (0x09)
2448
2449/* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2450
2451
2452typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2
2453{
2454 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2455 U8 NumDevsPerEnclosure; /* 08h */
2456 U8 Reserved1; /* 09h */
2457 U16 Reserved2; /* 0Ah */
2458 U16 MaxPersistentIDs; /* 0Ch */
2459 U16 NumPersistentIDsUsed; /* 0Eh */
2460 U8 Status; /* 10h */
2461 U8 Flags; /* 11h */
2462 U16 MaxNumPhysicalMappedIDs;/* 12h */
2463} CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2,
2464 SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t;
2465
2466#define MPI_SASIOUNITPAGE2_PAGEVERSION (0x05)
2467
2468/* values for SAS IO Unit Page 2 Status field */
2469#define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02)
2470#define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS (0x01)
2471
2472/* values for SAS IO Unit Page 2 Flags field */
2473#define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS (0x01)
2474/* Physical Mapping Modes */
2475#define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE (0x0E)
2476#define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE (1)
2477#define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP (0x00)
2478#define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP (0x01)
2479#define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP (0x02)
2480#define MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP (0x07)
2481
2482#define MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT (0x10)
2483#define MPI_SAS_IOUNIT2_FLAGS_DA_STARTING_SLOT (0x20)
2484
2485
2486typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3
2487{
2488 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2489 U32 Reserved1; /* 08h */
2490 U32 MaxInvalidDwordCount; /* 0Ch */
2491 U32 InvalidDwordCountTime; /* 10h */
2492 U32 MaxRunningDisparityErrorCount; /* 14h */
2493 U32 RunningDisparityErrorTime; /* 18h */
2494 U32 MaxLossDwordSynchCount; /* 1Ch */
2495 U32 LossDwordSynchCountTime; /* 20h */
2496 U32 MaxPhyResetProblemCount; /* 24h */
2497 U32 PhyResetProblemTime; /* 28h */
2498} CONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3,
2499 SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t;
2500
2501#define MPI_SASIOUNITPAGE3_PAGEVERSION (0x00)
2502
2503
2504/****************************************************************************
2505* SAS Expander Config Pages
2506****************************************************************************/
2507
2508typedef struct _CONFIG_PAGE_SAS_EXPANDER_0
2509{
2510 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2511 U8 PhysicalPort; /* 08h */
2512 U8 Reserved1; /* 09h */
2513 U16 EnclosureHandle; /* 0Ah */
2514 U64 SASAddress; /* 0Ch */
2515 U32 DiscoveryStatus; /* 14h */
2516 U16 DevHandle; /* 18h */
2517 U16 ParentDevHandle; /* 1Ah */
2518 U16 ExpanderChangeCount; /* 1Ch */
2519 U16 ExpanderRouteIndexes; /* 1Eh */
2520 U8 NumPhys; /* 20h */
2521 U8 SASLevel; /* 21h */
2522 U8 Flags; /* 22h */
2523 U8 Reserved3; /* 23h */
2524} CONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0,
2525 SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t;
2526
2527#define MPI_SASEXPANDER0_PAGEVERSION (0x03)
2528
2529/* values for SAS Expander Page 0 DiscoveryStatus field */
2530#define MPI_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2531#define MPI_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2532#define MPI_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2533#define MPI_SAS_EXPANDER0_DS_EXPANDER_ERR (0x00000008)
2534#define MPI_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2535#define MPI_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2536#define MPI_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2537#define MPI_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2538#define MPI_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2539#define MPI_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2540#define MPI_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2541#define MPI_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2542
2543/* values for SAS Expander Page 0 Flags field */
2544#define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x02)
2545#define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x01)
2546
2547
2548typedef struct _CONFIG_PAGE_SAS_EXPANDER_1
2549{
2550 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2551 U8 PhysicalPort; /* 08h */
2552 U8 Reserved1; /* 09h */
2553 U16 Reserved2; /* 0Ah */
2554 U8 NumPhys; /* 0Ch */
2555 U8 Phy; /* 0Dh */
2556 U16 NumTableEntriesProgrammed; /* 0Eh */
2557 U8 ProgrammedLinkRate; /* 10h */
2558 U8 HwLinkRate; /* 11h */
2559 U16 AttachedDevHandle; /* 12h */
2560 U32 PhyInfo; /* 14h */
2561 U32 AttachedDeviceInfo; /* 18h */
2562 U16 OwnerDevHandle; /* 1Ch */
2563 U8 ChangeCount; /* 1Eh */
2564 U8 NegotiatedLinkRate; /* 1Fh */
2565 U8 PhyIdentifier; /* 20h */
2566 U8 AttachedPhyIdentifier; /* 21h */
2567 U8 Reserved3; /* 22h */
2568 U8 DiscoveryInfo; /* 23h */
2569 U32 Reserved4; /* 24h */
2570} CONFIG_PAGE_SAS_EXPANDER_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_1,
2571 SasExpanderPage1_t, MPI_POINTER pSasExpanderPage1_t;
2572
2573#define MPI_SASEXPANDER1_PAGEVERSION (0x01)
2574
2575/* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */
2576
2577/* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */
2578
2579/* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */
2580
2581/* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */
2582
2583/* values for SAS Expander Page 1 DiscoveryInfo field */
2584#define MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY DISABLED (0x04)
2585#define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2586#define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2587
2588/* values for SAS Expander Page 1 NegotiatedLinkRate field */
2589#define MPI_SAS_EXPANDER1_NEG_RATE_UNKNOWN (0x00)
2590#define MPI_SAS_EXPANDER1_NEG_RATE_PHY_DISABLED (0x01)
2591#define MPI_SAS_EXPANDER1_NEG_RATE_FAILED_NEGOTIATION (0x02)
2592#define MPI_SAS_EXPANDER1_NEG_RATE_SATA_OOB_COMPLETE (0x03)
2593#define MPI_SAS_EXPANDER1_NEG_RATE_1_5 (0x08)
2594#define MPI_SAS_EXPANDER1_NEG_RATE_3_0 (0x09)
2595
2596
2597/****************************************************************************
2598* SAS Device Config Pages
2599****************************************************************************/
2600
2601typedef struct _CONFIG_PAGE_SAS_DEVICE_0
2602{
2603 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2604 U16 Slot; /* 08h */
2605 U16 EnclosureHandle; /* 0Ah */
2606 U64 SASAddress; /* 0Ch */
2607 U16 ParentDevHandle; /* 14h */
2608 U8 PhyNum; /* 16h */
2609 U8 AccessStatus; /* 17h */
2610 U16 DevHandle; /* 18h */
2611 U8 TargetID; /* 1Ah */
2612 U8 Bus; /* 1Bh */
2613 U32 DeviceInfo; /* 1Ch */
2614 U16 Flags; /* 20h */
2615 U8 PhysicalPort; /* 22h */
2616 U8 Reserved2; /* 23h */
2617} CONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0,
2618 SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t;
2619
2620#define MPI_SASDEVICE0_PAGEVERSION (0x04)
2621
2622/* values for SAS Device Page 0 AccessStatus field */
2623#define MPI_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2624#define MPI_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2625#define MPI_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2626
2627/* values for SAS Device Page 0 Flags field */
2628#define MPI_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2629#define MPI_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2630#define MPI_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2631#define MPI_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2632#define MPI_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2633#define MPI_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2634#define MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2635#define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT (0x0004)
2636#define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED (0x0002)
2637#define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2638
2639/* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */
2640
2641
2642typedef struct _CONFIG_PAGE_SAS_DEVICE_1
2643{
2644 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2645 U32 Reserved1; /* 08h */
2646 U64 SASAddress; /* 0Ch */
2647 U32 Reserved2; /* 14h */
2648 U16 DevHandle; /* 18h */
2649 U8 TargetID; /* 1Ah */
2650 U8 Bus; /* 1Bh */
2651 U8 InitialRegDeviceFIS[20];/* 1Ch */
2652} CONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1,
2653 SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t;
2654
2655#define MPI_SASDEVICE1_PAGEVERSION (0x00)
2656
2657
2658typedef struct _CONFIG_PAGE_SAS_DEVICE_2
2659{
2660 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2661 U64 PhysicalIdentifier; /* 08h */
2662 U32 EnclosureMapping; /* 10h */
2663} CONFIG_PAGE_SAS_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_2,
2664 SasDevicePage2_t, MPI_POINTER pSasDevicePage2_t;
2665
2666#define MPI_SASDEVICE2_PAGEVERSION (0x01)
2667
2668/* defines for SAS Device Page 2 EnclosureMapping field */
2669#define MPI_SASDEVICE2_ENC_MAP_MASK_MISSING_COUNT (0x0000000F)
2670#define MPI_SASDEVICE2_ENC_MAP_SHIFT_MISSING_COUNT (0)
2671#define MPI_SASDEVICE2_ENC_MAP_MASK_NUM_SLOTS (0x000007F0)
2672#define MPI_SASDEVICE2_ENC_MAP_SHIFT_NUM_SLOTS (4)
2673#define MPI_SASDEVICE2_ENC_MAP_MASK_START_INDEX (0x001FF800)
2674#define MPI_SASDEVICE2_ENC_MAP_SHIFT_START_INDEX (11)
2675
2676
2677/****************************************************************************
2678* SAS PHY Config Pages
2679****************************************************************************/
2680
2681typedef struct _CONFIG_PAGE_SAS_PHY_0
2682{
2683 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2684 U16 OwnerDevHandle; /* 08h */
2685 U16 Reserved1; /* 0Ah */
2686 U64 SASAddress; /* 0Ch */
2687 U16 AttachedDevHandle; /* 14h */
2688 U8 AttachedPhyIdentifier; /* 16h */
2689 U8 Reserved2; /* 17h */
2690 U32 AttachedDeviceInfo; /* 18h */
2691 U8 ProgrammedLinkRate; /* 20h */
2692 U8 HwLinkRate; /* 21h */
2693 U8 ChangeCount; /* 22h */
2694 U8 Flags; /* 23h */
2695 U32 PhyInfo; /* 24h */
2696} CONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0,
2697 SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t;
2698
2699#define MPI_SASPHY0_PAGEVERSION (0x01)
2700
2701/* values for SAS PHY Page 0 ProgrammedLinkRate field */
2702#define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK (0xF0)
2703#define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
2704#define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 (0x80)
2705#define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 (0x90)
2706#define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK (0x0F)
2707#define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
2708#define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 (0x08)
2709#define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 (0x09)
2710
2711/* values for SAS PHY Page 0 HwLinkRate field */
2712#define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK (0xF0)
2713#define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 (0x80)
2714#define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 (0x90)
2715#define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK (0x0F)
2716#define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 (0x08)
2717#define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 (0x09)
2718
2719/* values for SAS PHY Page 0 Flags field */
2720#define MPI_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2721
2722/* values for SAS PHY Page 0 PhyInfo field */
2723#define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
2724#define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000)
2725#define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000)
2726
2727#define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
2728#define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
2729
2730#define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
2731#define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING (0x00000000)
2732#define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
2733#define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING (0x00000020)
2734
2735#define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE (0x0000000F)
2736#define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE (0x00000000)
2737#define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED (0x00000001)
2738#define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED (0x00000002)
2739#define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE (0x00000003)
2740#define MPI_SAS_PHY0_PHYINFO_RATE_1_5 (0x00000008)
2741#define MPI_SAS_PHY0_PHYINFO_RATE_3_0 (0x00000009)
2742
2743
2744typedef struct _CONFIG_PAGE_SAS_PHY_1
2745{
2746 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2747 U32 Reserved1; /* 08h */
2748 U32 InvalidDwordCount; /* 0Ch */
2749 U32 RunningDisparityErrorCount; /* 10h */
2750 U32 LossDwordSynchCount; /* 14h */
2751 U32 PhyResetProblemCount; /* 18h */
2752} CONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1,
2753 SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t;
2754
2755#define MPI_SASPHY1_PAGEVERSION (0x00)
2756
2757
2758/****************************************************************************
2759* SAS Enclosure Config Pages
2760****************************************************************************/
2761
2762typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_0
2763{
2764 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2765 U32 Reserved1; /* 08h */
2766 U64 EnclosureLogicalID; /* 0Ch */
2767 U16 Flags; /* 14h */
2768 U16 EnclosureHandle; /* 16h */
2769 U16 NumSlots; /* 18h */
2770 U16 StartSlot; /* 1Ah */
2771 U8 StartTargetID; /* 1Ch */
2772 U8 StartBus; /* 1Dh */
2773 U8 SEPTargetID; /* 1Eh */
2774 U8 SEPBus; /* 1Fh */
2775 U32 Reserved2; /* 20h */
2776 U32 Reserved3; /* 24h */
2777} CONFIG_PAGE_SAS_ENCLOSURE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_ENCLOSURE_0,
2778 SasEnclosurePage0_t, MPI_POINTER pSasEnclosurePage0_t;
2779
2780#define MPI_SASENCLOSURE0_PAGEVERSION (0x01)
2781
2782/* values for SAS Enclosure Page 0 Flags field */
2783#define MPI_SAS_ENCLS0_FLAGS_SEP_BUS_ID_VALID (0x0020)
2784#define MPI_SAS_ENCLS0_FLAGS_START_BUS_ID_VALID (0x0010)
2785
2786#define MPI_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2787#define MPI_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2788#define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2789#define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2790#define MPI_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2791#define MPI_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2792#define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2793
2794
2795/****************************************************************************
2796* Log Config Pages
2797****************************************************************************/
2798/*
2799 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2800 * one and check NumLogEntries at runtime.
2801 */
2802#ifndef MPI_LOG_0_NUM_LOG_ENTRIES
2803#define MPI_LOG_0_NUM_LOG_ENTRIES (1)
2804#endif
2805
2806#define MPI_LOG_0_LOG_DATA_LENGTH (20)
2807
2808typedef struct _MPI_LOG_0_ENTRY
2809{
2810 U64 WWID; /* 00h */
2811 U32 TimeStamp; /* 08h */
2812 U32 Reserved1; /* 0Ch */
2813 U16 LogSequence; /* 10h */
2814 U16 LogEntryQualifier; /* 12h */
2815 U8 LogData[MPI_LOG_0_LOG_DATA_LENGTH]; /* 14h */
2816} MPI_LOG_0_ENTRY, MPI_POINTER PTR_MPI_LOG_0_ENTRY,
2817 MpiLog0Entry_t, MPI_POINTER pMpiLog0Entry_t;
2818
2819/* values for Log Page 0 LogEntry LogEntryQualifier field */
2820#define MPI_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2821#define MPI_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2822
2823typedef struct _CONFIG_PAGE_LOG_0
2824{
2825 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2826 U32 Reserved1; /* 08h */
2827 U32 Reserved2; /* 0Ch */
2828 U16 NumLogEntries; /* 10h */
2829 U16 Reserved3; /* 12h */
2830 MPI_LOG_0_ENTRY LogEntry[MPI_LOG_0_NUM_LOG_ENTRIES]; /* 14h */
2831} CONFIG_PAGE_LOG_0, MPI_POINTER PTR_CONFIG_PAGE_LOG_0,
2832 LogPage0_t, MPI_POINTER pLogPage0_t;
2833
2834#define MPI_LOG_0_PAGEVERSION (0x00)
2835
2836
2837#endif
2838