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mpi_cnfg.h (102599) mpi_cnfg.h (115778)
1/* $FreeBSD: head/sys/dev/mpt/mpilib/mpi_cnfg.h 102599 2002-08-30 03:36:50Z mjacob $ */
1/* $FreeBSD: head/sys/dev/mpt/mpilib/mpi_cnfg.h 115778 2003-06-03 17:47:48Z mjacob $ */
2/*
3 * Copyright (c) 2000, 2001 by LSI Logic Corporation
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice immediately at the beginning of the file, without modification,

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23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 *
27 * Name: MPI_CNFG.H
28 * Title: MPI Config message, structures, and Pages
29 * Creation Date: July 27, 2000
30 *
2/*
3 * Copyright (c) 2000, 2001 by LSI Logic Corporation
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice immediately at the beginning of the file, without modification,

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23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 *
27 * Name: MPI_CNFG.H
28 * Title: MPI Config message, structures, and Pages
29 * Creation Date: July 27, 2000
30 *
31 * MPI Version: 01.02.05
31 * MPI_CNFG.H Version: 01.02.11
32 *
33 * Version History
34 * ---------------
35 *
36 * Date Version Description
37 * -------- -------- ------------------------------------------------------
38 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000.
39 * 06-06-00 01.00.01 Update version number for 1.0 release.

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125 * RAID PhysDisk Page 0.
126 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK.
127 * Modified some of the new defines to make them 32
128 * character unique.
129 * Modified how variable length pages (arrays) are defined.
130 * Added generic defines for hot spare pools and RAID
131 * volume types.
132 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR.
32 *
33 * Version History
34 * ---------------
35 *
36 * Date Version Description
37 * -------- -------- ------------------------------------------------------
38 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000.
39 * 06-06-00 01.00.01 Update version number for 1.0 release.

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125 * RAID PhysDisk Page 0.
126 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK.
127 * Modified some of the new defines to make them 32
128 * character unique.
129 * Modified how variable length pages (arrays) are defined.
130 * Added generic defines for hot spare pools and RAID
131 * volume types.
132 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR.
133 * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with
134 * related define, and bumped the page version define.
135 * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a
136 * reserved byte and added a define.
137 * Added define for
138 * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE.
139 * Added new config page: CONFIG_PAGE_IOC_5.
140 * Added MaxAliases, MaxHardAliases, and NumCurrentAliases
141 * fields to CONFIG_PAGE_FC_PORT_0.
142 * Added AltConnector and NumRequestedAliases fields to
143 * CONFIG_PAGE_FC_PORT_1.
144 * Added new config page: CONFIG_PAGE_FC_PORT_10.
145 * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines.
146 * Added additional MPI_SCSIDEVPAGE0_NP_ defines.
147 * Added more MPI_SCSIDEVPAGE1_RP_ defines.
148 * Added define for
149 * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE.
150 * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3.
151 * Modified MPI_FCPORTPAGE5_FLAGS_ defines.
152 * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define.
153 * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0.
154 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
155 * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0.
156 * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for
157 * CONFIG_PAGE_FC_PORT_1.
158 * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable
159 * an alias.
160 * Added more device id defines.
133 * --------------------------------------------------------------------------
134 */
135
136#ifndef MPI_CNFG_H
137#define MPI_CNFG_H
138
139
140/*****************************************************************************
141*
142* C o n f i g M e s s a g e a n d S t r u c t u r e s
143*
144*****************************************************************************/
145
146typedef struct _CONFIG_PAGE_HEADER
147{
148 U8 PageVersion; /* 00h */
149 U8 PageLength; /* 01h */
150 U8 PageNumber; /* 02h */
151 U8 PageType; /* 03h */
161 * --------------------------------------------------------------------------
162 */
163
164#ifndef MPI_CNFG_H
165#define MPI_CNFG_H
166
167
168/*****************************************************************************
169*
170* C o n f i g M e s s a g e a n d S t r u c t u r e s
171*
172*****************************************************************************/
173
174typedef struct _CONFIG_PAGE_HEADER
175{
176 U8 PageVersion; /* 00h */
177 U8 PageLength; /* 01h */
178 U8 PageNumber; /* 02h */
179 U8 PageType; /* 03h */
152} fCONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER,
180} CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER,
153 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t;
154
155typedef union _CONFIG_PAGE_HEADER_UNION
156{
157 ConfigPageHeader_t Struct;
158 U8 Bytes[4];
159 U16 Word16[2];
160 U32 Word32;
161} ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion,
181 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t;
182
183typedef union _CONFIG_PAGE_HEADER_UNION
184{
185 ConfigPageHeader_t Struct;
186 U8 Bytes[4];
187 U16 Word16[2];
188 U32 Word32;
189} ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion,
162 fCONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION;
190 CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION;
163
164
165/****************************************************************************
166* PageType field values
167****************************************************************************/
168#define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00)
169#define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10)
170#define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20)

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231 U8 Action; /* 00h */
232 U8 Reserved; /* 01h */
233 U8 ChainOffset; /* 02h */
234 U8 Function; /* 03h */
235 U8 Reserved1[3]; /* 04h */
236 U8 MsgFlags; /* 07h */
237 U32 MsgContext; /* 08h */
238 U8 Reserved2[8]; /* 0Ch */
191
192
193/****************************************************************************
194* PageType field values
195****************************************************************************/
196#define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00)
197#define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10)
198#define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20)

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259 U8 Action; /* 00h */
260 U8 Reserved; /* 01h */
261 U8 ChainOffset; /* 02h */
262 U8 Function; /* 03h */
263 U8 Reserved1[3]; /* 04h */
264 U8 MsgFlags; /* 07h */
265 U32 MsgContext; /* 08h */
266 U8 Reserved2[8]; /* 0Ch */
239 fCONFIG_PAGE_HEADER Header; /* 14h */
267 CONFIG_PAGE_HEADER Header; /* 14h */
240 U32 PageAddress; /* 18h */
241 SGE_IO_UNION PageBufferSGE; /* 1Ch */
242} MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG,
243 Config_t, MPI_POINTER pConfig_t;
244
245
246/****************************************************************************
247* Action field values

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263 U8 MsgLength; /* 02h */
264 U8 Function; /* 03h */
265 U8 Reserved1[3]; /* 04h */
266 U8 MsgFlags; /* 07h */
267 U32 MsgContext; /* 08h */
268 U8 Reserved2[2]; /* 0Ch */
269 U16 IOCStatus; /* 0Eh */
270 U32 IOCLogInfo; /* 10h */
268 U32 PageAddress; /* 18h */
269 SGE_IO_UNION PageBufferSGE; /* 1Ch */
270} MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG,
271 Config_t, MPI_POINTER pConfig_t;
272
273
274/****************************************************************************
275* Action field values

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291 U8 MsgLength; /* 02h */
292 U8 Function; /* 03h */
293 U8 Reserved1[3]; /* 04h */
294 U8 MsgFlags; /* 07h */
295 U32 MsgContext; /* 08h */
296 U8 Reserved2[2]; /* 0Ch */
297 U16 IOCStatus; /* 0Eh */
298 U32 IOCLogInfo; /* 10h */
271 fCONFIG_PAGE_HEADER Header; /* 14h */
299 CONFIG_PAGE_HEADER Header; /* 14h */
272} MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY,
273 ConfigReply_t, MPI_POINTER pConfigReply_t;
274
275
276
277/*****************************************************************************
278*
279* C o n f i g u r a t i o n P a g e s
280*
281*****************************************************************************/
282
283/****************************************************************************
284* Manufacturing Config pages
285****************************************************************************/
300} MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY,
301 ConfigReply_t, MPI_POINTER pConfigReply_t;
302
303
304
305/*****************************************************************************
306*
307* C o n f i g u r a t i o n P a g e s
308*
309*****************************************************************************/
310
311/****************************************************************************
312* Manufacturing Config pages
313****************************************************************************/
314#define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000)
315#define MPI_MANUFACTPAGE_VENDORID_TREBIA (0x1783)
316
286#define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621)
287#define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624)
288#define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622)
289#define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628)
290#define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626)
317#define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621)
318#define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624)
319#define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622)
320#define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628)
321#define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626)
322
291#define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030)
292#define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031)
293#define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032)
294#define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033)
295#define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040)
296#define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041)
297
323#define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030)
324#define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031)
325#define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032)
326#define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033)
327#define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040)
328#define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041)
329
330#define MPI_MANUFACTPAGE_DEVID_SA2010 (0x0804)
331#define MPI_MANUFACTPAGE_DEVID_SA2010ZC (0x0805)
332#define MPI_MANUFACTPAGE_DEVID_SA2020 (0x0806)
333#define MPI_MANUFACTPAGE_DEVID_SA2020ZC (0x0807)
334
335#define MPI_MANUFACTPAGE_DEVID_SNP1000 (0x0010)
336#define MPI_MANUFACTPAGE_DEVID_SNP500 (0x0020)
337
338
339
298typedef struct _CONFIG_PAGE_MANUFACTURING_0
299{
340typedef struct _CONFIG_PAGE_MANUFACTURING_0
341{
300 fCONFIG_PAGE_HEADER Header; /* 00h */
342 CONFIG_PAGE_HEADER Header; /* 00h */
301 U8 ChipName[16]; /* 04h */
302 U8 ChipRevision[8]; /* 14h */
303 U8 BoardName[16]; /* 1Ch */
304 U8 BoardAssembly[16]; /* 2Ch */
305 U8 BoardTracerNumber[16]; /* 3Ch */
306
343 U8 ChipName[16]; /* 04h */
344 U8 ChipRevision[8]; /* 14h */
345 U8 BoardName[16]; /* 1Ch */
346 U8 BoardAssembly[16]; /* 2Ch */
347 U8 BoardTracerNumber[16]; /* 3Ch */
348
307} fCONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0,
349} CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0,
308 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t;
309
310#define MPI_MANUFACTURING0_PAGEVERSION (0x00)
311
312
313typedef struct _CONFIG_PAGE_MANUFACTURING_1
314{
350 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t;
351
352#define MPI_MANUFACTURING0_PAGEVERSION (0x00)
353
354
355typedef struct _CONFIG_PAGE_MANUFACTURING_1
356{
315 fCONFIG_PAGE_HEADER Header; /* 00h */
357 CONFIG_PAGE_HEADER Header; /* 00h */
316 U8 VPD[256]; /* 04h */
358 U8 VPD[256]; /* 04h */
317} fCONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1,
359} CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1,
318 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t;
319
320#define MPI_MANUFACTURING1_PAGEVERSION (0x00)
321
322
323typedef struct _MPI_CHIP_REVISION_ID
324{
325 U16 DeviceID; /* 00h */

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334 * one and check Header.PageLength at runtime.
335 */
336#ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS
337#define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
338#endif
339
340typedef struct _CONFIG_PAGE_MANUFACTURING_2
341{
360 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t;
361
362#define MPI_MANUFACTURING1_PAGEVERSION (0x00)
363
364
365typedef struct _MPI_CHIP_REVISION_ID
366{
367 U16 DeviceID; /* 00h */

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376 * one and check Header.PageLength at runtime.
377 */
378#ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS
379#define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
380#endif
381
382typedef struct _CONFIG_PAGE_MANUFACTURING_2
383{
342 fCONFIG_PAGE_HEADER Header; /* 00h */
384 CONFIG_PAGE_HEADER Header; /* 00h */
343 MPI_CHIP_REVISION_ID ChipId; /* 04h */
344 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */
385 MPI_CHIP_REVISION_ID ChipId; /* 04h */
386 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */
345} fCONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2,
387} CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2,
346 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t;
347
348#define MPI_MANUFACTURING2_PAGEVERSION (0x00)
349
350
351/*
352 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
353 * one and check Header.PageLength at runtime.
354 */
355#ifndef MPI_MAN_PAGE_3_INFO_WORDS
356#define MPI_MAN_PAGE_3_INFO_WORDS (1)
357#endif
358
359typedef struct _CONFIG_PAGE_MANUFACTURING_3
360{
388 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t;
389
390#define MPI_MANUFACTURING2_PAGEVERSION (0x00)
391
392
393/*
394 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
395 * one and check Header.PageLength at runtime.
396 */
397#ifndef MPI_MAN_PAGE_3_INFO_WORDS
398#define MPI_MAN_PAGE_3_INFO_WORDS (1)
399#endif
400
401typedef struct _CONFIG_PAGE_MANUFACTURING_3
402{
361 fCONFIG_PAGE_HEADER Header; /* 00h */
403 CONFIG_PAGE_HEADER Header; /* 00h */
362 MPI_CHIP_REVISION_ID ChipId; /* 04h */
363 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */
404 MPI_CHIP_REVISION_ID ChipId; /* 04h */
405 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */
364} fCONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3,
406} CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3,
365 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t;
366
367#define MPI_MANUFACTURING3_PAGEVERSION (0x00)
368
369
370typedef struct _CONFIG_PAGE_MANUFACTURING_4
371{
407 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t;
408
409#define MPI_MANUFACTURING3_PAGEVERSION (0x00)
410
411
412typedef struct _CONFIG_PAGE_MANUFACTURING_4
413{
372 fCONFIG_PAGE_HEADER Header; /* 00h */
414 CONFIG_PAGE_HEADER Header; /* 00h */
373 U32 Reserved1; /* 04h */
374 U8 InfoOffset0; /* 08h */
375 U8 InfoSize0; /* 09h */
376 U8 InfoOffset1; /* 0Ah */
377 U8 InfoSize1; /* 0Bh */
378 U8 InquirySize; /* 0Ch */
379 U8 Reserved2; /* 0Dh */
380 U16 Reserved3; /* 0Eh */
381 U8 InquiryData[56]; /* 10h */
382 U32 ISVolumeSettings; /* 48h */
383 U32 IMEVolumeSettings; /* 4Ch */
384 U32 IMVolumeSettings; /* 50h */
415 U32 Reserved1; /* 04h */
416 U8 InfoOffset0; /* 08h */
417 U8 InfoSize0; /* 09h */
418 U8 InfoOffset1; /* 0Ah */
419 U8 InfoSize1; /* 0Bh */
420 U8 InquirySize; /* 0Ch */
421 U8 Reserved2; /* 0Dh */
422 U16 Reserved3; /* 0Eh */
423 U8 InquiryData[56]; /* 10h */
424 U32 ISVolumeSettings; /* 48h */
425 U32 IMEVolumeSettings; /* 4Ch */
426 U32 IMVolumeSettings; /* 50h */
385} fCONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4,
427} CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4,
386 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t;
387
388#define MPI_MANUFACTURING4_PAGEVERSION (0x00)
389
390
391/****************************************************************************
392* IO Unit Config Pages
393****************************************************************************/
394
395typedef struct _CONFIG_PAGE_IO_UNIT_0
396{
428 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t;
429
430#define MPI_MANUFACTURING4_PAGEVERSION (0x00)
431
432
433/****************************************************************************
434* IO Unit Config Pages
435****************************************************************************/
436
437typedef struct _CONFIG_PAGE_IO_UNIT_0
438{
397 fCONFIG_PAGE_HEADER Header; /* 00h */
439 CONFIG_PAGE_HEADER Header; /* 00h */
398 U64 UniqueValue; /* 04h */
440 U64 UniqueValue; /* 04h */
399} fCONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0,
441} CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0,
400 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t;
401
402#define MPI_IOUNITPAGE0_PAGEVERSION (0x00)
403
404
405typedef struct _CONFIG_PAGE_IO_UNIT_1
406{
442 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t;
443
444#define MPI_IOUNITPAGE0_PAGEVERSION (0x00)
445
446
447typedef struct _CONFIG_PAGE_IO_UNIT_1
448{
407 fCONFIG_PAGE_HEADER Header; /* 00h */
449 CONFIG_PAGE_HEADER Header; /* 00h */
408 U32 Flags; /* 04h */
450 U32 Flags; /* 04h */
409} fCONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1,
451} CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1,
410 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t;
411
412#define MPI_IOUNITPAGE1_PAGEVERSION (0x00)
413
414/* IO Unit Page 1 Flags defines */
415
416#define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000)
417#define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001)

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429} MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO,
430 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t;
431
432#define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
433#define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
434
435typedef struct _CONFIG_PAGE_IO_UNIT_2
436{
452 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t;
453
454#define MPI_IOUNITPAGE1_PAGEVERSION (0x00)
455
456/* IO Unit Page 1 Flags defines */
457
458#define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000)
459#define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001)

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471} MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO,
472 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t;
473
474#define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
475#define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
476
477typedef struct _CONFIG_PAGE_IO_UNIT_2
478{
437 fCONFIG_PAGE_HEADER Header; /* 00h */
479 CONFIG_PAGE_HEADER Header; /* 00h */
438 U32 Flags; /* 04h */
439 U32 BiosVersion; /* 08h */
440 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */
480 U32 Flags; /* 04h */
481 U32 BiosVersion; /* 08h */
482 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */
441} fCONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2,
483} CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2,
442 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t;
443
444#define MPI_IOUNITPAGE2_PAGEVERSION (0x00)
445
446#define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002)
447#define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004)
448#define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008)
449#define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010)

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454 * one and check Header.PageLength at runtime.
455 */
456#ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX
457#define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
458#endif
459
460typedef struct _CONFIG_PAGE_IO_UNIT_3
461{
484 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t;
485
486#define MPI_IOUNITPAGE2_PAGEVERSION (0x00)
487
488#define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002)
489#define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004)
490#define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008)
491#define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010)

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496 * one and check Header.PageLength at runtime.
497 */
498#ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX
499#define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
500#endif
501
502typedef struct _CONFIG_PAGE_IO_UNIT_3
503{
462 fCONFIG_PAGE_HEADER Header; /* 00h */
504 CONFIG_PAGE_HEADER Header; /* 00h */
463 U8 GPIOCount; /* 04h */
464 U8 Reserved1; /* 05h */
465 U16 Reserved2; /* 06h */
466 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */
505 U8 GPIOCount; /* 04h */
506 U8 Reserved1; /* 05h */
507 U16 Reserved2; /* 06h */
508 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */
467} fCONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3,
509} CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3,
468 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t;
469
470#define MPI_IOUNITPAGE3_PAGEVERSION (0x01)
471
472#define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC)
473#define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
474#define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00)
475#define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01)
476
477
478/****************************************************************************
479* IOC Config Pages
480****************************************************************************/
481
482typedef struct _CONFIG_PAGE_IOC_0
483{
510 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t;
511
512#define MPI_IOUNITPAGE3_PAGEVERSION (0x01)
513
514#define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC)
515#define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
516#define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00)
517#define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01)
518
519
520/****************************************************************************
521* IOC Config Pages
522****************************************************************************/
523
524typedef struct _CONFIG_PAGE_IOC_0
525{
484 fCONFIG_PAGE_HEADER Header; /* 00h */
526 CONFIG_PAGE_HEADER Header; /* 00h */
485 U32 TotalNVStore; /* 04h */
486 U32 FreeNVStore; /* 08h */
487 U16 VendorID; /* 0Ch */
488 U16 DeviceID; /* 0Eh */
489 U8 RevisionID; /* 10h */
490 U8 Reserved[3]; /* 11h */
491 U32 ClassCode; /* 14h */
492 U16 SubsystemVendorID; /* 18h */
493 U16 SubsystemID; /* 1Ah */
527 U32 TotalNVStore; /* 04h */
528 U32 FreeNVStore; /* 08h */
529 U16 VendorID; /* 0Ch */
530 U16 DeviceID; /* 0Eh */
531 U8 RevisionID; /* 10h */
532 U8 Reserved[3]; /* 11h */
533 U32 ClassCode; /* 14h */
534 U16 SubsystemVendorID; /* 18h */
535 U16 SubsystemID; /* 1Ah */
494} fCONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0,
536} CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0,
495 IOCPage0_t, MPI_POINTER pIOCPage0_t;
496
497#define MPI_IOCPAGE0_PAGEVERSION (0x01)
498
499
500typedef struct _CONFIG_PAGE_IOC_1
501{
537 IOCPage0_t, MPI_POINTER pIOCPage0_t;
538
539#define MPI_IOCPAGE0_PAGEVERSION (0x01)
540
541
542typedef struct _CONFIG_PAGE_IOC_1
543{
502 fCONFIG_PAGE_HEADER Header; /* 00h */
544 CONFIG_PAGE_HEADER Header; /* 00h */
503 U32 Flags; /* 04h */
504 U32 CoalescingTimeout; /* 08h */
505 U8 CoalescingDepth; /* 0Ch */
545 U32 Flags; /* 04h */
546 U32 CoalescingTimeout; /* 08h */
547 U8 CoalescingDepth; /* 0Ch */
506 U8 Reserved[3]; /* 0Dh */
507} fCONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1,
548 U8 PCISlotNum; /* 0Dh */
549 U8 Reserved[2]; /* 0Eh */
550} CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1,
508 IOCPage1_t, MPI_POINTER pIOCPage1_t;
509
551 IOCPage1_t, MPI_POINTER pIOCPage1_t;
552
510#define MPI_IOCPAGE1_PAGEVERSION (0x00)
553#define MPI_IOCPAGE1_PAGEVERSION (0x01)
511
512#define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001)
513
554
555#define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001)
556
557#define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
514
558
559
515typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL
516{
517 U8 VolumeID; /* 00h */
518 U8 VolumeBus; /* 01h */
519 U8 VolumeIOC; /* 02h */
520 U8 VolumePageNumber; /* 03h */
521 U8 VolumeType; /* 04h */
560typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL
561{
562 U8 VolumeID; /* 00h */
563 U8 VolumeBus; /* 01h */
564 U8 VolumeIOC; /* 02h */
565 U8 VolumePageNumber; /* 03h */
566 U8 VolumeType; /* 04h */
522 U8 Reserved2; /* 05h */
567 U8 Flags; /* 05h */
523 U16 Reserved3; /* 06h */
568 U16 Reserved3; /* 06h */
524} fCONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL,
569} CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL,
525 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t;
526
570 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t;
571
572/* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */
573
574#define MPI_RAID_VOL_TYPE_IS (0x00)
575#define MPI_RAID_VOL_TYPE_IME (0x01)
576#define MPI_RAID_VOL_TYPE_IM (0x02)
577
578/* IOC Page 2 Volume Flags values */
579
580#define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08)
581
527/*
528 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
529 * one and check Header.PageLength at runtime.
530 */
531#ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX
532#define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1)
533#endif
534
535typedef struct _CONFIG_PAGE_IOC_2
536{
582/*
583 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
584 * one and check Header.PageLength at runtime.
585 */
586#ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX
587#define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1)
588#endif
589
590typedef struct _CONFIG_PAGE_IOC_2
591{
537 fCONFIG_PAGE_HEADER Header; /* 00h */
592 CONFIG_PAGE_HEADER Header; /* 00h */
538 U32 CapabilitiesFlags; /* 04h */
539 U8 NumActiveVolumes; /* 08h */
540 U8 MaxVolumes; /* 09h */
541 U8 NumActivePhysDisks; /* 0Ah */
542 U8 MaxPhysDisks; /* 0Bh */
593 U32 CapabilitiesFlags; /* 04h */
594 U8 NumActiveVolumes; /* 08h */
595 U8 MaxVolumes; /* 09h */
596 U8 NumActivePhysDisks; /* 0Ah */
597 U8 MaxPhysDisks; /* 0Bh */
543 fCONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */
544} fCONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2,
598 CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */
599} CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2,
545 IOCPage2_t, MPI_POINTER pIOCPage2_t;
546
600 IOCPage2_t, MPI_POINTER pIOCPage2_t;
601
547#define MPI_IOCPAGE2_PAGEVERSION (0x01)
602#define MPI_IOCPAGE2_PAGEVERSION (0x02)
548
549/* IOC Page 2 Capabilities flags */
550
551#define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001)
552#define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002)
553#define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004)
554#define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000)
555#define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000)
556#define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000)
557
603
604/* IOC Page 2 Capabilities flags */
605
606#define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001)
607#define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002)
608#define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004)
609#define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000)
610#define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000)
611#define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000)
612
558/* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */
559
613
560#define MPI_RAID_VOL_TYPE_IS (0x00)
561#define MPI_RAID_VOL_TYPE_IME (0x01)
562#define MPI_RAID_VOL_TYPE_IM (0x02)
563
564
565typedef struct _IOC_3_PHYS_DISK
566{
567 U8 PhysDiskID; /* 00h */
568 U8 PhysDiskBus; /* 01h */
569 U8 PhysDiskIOC; /* 02h */
570 U8 PhysDiskNum; /* 03h */
571} IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK,
572 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t;
573
574/*
575 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
576 * one and check Header.PageLength at runtime.
577 */
578#ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX
579#define MPI_IOC_PAGE_3_PHYSDISK_MAX (1)
580#endif
581
582typedef struct _CONFIG_PAGE_IOC_3
583{
614typedef struct _IOC_3_PHYS_DISK
615{
616 U8 PhysDiskID; /* 00h */
617 U8 PhysDiskBus; /* 01h */
618 U8 PhysDiskIOC; /* 02h */
619 U8 PhysDiskNum; /* 03h */
620} IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK,
621 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t;
622
623/*
624 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
625 * one and check Header.PageLength at runtime.
626 */
627#ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX
628#define MPI_IOC_PAGE_3_PHYSDISK_MAX (1)
629#endif
630
631typedef struct _CONFIG_PAGE_IOC_3
632{
584 fCONFIG_PAGE_HEADER Header; /* 00h */
633 CONFIG_PAGE_HEADER Header; /* 00h */
585 U8 NumPhysDisks; /* 04h */
586 U8 Reserved1; /* 05h */
587 U16 Reserved2; /* 06h */
588 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */
634 U8 NumPhysDisks; /* 04h */
635 U8 Reserved1; /* 05h */
636 U16 Reserved2; /* 06h */
637 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */
589} fCONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3,
638} CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3,
590 IOCPage3_t, MPI_POINTER pIOCPage3_t;
591
592#define MPI_IOCPAGE3_PAGEVERSION (0x00)
593
594
595typedef struct _IOC_4_SEP
596{
597 U8 SEPTargetID; /* 00h */

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605 * one and check Header.PageLength at runtime.
606 */
607#ifndef MPI_IOC_PAGE_4_SEP_MAX
608#define MPI_IOC_PAGE_4_SEP_MAX (1)
609#endif
610
611typedef struct _CONFIG_PAGE_IOC_4
612{
639 IOCPage3_t, MPI_POINTER pIOCPage3_t;
640
641#define MPI_IOCPAGE3_PAGEVERSION (0x00)
642
643
644typedef struct _IOC_4_SEP
645{
646 U8 SEPTargetID; /* 00h */

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654 * one and check Header.PageLength at runtime.
655 */
656#ifndef MPI_IOC_PAGE_4_SEP_MAX
657#define MPI_IOC_PAGE_4_SEP_MAX (1)
658#endif
659
660typedef struct _CONFIG_PAGE_IOC_4
661{
613 fCONFIG_PAGE_HEADER Header; /* 00h */
662 CONFIG_PAGE_HEADER Header; /* 00h */
614 U8 ActiveSEP; /* 04h */
615 U8 MaxSEP; /* 05h */
616 U16 Reserved1; /* 06h */
617 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */
663 U8 ActiveSEP; /* 04h */
664 U8 MaxSEP; /* 05h */
665 U16 Reserved1; /* 06h */
666 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */
618} fCONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4,
667} CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4,
619 IOCPage4_t, MPI_POINTER pIOCPage4_t;
620
621#define MPI_IOCPAGE4_PAGEVERSION (0x00)
622
623
668 IOCPage4_t, MPI_POINTER pIOCPage4_t;
669
670#define MPI_IOCPAGE4_PAGEVERSION (0x00)
671
672
673typedef struct _IOC_5_HOT_SPARE
674{
675 U8 PhysDiskNum; /* 00h */
676 U8 Reserved; /* 01h */
677 U8 HotSparePool; /* 02h */
678 U8 Flags; /* 03h */
679} IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE,
680 Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t;
681
682/* IOC Page 5 HotSpare Flags */
683#define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01)
684
685/*
686 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
687 * one and check Header.PageLength at runtime.
688 */
689#ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX
690#define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1)
691#endif
692
693typedef struct _CONFIG_PAGE_IOC_5
694{
695 CONFIG_PAGE_HEADER Header; /* 00h */
696 U32 Reserved1; /* 04h */
697 U8 NumHotSpares; /* 08h */
698 U8 Reserved2; /* 09h */
699 U16 Reserved3; /* 0Ah */
700 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */
701} CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5,
702 IOCPage5_t, MPI_POINTER pIOCPage5_t;
703
704#define MPI_IOCPAGE5_PAGEVERSION (0x00)
705
706
707
624/****************************************************************************
625* SCSI Port Config Pages
626****************************************************************************/
627
628typedef struct _CONFIG_PAGE_SCSI_PORT_0
629{
708/****************************************************************************
709* SCSI Port Config Pages
710****************************************************************************/
711
712typedef struct _CONFIG_PAGE_SCSI_PORT_0
713{
630 fCONFIG_PAGE_HEADER Header; /* 00h */
714 CONFIG_PAGE_HEADER Header; /* 00h */
631 U32 Capabilities; /* 04h */
632 U32 PhysicalInterface; /* 08h */
715 U32 Capabilities; /* 04h */
716 U32 PhysicalInterface; /* 08h */
633} fCONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0,
717} CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0,
634 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t;
635
636#define MPI_SCSIPORTPAGE0_PAGEVERSION (0x01)
637
638#define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001)
639#define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002)
640#define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004)
641#define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
642#define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
643#define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000)
644#define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000)
645
646#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003)
647#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01)
648#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02)
649#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03)
718 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t;
719
720#define MPI_SCSIPORTPAGE0_PAGEVERSION (0x01)
721
722#define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001)
723#define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002)
724#define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004)
725#define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
726#define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
727#define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000)
728#define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000)
729
730#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003)
731#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01)
732#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02)
733#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03)
734#define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000)
735#define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24)
736#define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE)
737#define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF)
650
651
652typedef struct _CONFIG_PAGE_SCSI_PORT_1
653{
738
739
740typedef struct _CONFIG_PAGE_SCSI_PORT_1
741{
654 fCONFIG_PAGE_HEADER Header; /* 00h */
742 CONFIG_PAGE_HEADER Header; /* 00h */
655 U32 Configuration; /* 04h */
656 U32 OnBusTimerValue; /* 08h */
743 U32 Configuration; /* 04h */
744 U32 OnBusTimerValue; /* 08h */
657} fCONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1,
745} CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1,
658 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;
659
660#define MPI_SCSIPORTPAGE1_PAGEVERSION (0x02)
661
662#define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF)
663#define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000)
664
665
666typedef struct _MPI_DEVICE_INFO
667{
668 U8 Timeout; /* 00h */
669 U8 SyncFactor; /* 01h */
670 U16 DeviceFlags; /* 02h */
671} MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO,
672 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t;
673
674typedef struct _CONFIG_PAGE_SCSI_PORT_2
675{
746 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;
747
748#define MPI_SCSIPORTPAGE1_PAGEVERSION (0x02)
749
750#define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF)
751#define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000)
752
753
754typedef struct _MPI_DEVICE_INFO
755{
756 U8 Timeout; /* 00h */
757 U8 SyncFactor; /* 01h */
758 U16 DeviceFlags; /* 02h */
759} MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO,
760 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t;
761
762typedef struct _CONFIG_PAGE_SCSI_PORT_2
763{
676 fCONFIG_PAGE_HEADER Header; /* 00h */
764 CONFIG_PAGE_HEADER Header; /* 00h */
677 U32 PortFlags; /* 04h */
678 U32 PortSettings; /* 08h */
679 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */
765 U32 PortFlags; /* 04h */
766 U32 PortSettings; /* 08h */
767 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */
680} fCONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2,
768} CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2,
681 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t;
682
683#define MPI_SCSIPORTPAGE2_PAGEVERSION (0x01)
684
685#define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001)
686#define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004)
687#define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
688#define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010)

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709
710
711/****************************************************************************
712* SCSI Target Device Config Pages
713****************************************************************************/
714
715typedef struct _CONFIG_PAGE_SCSI_DEVICE_0
716{
769 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t;
770
771#define MPI_SCSIPORTPAGE2_PAGEVERSION (0x01)
772
773#define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001)
774#define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004)
775#define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
776#define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010)

--- 20 unchanged lines hidden (view full) ---

797
798
799/****************************************************************************
800* SCSI Target Device Config Pages
801****************************************************************************/
802
803typedef struct _CONFIG_PAGE_SCSI_DEVICE_0
804{
717 fCONFIG_PAGE_HEADER Header; /* 00h */
805 CONFIG_PAGE_HEADER Header; /* 00h */
718 U32 NegotiatedParameters; /* 04h */
719 U32 Information; /* 08h */
806 U32 NegotiatedParameters; /* 04h */
807 U32 Information; /* 08h */
720} fCONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0,
808} CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0,
721 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t;
722
809 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t;
810
723#define MPI_SCSIDEVPAGE0_PAGEVERSION (0x02)
811#define MPI_SCSIDEVPAGE0_PAGEVERSION (0x03)
724
725#define MPI_SCSIDEVPAGE0_NP_IU (0x00000001)
726#define MPI_SCSIDEVPAGE0_NP_DT (0x00000002)
727#define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004)
812
813#define MPI_SCSIDEVPAGE0_NP_IU (0x00000001)
814#define MPI_SCSIDEVPAGE0_NP_DT (0x00000002)
815#define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004)
816#define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008)
817#define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010)
818#define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020)
819#define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040)
820#define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080)
728#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00)
729#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000)
730#define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000)
731#define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000)
732
733#define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001)
734#define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002)
735#define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004)
736#define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008)
737
738
739typedef struct _CONFIG_PAGE_SCSI_DEVICE_1
740{
821#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00)
822#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000)
823#define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000)
824#define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000)
825
826#define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001)
827#define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002)
828#define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004)
829#define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008)
830
831
832typedef struct _CONFIG_PAGE_SCSI_DEVICE_1
833{
741 fCONFIG_PAGE_HEADER Header; /* 00h */
834 CONFIG_PAGE_HEADER Header; /* 00h */
742 U32 RequestedParameters; /* 04h */
743 U32 Reserved; /* 08h */
744 U32 Configuration; /* 0Ch */
835 U32 RequestedParameters; /* 04h */
836 U32 Reserved; /* 08h */
837 U32 Configuration; /* 0Ch */
745} fCONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1,
838} CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1,
746 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t;
747
839 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t;
840
748#define MPI_SCSIDEVPAGE1_PAGEVERSION (0x03)
841#define MPI_SCSIDEVPAGE1_PAGEVERSION (0x04)
749
750#define MPI_SCSIDEVPAGE1_RP_IU (0x00000001)
751#define MPI_SCSIDEVPAGE1_RP_DT (0x00000002)
752#define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004)
842
843#define MPI_SCSIDEVPAGE1_RP_IU (0x00000001)
844#define MPI_SCSIDEVPAGE1_RP_DT (0x00000002)
845#define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004)
846#define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008)
847#define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010)
848#define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020)
849#define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040)
850#define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080)
753#define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
754#define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
755#define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000)
756#define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000)
757
851#define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
852#define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
853#define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000)
854#define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000)
855
758#define MPI_SCSIDEVPAGE1_DV_LVD_DRIVE_STRENGTH_MASK (0x00000003)
759#define MPI_SCSIDEVPAGE1_DV_SE_SLEW_RATE_MASK (0x00000300)
760
761#define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002)
762#define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004)
856#define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002)
857#define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004)
858#define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008)
859#define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010)
763
764
765typedef struct _CONFIG_PAGE_SCSI_DEVICE_2
766{
860
861
862typedef struct _CONFIG_PAGE_SCSI_DEVICE_2
863{
767 fCONFIG_PAGE_HEADER Header; /* 00h */
864 CONFIG_PAGE_HEADER Header; /* 00h */
768 U32 DomainValidation; /* 04h */
769 U32 ParityPipeSelect; /* 08h */
770 U32 DataPipeSelect; /* 0Ch */
865 U32 DomainValidation; /* 04h */
866 U32 ParityPipeSelect; /* 08h */
867 U32 DataPipeSelect; /* 0Ch */
771} fCONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2,
868} CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2,
772 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t;
773
869 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t;
870
774#define MPI_SCSIDEVPAGE2_PAGEVERSION (0x00)
871#define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01)
775
776#define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010)
777#define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020)
778#define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380)
779#define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00)
780#define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000)
781#define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000)
782#define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000)

--- 15 unchanged lines hidden (view full) ---

798#define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000)
799#define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000)
800#define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000)
801#define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000)
802#define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000)
803#define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000)
804
805
872
873#define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010)
874#define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020)
875#define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380)
876#define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00)
877#define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000)
878#define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000)
879#define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000)

--- 15 unchanged lines hidden (view full) ---

895#define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000)
896#define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000)
897#define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000)
898#define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000)
899#define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000)
900#define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000)
901
902
903typedef struct _CONFIG_PAGE_SCSI_DEVICE_3
904{
905 CONFIG_PAGE_HEADER Header; /* 00h */
906 U16 MsgRejectCount; /* 04h */
907 U16 PhaseErrorCount; /* 06h */
908 U16 ParityErrorCount; /* 08h */
909 U16 Reserved; /* 0Ah */
910} CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3,
911 SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t;
912
913#define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00)
914
915#define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE)
916#define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF)
917
918
806/****************************************************************************
807* FC Port Config Pages
808****************************************************************************/
809
810typedef struct _CONFIG_PAGE_FC_PORT_0
811{
919/****************************************************************************
920* FC Port Config Pages
921****************************************************************************/
922
923typedef struct _CONFIG_PAGE_FC_PORT_0
924{
812 fCONFIG_PAGE_HEADER Header; /* 00h */
925 CONFIG_PAGE_HEADER Header; /* 00h */
813 U32 Flags; /* 04h */
814 U8 MPIPortNumber; /* 08h */
815 U8 LinkType; /* 09h */
816 U8 PortState; /* 0Ah */
817 U8 Reserved; /* 0Bh */
818 U32 PortIdentifier; /* 0Ch */
819 U64 WWNN; /* 10h */
820 U64 WWPN; /* 18h */
821 U32 SupportedServiceClass; /* 20h */
822 U32 SupportedSpeeds; /* 24h */
823 U32 CurrentSpeed; /* 28h */
824 U32 MaxFrameSize; /* 2Ch */
825 U64 FabricWWNN; /* 30h */
826 U64 FabricWWPN; /* 38h */
827 U32 DiscoveredPortsCount; /* 40h */
828 U32 MaxInitiators; /* 44h */
926 U32 Flags; /* 04h */
927 U8 MPIPortNumber; /* 08h */
928 U8 LinkType; /* 09h */
929 U8 PortState; /* 0Ah */
930 U8 Reserved; /* 0Bh */
931 U32 PortIdentifier; /* 0Ch */
932 U64 WWNN; /* 10h */
933 U64 WWPN; /* 18h */
934 U32 SupportedServiceClass; /* 20h */
935 U32 SupportedSpeeds; /* 24h */
936 U32 CurrentSpeed; /* 28h */
937 U32 MaxFrameSize; /* 2Ch */
938 U64 FabricWWNN; /* 30h */
939 U64 FabricWWPN; /* 38h */
940 U32 DiscoveredPortsCount; /* 40h */
941 U32 MaxInitiators; /* 44h */
829} fCONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0,
942 U8 MaxAliasesSupported; /* 48h */
943 U8 MaxHardAliasesSupported; /* 49h */
944 U8 NumCurrentAliases; /* 4Ah */
945 U8 Reserved1; /* 4Bh */
946} CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0,
830 FCPortPage0_t, MPI_POINTER pFCPortPage0_t;
831
947 FCPortPage0_t, MPI_POINTER pFCPortPage0_t;
948
832#define MPI_FCPORTPAGE0_PAGEVERSION (0x01)
949#define MPI_FCPORTPAGE0_PAGEVERSION (0x02)
833
834#define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F)
835#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR)
836#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET)
837#define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN)
838#define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR)
839
840#define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010)
841#define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020)
950
951#define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F)
952#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR)
953#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET)
954#define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN)
955#define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR)
956
957#define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010)
958#define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020)
842#define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000030)
959#define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040)
843
844#define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00)
845#define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000)
846#define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100)
847#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200)
848#define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400)
849#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800)
850

--- 33 unchanged lines hidden (view full) ---

884
885#define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED
886#define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED
887#define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED
888
889
890typedef struct _CONFIG_PAGE_FC_PORT_1
891{
960
961#define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00)
962#define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000)
963#define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100)
964#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200)
965#define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400)
966#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800)
967

--- 33 unchanged lines hidden (view full) ---

1001
1002#define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED
1003#define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED
1004#define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED
1005
1006
1007typedef struct _CONFIG_PAGE_FC_PORT_1
1008{
892 fCONFIG_PAGE_HEADER Header; /* 00h */
1009 CONFIG_PAGE_HEADER Header; /* 00h */
893 U32 Flags; /* 04h */
894 U64 NoSEEPROMWWNN; /* 08h */
895 U64 NoSEEPROMWWPN; /* 10h */
896 U8 HardALPA; /* 18h */
897 U8 LinkConfig; /* 19h */
898 U8 TopologyConfig; /* 1Ah */
1010 U32 Flags; /* 04h */
1011 U64 NoSEEPROMWWNN; /* 08h */
1012 U64 NoSEEPROMWWPN; /* 10h */
1013 U8 HardALPA; /* 18h */
1014 U8 LinkConfig; /* 19h */
1015 U8 TopologyConfig; /* 1Ah */
899 U8 Reserved; /* 1Bh */
900} fCONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1,
1016 U8 AltConnector; /* 1Bh */
1017 U8 NumRequestedAliases; /* 1Ch */
1018 U8 RR_TOV; /* 1Dh */
1019 U16 Reserved2; /* 1Eh */
1020} CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1,
901 FCPortPage1_t, MPI_POINTER pFCPortPage1_t;
902
1021 FCPortPage1_t, MPI_POINTER pFCPortPage1_t;
1022
903#define MPI_FCPORTPAGE1_PAGEVERSION (0x02)
1023#define MPI_FCPORTPAGE1_PAGEVERSION (0x05)
904
905#define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000)
906#define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000)
1024
1025#define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000)
1026#define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000)
1027#define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000)
1028#define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000)
1029#define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000)
1030#define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070)
1031#define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002)
907#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001)
908#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000)
909
910#define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000)
911#define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28)
912#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
913#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
914#define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
915#define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
916
1032#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001)
1033#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000)
1034
1035#define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000)
1036#define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28)
1037#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1038#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1039#define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1040#define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1041
1042#define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000)
1043#define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010)
1044#define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030)
1045#define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050)
1046
917#define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF)
918
919#define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F)
920#define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00)
921#define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01)
922#define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02)
923#define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03)
924#define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F)
925
926#define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F)
927#define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01)
928#define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02)
929#define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F)
930
1047#define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF)
1048
1049#define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F)
1050#define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00)
1051#define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01)
1052#define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02)
1053#define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03)
1054#define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F)
1055
1056#define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F)
1057#define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01)
1058#define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02)
1059#define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F)
1060
1061#define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00)
931
1062
1063
932typedef struct _CONFIG_PAGE_FC_PORT_2
933{
1064typedef struct _CONFIG_PAGE_FC_PORT_2
1065{
934 fCONFIG_PAGE_HEADER Header; /* 00h */
1066 CONFIG_PAGE_HEADER Header; /* 00h */
935 U8 NumberActive; /* 04h */
936 U8 ALPA[127]; /* 05h */
1067 U8 NumberActive; /* 04h */
1068 U8 ALPA[127]; /* 05h */
937} fCONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2,
1069} CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2,
938 FCPortPage2_t, MPI_POINTER pFCPortPage2_t;
939
940#define MPI_FCPORTPAGE2_PAGEVERSION (0x01)
941
942
943typedef struct _WWN_FORMAT
944{
945 U64 WWNN; /* 00h */

--- 29 unchanged lines hidden (view full) ---

975 * one and check Header.PageLength at runtime.
976 */
977#ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX
978#define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1)
979#endif
980
981typedef struct _CONFIG_PAGE_FC_PORT_3
982{
1070 FCPortPage2_t, MPI_POINTER pFCPortPage2_t;
1071
1072#define MPI_FCPORTPAGE2_PAGEVERSION (0x01)
1073
1074
1075typedef struct _WWN_FORMAT
1076{
1077 U64 WWNN; /* 00h */

--- 29 unchanged lines hidden (view full) ---

1107 * one and check Header.PageLength at runtime.
1108 */
1109#ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX
1110#define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1)
1111#endif
1112
1113typedef struct _CONFIG_PAGE_FC_PORT_3
1114{
983 fCONFIG_PAGE_HEADER Header; /* 00h */
1115 CONFIG_PAGE_HEADER Header; /* 00h */
984 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */
1116 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */
985} fCONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3,
1117} CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3,
986 FCPortPage3_t, MPI_POINTER pFCPortPage3_t;
987
988#define MPI_FCPORTPAGE3_PAGEVERSION (0x01)
989
990
991typedef struct _CONFIG_PAGE_FC_PORT_4
992{
1118 FCPortPage3_t, MPI_POINTER pFCPortPage3_t;
1119
1120#define MPI_FCPORTPAGE3_PAGEVERSION (0x01)
1121
1122
1123typedef struct _CONFIG_PAGE_FC_PORT_4
1124{
993 fCONFIG_PAGE_HEADER Header; /* 00h */
1125 CONFIG_PAGE_HEADER Header; /* 00h */
994 U32 PortFlags; /* 04h */
995 U32 PortSettings; /* 08h */
1126 U32 PortFlags; /* 04h */
1127 U32 PortSettings; /* 08h */
996} fCONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4,
1128} CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4,
997 FCPortPage4_t, MPI_POINTER pFCPortPage4_t;
998
999#define MPI_FCPORTPAGE4_PAGEVERSION (0x00)
1000
1001#define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
1002
1003#define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030)
1004#define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000)

--- 6 unchanged lines hidden (view full) ---

1011
1012typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO
1013{
1014 U8 Flags; /* 00h */
1015 U8 AliasAlpa; /* 01h */
1016 U16 Reserved; /* 02h */
1017 U64 AliasWWNN; /* 04h */
1018 U64 AliasWWPN; /* 0Ch */
1129 FCPortPage4_t, MPI_POINTER pFCPortPage4_t;
1130
1131#define MPI_FCPORTPAGE4_PAGEVERSION (0x00)
1132
1133#define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
1134
1135#define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030)
1136#define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000)

--- 6 unchanged lines hidden (view full) ---

1143
1144typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO
1145{
1146 U8 Flags; /* 00h */
1147 U8 AliasAlpa; /* 01h */
1148 U16 Reserved; /* 02h */
1149 U64 AliasWWNN; /* 04h */
1150 U64 AliasWWPN; /* 0Ch */
1019} fCONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1151} CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1020 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1021 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t;
1022
1152 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1153 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t;
1154
1023/*
1024 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1025 * one and check Header.PageLength at runtime.
1026 */
1027#ifndef MPI_FC_PORT_PAGE_5_ALIAS_MAX
1028#define MPI_FC_PORT_PAGE_5_ALIAS_MAX (1)
1029#endif
1030
1031typedef struct _CONFIG_PAGE_FC_PORT_5
1032{
1155typedef struct _CONFIG_PAGE_FC_PORT_5
1156{
1033 fCONFIG_PAGE_HEADER Header; /* 00h */
1034 fCONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo[MPI_FC_PORT_PAGE_5_ALIAS_MAX];/* 04h */
1035} fCONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5,
1157 CONFIG_PAGE_HEADER Header; /* 00h */
1158 CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */
1159} CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5,
1036 FCPortPage5_t, MPI_POINTER pFCPortPage5_t;
1037
1160 FCPortPage5_t, MPI_POINTER pFCPortPage5_t;
1161
1038#define MPI_FCPORTPAGE5_PAGEVERSION (0x00)
1162#define MPI_FCPORTPAGE5_PAGEVERSION (0x02)
1039
1163
1040#define MPI_FCPORTPAGE5_FLAGS_ALIAS_ALPA_VALID (0x01)
1041#define MPI_FCPORTPAGE5_FLAGS_ALIAS_WWN_VALID (0x02)
1164#define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01)
1165#define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02)
1166#define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04)
1167#define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08)
1168#define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10)
1042
1169
1043
1044typedef struct _CONFIG_PAGE_FC_PORT_6
1045{
1170typedef struct _CONFIG_PAGE_FC_PORT_6
1171{
1046 fCONFIG_PAGE_HEADER Header; /* 00h */
1172 CONFIG_PAGE_HEADER Header; /* 00h */
1047 U32 Reserved; /* 04h */
1048 U64 TimeSinceReset; /* 08h */
1049 U64 TxFrames; /* 10h */
1050 U64 RxFrames; /* 18h */
1051 U64 TxWords; /* 20h */
1052 U64 RxWords; /* 28h */
1053 U64 LipCount; /* 30h */
1054 U64 NosCount; /* 38h */
1055 U64 ErrorFrames; /* 40h */
1056 U64 DumpedFrames; /* 48h */
1057 U64 LinkFailureCount; /* 50h */
1058 U64 LossOfSyncCount; /* 58h */
1059 U64 LossOfSignalCount; /* 60h */
1060 U64 PrimativeSeqErrCount; /* 68h */
1061 U64 InvalidTxWordCount; /* 70h */
1062 U64 InvalidCrcCount; /* 78h */
1063 U64 FcpInitiatorIoCount; /* 80h */
1173 U32 Reserved; /* 04h */
1174 U64 TimeSinceReset; /* 08h */
1175 U64 TxFrames; /* 10h */
1176 U64 RxFrames; /* 18h */
1177 U64 TxWords; /* 20h */
1178 U64 RxWords; /* 28h */
1179 U64 LipCount; /* 30h */
1180 U64 NosCount; /* 38h */
1181 U64 ErrorFrames; /* 40h */
1182 U64 DumpedFrames; /* 48h */
1183 U64 LinkFailureCount; /* 50h */
1184 U64 LossOfSyncCount; /* 58h */
1185 U64 LossOfSignalCount; /* 60h */
1186 U64 PrimativeSeqErrCount; /* 68h */
1187 U64 InvalidTxWordCount; /* 70h */
1188 U64 InvalidCrcCount; /* 78h */
1189 U64 FcpInitiatorIoCount; /* 80h */
1064} fCONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6,
1190} CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6,
1065 FCPortPage6_t, MPI_POINTER pFCPortPage6_t;
1066
1067#define MPI_FCPORTPAGE6_PAGEVERSION (0x00)
1068
1069
1070typedef struct _CONFIG_PAGE_FC_PORT_7
1071{
1191 FCPortPage6_t, MPI_POINTER pFCPortPage6_t;
1192
1193#define MPI_FCPORTPAGE6_PAGEVERSION (0x00)
1194
1195
1196typedef struct _CONFIG_PAGE_FC_PORT_7
1197{
1072 fCONFIG_PAGE_HEADER Header; /* 00h */
1198 CONFIG_PAGE_HEADER Header; /* 00h */
1073 U32 Reserved; /* 04h */
1074 U8 PortSymbolicName[256]; /* 08h */
1199 U32 Reserved; /* 04h */
1200 U8 PortSymbolicName[256]; /* 08h */
1075} fCONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7,
1201} CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7,
1076 FCPortPage7_t, MPI_POINTER pFCPortPage7_t;
1077
1078#define MPI_FCPORTPAGE7_PAGEVERSION (0x00)
1079
1080
1081typedef struct _CONFIG_PAGE_FC_PORT_8
1082{
1202 FCPortPage7_t, MPI_POINTER pFCPortPage7_t;
1203
1204#define MPI_FCPORTPAGE7_PAGEVERSION (0x00)
1205
1206
1207typedef struct _CONFIG_PAGE_FC_PORT_8
1208{
1083 fCONFIG_PAGE_HEADER Header; /* 00h */
1209 CONFIG_PAGE_HEADER Header; /* 00h */
1084 U32 BitVector[8]; /* 04h */
1210 U32 BitVector[8]; /* 04h */
1085} fCONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8,
1211} CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8,
1086 FCPortPage8_t, MPI_POINTER pFCPortPage8_t;
1087
1088#define MPI_FCPORTPAGE8_PAGEVERSION (0x00)
1089
1090
1091typedef struct _CONFIG_PAGE_FC_PORT_9
1092{
1212 FCPortPage8_t, MPI_POINTER pFCPortPage8_t;
1213
1214#define MPI_FCPORTPAGE8_PAGEVERSION (0x00)
1215
1216
1217typedef struct _CONFIG_PAGE_FC_PORT_9
1218{
1093 fCONFIG_PAGE_HEADER Header; /* 00h */
1219 CONFIG_PAGE_HEADER Header; /* 00h */
1094 U32 Reserved; /* 04h */
1095 U64 GlobalWWPN; /* 08h */
1096 U64 GlobalWWNN; /* 10h */
1097 U32 UnitType; /* 18h */
1098 U32 PhysicalPortNumber; /* 1Ch */
1099 U32 NumAttachedNodes; /* 20h */
1100 U16 IPVersion; /* 24h */
1101 U16 UDPPortNumber; /* 26h */
1102 U8 IPAddress[16]; /* 28h */
1103 U16 Reserved1; /* 38h */
1104 U16 TopologyDiscoveryFlags; /* 3Ah */
1220 U32 Reserved; /* 04h */
1221 U64 GlobalWWPN; /* 08h */
1222 U64 GlobalWWNN; /* 10h */
1223 U32 UnitType; /* 18h */
1224 U32 PhysicalPortNumber; /* 1Ch */
1225 U32 NumAttachedNodes; /* 20h */
1226 U16 IPVersion; /* 24h */
1227 U16 UDPPortNumber; /* 26h */
1228 U8 IPAddress[16]; /* 28h */
1229 U16 Reserved1; /* 38h */
1230 U16 TopologyDiscoveryFlags; /* 3Ah */
1105} fCONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9,
1231} CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9,
1106 FCPortPage9_t, MPI_POINTER pFCPortPage9_t;
1107
1108#define MPI_FCPORTPAGE9_PAGEVERSION (0x00)
1109
1110
1232 FCPortPage9_t, MPI_POINTER pFCPortPage9_t;
1233
1234#define MPI_FCPORTPAGE9_PAGEVERSION (0x00)
1235
1236
1237typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA
1238{
1239 U8 Id; /* 10h */
1240 U8 ExtId; /* 11h */
1241 U8 Connector; /* 12h */
1242 U8 Transceiver[8]; /* 13h */
1243 U8 Encoding; /* 1Bh */
1244 U8 BitRate_100mbs; /* 1Ch */
1245 U8 Reserved1; /* 1Dh */
1246 U8 Length9u_km; /* 1Eh */
1247 U8 Length9u_100m; /* 1Fh */
1248 U8 Length50u_10m; /* 20h */
1249 U8 Length62p5u_10m; /* 21h */
1250 U8 LengthCopper_m; /* 22h */
1251 U8 Reseverved2; /* 22h */
1252 U8 VendorName[16]; /* 24h */
1253 U8 Reserved3; /* 34h */
1254 U8 VendorOUI[3]; /* 35h */
1255 U8 VendorPN[16]; /* 38h */
1256 U8 VendorRev[4]; /* 48h */
1257 U16 Reserved4; /* 4Ch */
1258 U8 Reserved5; /* 4Eh */
1259 U8 CC_BASE; /* 4Fh */
1260} CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
1261 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
1262 FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t;
1263
1264#define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00)
1265#define MPI_FCPORT10_BASE_ID_GBIC (0x01)
1266#define MPI_FCPORT10_BASE_ID_FIXED (0x02)
1267#define MPI_FCPORT10_BASE_ID_SFP (0x03)
1268#define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04)
1269#define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F)
1270#define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80)
1271
1272#define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00)
1273#define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01)
1274#define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02)
1275#define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03)
1276#define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04)
1277#define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05)
1278#define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06)
1279#define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07)
1280#define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80)
1281
1282#define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00)
1283#define MPI_FCPORT10_BASE_CONN_SC (0x01)
1284#define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02)
1285#define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03)
1286#define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04)
1287#define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05)
1288#define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06)
1289#define MPI_FCPORT10_BASE_CONN_LC (0x07)
1290#define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08)
1291#define MPI_FCPORT10_BASE_CONN_MU (0x09)
1292#define MPI_FCPORT10_BASE_CONN_SG (0x0A)
1293#define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B)
1294#define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C)
1295#define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F)
1296#define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20)
1297#define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21)
1298#define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22)
1299#define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F)
1300#define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80)
1301
1302#define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00)
1303#define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01)
1304#define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02)
1305#define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03)
1306#define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04)
1307
1308
1309typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA
1310{
1311 U8 Options[2]; /* 50h */
1312 U8 BitRateMax; /* 52h */
1313 U8 BitRateMin; /* 53h */
1314 U8 VendorSN[16]; /* 54h */
1315 U8 DateCode[8]; /* 64h */
1316 U8 Reserved5[3]; /* 6Ch */
1317 U8 CC_EXT; /* 6Fh */
1318} CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
1319 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
1320 FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t;
1321
1322#define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20)
1323#define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10)
1324#define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08)
1325#define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04)
1326#define MPI_FCPORT10_EXT_OPTION1_LOS (0x02)
1327
1328
1329typedef struct _CONFIG_PAGE_FC_PORT_10
1330{
1331 CONFIG_PAGE_HEADER Header; /* 00h */
1332 U8 Flags; /* 04h */
1333 U8 Reserved1; /* 05h */
1334 U16 Reserved2; /* 06h */
1335 U32 HwConfig1; /* 08h */
1336 U32 HwConfig2; /* 0Ch */
1337 CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */
1338 CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */
1339 U8 VendorSpecific[32]; /* 70h */
1340} CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10,
1341 FCPortPage10_t, MPI_POINTER pFCPortPage10_t;
1342
1343#define MPI_FCPORTPAGE10_PAGEVERSION (0x00)
1344
1345/* standard MODDEF pin definitions (from GBIC spec.) */
1346#define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007)
1347#define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001)
1348#define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002)
1349#define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004)
1350#define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007)
1351#define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006)
1352#define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005)
1353#define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004)
1354#define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003)
1355#define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002)
1356#define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001)
1357#define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000)
1358
1359#define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010)
1360#define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020)
1361
1362
1111/****************************************************************************
1112* FC Device Config Pages
1113****************************************************************************/
1114
1115typedef struct _CONFIG_PAGE_FC_DEVICE_0
1116{
1363/****************************************************************************
1364* FC Device Config Pages
1365****************************************************************************/
1366
1367typedef struct _CONFIG_PAGE_FC_DEVICE_0
1368{
1117 fCONFIG_PAGE_HEADER Header; /* 00h */
1369 CONFIG_PAGE_HEADER Header; /* 00h */
1118 U64 WWNN; /* 04h */
1119 U64 WWPN; /* 0Ch */
1120 U32 PortIdentifier; /* 14h */
1121 U8 Protocol; /* 18h */
1122 U8 Flags; /* 19h */
1123 U16 BBCredit; /* 1Ah */
1124 U16 MaxRxFrameSize; /* 1Ch */
1125 U8 Reserved1; /* 1Eh */
1126 U8 PortNumber; /* 1Fh */
1127 U8 FcPhLowestVersion; /* 20h */
1128 U8 FcPhHighestVersion; /* 21h */
1129 U8 CurrentTargetID; /* 22h */
1130 U8 CurrentBus; /* 23h */
1370 U64 WWNN; /* 04h */
1371 U64 WWPN; /* 0Ch */
1372 U32 PortIdentifier; /* 14h */
1373 U8 Protocol; /* 18h */
1374 U8 Flags; /* 19h */
1375 U16 BBCredit; /* 1Ah */
1376 U16 MaxRxFrameSize; /* 1Ch */
1377 U8 Reserved1; /* 1Eh */
1378 U8 PortNumber; /* 1Fh */
1379 U8 FcPhLowestVersion; /* 20h */
1380 U8 FcPhHighestVersion; /* 21h */
1381 U8 CurrentTargetID; /* 22h */
1382 U8 CurrentBus; /* 23h */
1131} fCONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0,
1383} CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0,
1132 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t;
1133
1134#define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x02)
1135
1136#define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01)
1384 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t;
1385
1386#define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x02)
1387
1388#define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01)
1389#define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02)
1390#define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04)
1137
1138#define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01)
1139#define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02)
1140#define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04)
1141
1142#define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK)
1143#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK)
1144#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)

--- 27 unchanged lines hidden (view full) ---

1172} RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS,
1173 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t;
1174
1175/* RAID Volume Page 0 VolumeStatus defines */
1176
1177#define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01)
1178#define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02)
1179#define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04)
1391
1392#define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01)
1393#define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02)
1394#define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04)
1395
1396#define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK)
1397#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK)
1398#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)

--- 27 unchanged lines hidden (view full) ---

1426} RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS,
1427 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t;
1428
1429/* RAID Volume Page 0 VolumeStatus defines */
1430
1431#define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01)
1432#define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02)
1433#define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04)
1434#define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08)
1180
1181#define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00)
1182#define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01)
1183#define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02)
1184
1185typedef struct _RAID_VOL0_SETTINGS
1186{
1187 U16 Settings; /* 00h */

--- 26 unchanged lines hidden (view full) ---

1214 * one and check Header.PageLength at runtime.
1215 */
1216#ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX
1217#define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1218#endif
1219
1220typedef struct _CONFIG_PAGE_RAID_VOL_0
1221{
1435
1436#define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00)
1437#define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01)
1438#define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02)
1439
1440typedef struct _RAID_VOL0_SETTINGS
1441{
1442 U16 Settings; /* 00h */

--- 26 unchanged lines hidden (view full) ---

1469 * one and check Header.PageLength at runtime.
1470 */
1471#ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX
1472#define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1473#endif
1474
1475typedef struct _CONFIG_PAGE_RAID_VOL_0
1476{
1222 fCONFIG_PAGE_HEADER Header; /* 00h */
1477 CONFIG_PAGE_HEADER Header; /* 00h */
1223 U8 VolumeID; /* 04h */
1224 U8 VolumeBus; /* 05h */
1225 U8 VolumeIOC; /* 06h */
1226 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */
1227 RAID_VOL0_STATUS VolumeStatus; /* 08h */
1228 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */
1229 U32 MaxLBA; /* 10h */
1230 U32 Reserved1; /* 14h */
1231 U32 StripeSize; /* 18h */
1232 U32 Reserved2; /* 1Ch */
1233 U32 Reserved3; /* 20h */
1234 U8 NumPhysDisks; /* 24h */
1235 U8 Reserved4; /* 25h */
1236 U16 Reserved5; /* 26h */
1237 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */
1478 U8 VolumeID; /* 04h */
1479 U8 VolumeBus; /* 05h */
1480 U8 VolumeIOC; /* 06h */
1481 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */
1482 RAID_VOL0_STATUS VolumeStatus; /* 08h */
1483 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */
1484 U32 MaxLBA; /* 10h */
1485 U32 Reserved1; /* 14h */
1486 U32 StripeSize; /* 18h */
1487 U32 Reserved2; /* 1Ch */
1488 U32 Reserved3; /* 20h */
1489 U8 NumPhysDisks; /* 24h */
1490 U8 Reserved4; /* 25h */
1491 U16 Reserved5; /* 26h */
1492 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */
1238} fCONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0,
1493} CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0,
1239 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t;
1240
1494 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t;
1495
1241#define MPI_RAIDVOLPAGE0_PAGEVERSION (0x00)
1496#define MPI_RAIDVOLPAGE0_PAGEVERSION (0x01)
1242
1243
1244/****************************************************************************
1245* RAID Physical Disk Config Pages
1246****************************************************************************/
1247
1248typedef struct _RAID_PHYS_DISK0_ERROR_DATA
1249{

--- 46 unchanged lines hidden (view full) ---

1296#define MPI_PHYSDISK0_STATUS_FAILED (0x03)
1297#define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04)
1298#define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05)
1299#define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06)
1300#define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF)
1301
1302typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0
1303{
1497
1498
1499/****************************************************************************
1500* RAID Physical Disk Config Pages
1501****************************************************************************/
1502
1503typedef struct _RAID_PHYS_DISK0_ERROR_DATA
1504{

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1551#define MPI_PHYSDISK0_STATUS_FAILED (0x03)
1552#define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04)
1553#define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05)
1554#define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06)
1555#define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF)
1556
1557typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0
1558{
1304 fCONFIG_PAGE_HEADER Header; /* 00h */
1559 CONFIG_PAGE_HEADER Header; /* 00h */
1305 U8 PhysDiskID; /* 04h */
1306 U8 PhysDiskBus; /* 05h */
1307 U8 PhysDiskIOC; /* 06h */
1308 U8 PhysDiskNum; /* 07h */
1309 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */
1310 U32 Reserved1; /* 0Ch */
1311 U32 Reserved2; /* 10h */
1312 U32 Reserved3; /* 14h */
1313 U8 DiskIdentifier[16]; /* 18h */
1314 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */
1315 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */
1316 U32 MaxLBA; /* 68h */
1317 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */
1560 U8 PhysDiskID; /* 04h */
1561 U8 PhysDiskBus; /* 05h */
1562 U8 PhysDiskIOC; /* 06h */
1563 U8 PhysDiskNum; /* 07h */
1564 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */
1565 U32 Reserved1; /* 0Ch */
1566 U32 Reserved2; /* 10h */
1567 U32 Reserved3; /* 14h */
1568 U8 DiskIdentifier[16]; /* 18h */
1569 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */
1570 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */
1571 U32 MaxLBA; /* 68h */
1572 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */
1318} fCONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0,
1573} CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0,
1319 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t;
1320
1321#define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x00)
1322
1323
1324/****************************************************************************
1325* LAN Config Pages
1326****************************************************************************/
1327
1328typedef struct _CONFIG_PAGE_LAN_0
1329{
1330 ConfigPageHeader_t Header; /* 00h */
1331 U16 TxRxModes; /* 04h */
1332 U16 Reserved; /* 06h */
1333 U32 PacketPrePad; /* 08h */
1574 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t;
1575
1576#define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x00)
1577
1578
1579/****************************************************************************
1580* LAN Config Pages
1581****************************************************************************/
1582
1583typedef struct _CONFIG_PAGE_LAN_0
1584{
1585 ConfigPageHeader_t Header; /* 00h */
1586 U16 TxRxModes; /* 04h */
1587 U16 Reserved; /* 06h */
1588 U32 PacketPrePad; /* 08h */
1334} fCONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0,
1589} CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0,
1335 LANPage0_t, MPI_POINTER pLANPage0_t;
1336
1337#define MPI_LAN_PAGE0_PAGEVERSION (0x01)
1338
1339#define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000)
1340#define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001)
1341#define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001)
1342

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1351 U32 HardwareAddressLow; /* 10h */
1352 U32 HardwareAddressHigh; /* 14h */
1353 U32 MaxWireSpeedLow; /* 18h */
1354 U32 MaxWireSpeedHigh; /* 1Ch */
1355 U32 BucketsRemaining; /* 20h */
1356 U32 MaxReplySize; /* 24h */
1357 U32 NegWireSpeedLow; /* 28h */
1358 U32 NegWireSpeedHigh; /* 2Ch */
1590 LANPage0_t, MPI_POINTER pLANPage0_t;
1591
1592#define MPI_LAN_PAGE0_PAGEVERSION (0x01)
1593
1594#define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000)
1595#define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001)
1596#define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001)
1597

--- 8 unchanged lines hidden (view full) ---

1606 U32 HardwareAddressLow; /* 10h */
1607 U32 HardwareAddressHigh; /* 14h */
1608 U32 MaxWireSpeedLow; /* 18h */
1609 U32 MaxWireSpeedHigh; /* 1Ch */
1610 U32 BucketsRemaining; /* 20h */
1611 U32 MaxReplySize; /* 24h */
1612 U32 NegWireSpeedLow; /* 28h */
1613 U32 NegWireSpeedHigh; /* 2Ch */
1359} fCONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1,
1614} CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1,
1360 LANPage1_t, MPI_POINTER pLANPage1_t;
1361
1362#define MPI_LAN_PAGE1_PAGEVERSION (0x03)
1363
1364#define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00)
1365#define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01)
1366
1367#endif
1368
1615 LANPage1_t, MPI_POINTER pLANPage1_t;
1616
1617#define MPI_LAN_PAGE1_PAGEVERSION (0x03)
1618
1619#define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00)
1620#define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01)
1621
1622#endif
1623