| mlxreg.h (138090) | mlxreg.h (240608) |
|---|---|
| 1/*- 2 * Copyright (c) 1999 Michael Smith 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 1999 Michael Smith 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/dev/mlx/mlxreg.h 138090 2004-11-25 12:15:49Z scottl $ | 26 * $FreeBSD: head/sys/dev/mlx/mlxreg.h 240608 2012-09-17 15:27:30Z jhb $ |
| 27 */ 28 29#define MLX_BLKSIZE 512 /* fixed feature */ 30#define MLX_PAGE_SIZE 4096 /* controller, not cpu, attribute */ 31 32/* 33 * Selected command codes. 34 */ --- 38 unchanged lines hidden (view full) --- 73#define MLX_V3_STATUS 0x0e 74#define MLX_V3_IDBR 0x40 75#define MLX_V3_ODBR 0x41 76#define MLX_V3_IER 0x43 77#define MLX_V3_FWERROR 0x3f 78#define MLX_V3_FWERROR_PARAM1 0x00 79#define MLX_V3_FWERROR_PARAM2 0x01 80 | 27 */ 28 29#define MLX_BLKSIZE 512 /* fixed feature */ 30#define MLX_PAGE_SIZE 4096 /* controller, not cpu, attribute */ 31 32/* 33 * Selected command codes. 34 */ --- 38 unchanged lines hidden (view full) --- 73#define MLX_V3_STATUS 0x0e 74#define MLX_V3_IDBR 0x40 75#define MLX_V3_ODBR 0x41 76#define MLX_V3_IER 0x43 77#define MLX_V3_FWERROR 0x3f 78#define MLX_V3_FWERROR_PARAM1 0x00 79#define MLX_V3_FWERROR_PARAM2 0x01 80 |
| 81#define MLX_V3_PUT_MAILBOX(sc, idx, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_MAILBOX + idx, val) 82#define MLX_V3_GET_STATUS_IDENT(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_STATUS_IDENT) 83#define MLX_V3_GET_STATUS(sc) bus_space_read_2 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_STATUS) 84#define MLX_V3_GET_IDBR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_IDBR) 85#define MLX_V3_PUT_IDBR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_IDBR, val) 86#define MLX_V3_GET_ODBR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_ODBR) 87#define MLX_V3_PUT_ODBR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_ODBR, val) 88#define MLX_V3_PUT_IER(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_IER, val) 89#define MLX_V3_GET_FWERROR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_FWERROR) 90#define MLX_V3_PUT_FWERROR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V3_FWERROR, val) 91#define MLX_V3_GET_FWERROR_PARAM1(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_FWERROR_PARAM1) 92#define MLX_V3_GET_FWERROR_PARAM2(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V3_FWERROR_PARAM2) | 81#define MLX_V3_PUT_MAILBOX(sc, idx, val) bus_write_1(sc->mlx_mem, MLX_V3_MAILBOX + idx, val) 82#define MLX_V3_GET_STATUS_IDENT(sc) bus_read_1 (sc->mlx_mem, MLX_V3_STATUS_IDENT) 83#define MLX_V3_GET_STATUS(sc) bus_read_2 (sc->mlx_mem, MLX_V3_STATUS) 84#define MLX_V3_GET_IDBR(sc) bus_read_1 (sc->mlx_mem, MLX_V3_IDBR) 85#define MLX_V3_PUT_IDBR(sc, val) bus_write_1(sc->mlx_mem, MLX_V3_IDBR, val) 86#define MLX_V3_GET_ODBR(sc) bus_read_1 (sc->mlx_mem, MLX_V3_ODBR) 87#define MLX_V3_PUT_ODBR(sc, val) bus_write_1(sc->mlx_mem, MLX_V3_ODBR, val) 88#define MLX_V3_PUT_IER(sc, val) bus_write_1(sc->mlx_mem, MLX_V3_IER, val) 89#define MLX_V3_GET_FWERROR(sc) bus_read_1 (sc->mlx_mem, MLX_V3_FWERROR) 90#define MLX_V3_PUT_FWERROR(sc, val) bus_write_1(sc->mlx_mem, MLX_V3_FWERROR, val) 91#define MLX_V3_GET_FWERROR_PARAM1(sc) bus_read_1 (sc->mlx_mem, MLX_V3_FWERROR_PARAM1) 92#define MLX_V3_GET_FWERROR_PARAM2(sc) bus_read_1 (sc->mlx_mem, MLX_V3_FWERROR_PARAM2) |
| 93 94#define MLX_V3_IDB_FULL (1<<0) /* mailbox is full */ 95#define MLX_V3_IDB_INIT_BUSY (1<<1) /* initialisation in progress */ 96 97#define MLX_V3_IDB_SACK (1<<1) /* acknowledge status read */ 98 99#define MLX_V3_ODB_SAVAIL (1<<0) /* status is available */ 100 --- 9 unchanged lines hidden (view full) --- 110#define MLX_V4_IDBR 0x0020 111#define MLX_V4_ODBR 0x002c 112#define MLX_V4_IER 0x0034 113#define MLX_V4_FWERROR 0x103f 114#define MLX_V4_FWERROR_PARAM1 0x1000 115#define MLX_V4_FWERROR_PARAM2 0x1001 116 117/* use longword access? */ | 93 94#define MLX_V3_IDB_FULL (1<<0) /* mailbox is full */ 95#define MLX_V3_IDB_INIT_BUSY (1<<1) /* initialisation in progress */ 96 97#define MLX_V3_IDB_SACK (1<<1) /* acknowledge status read */ 98 99#define MLX_V3_ODB_SAVAIL (1<<0) /* status is available */ 100 --- 9 unchanged lines hidden (view full) --- 110#define MLX_V4_IDBR 0x0020 111#define MLX_V4_ODBR 0x002c 112#define MLX_V4_IER 0x0034 113#define MLX_V4_FWERROR 0x103f 114#define MLX_V4_FWERROR_PARAM1 0x1000 115#define MLX_V4_FWERROR_PARAM2 0x1001 116 117/* use longword access? */ |
| 118#define MLX_V4_PUT_MAILBOX(sc, idx, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V4_MAILBOX + idx, val) 119#define MLX_V4_GET_STATUS_IDENT(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_STATUS_IDENT) 120#define MLX_V4_GET_STATUS(sc) bus_space_read_2 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_STATUS) 121#define MLX_V4_GET_IDBR(sc) bus_space_read_4 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_IDBR) 122#define MLX_V4_PUT_IDBR(sc, val) bus_space_write_4(sc->mlx_btag, sc->mlx_bhandle, MLX_V4_IDBR, val) 123#define MLX_V4_GET_ODBR(sc) bus_space_read_4 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_ODBR) 124#define MLX_V4_PUT_ODBR(sc, val) bus_space_write_4(sc->mlx_btag, sc->mlx_bhandle, MLX_V4_ODBR, val) 125#define MLX_V4_PUT_IER(sc, val) bus_space_write_4(sc->mlx_btag, sc->mlx_bhandle, MLX_V4_IER, val) 126#define MLX_V4_GET_FWERROR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_FWERROR) 127#define MLX_V4_PUT_FWERROR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V4_FWERROR, val) 128#define MLX_V4_GET_FWERROR_PARAM1(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_FWERROR_PARAM1) 129#define MLX_V4_GET_FWERROR_PARAM2(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V4_FWERROR_PARAM2) | 118#define MLX_V4_PUT_MAILBOX(sc, idx, val) bus_write_1(sc->mlx_mem, MLX_V4_MAILBOX + idx, val) 119#define MLX_V4_GET_STATUS_IDENT(sc) bus_read_1 (sc->mlx_mem, MLX_V4_STATUS_IDENT) 120#define MLX_V4_GET_STATUS(sc) bus_read_2 (sc->mlx_mem, MLX_V4_STATUS) 121#define MLX_V4_GET_IDBR(sc) bus_read_4 (sc->mlx_mem, MLX_V4_IDBR) 122#define MLX_V4_PUT_IDBR(sc, val) bus_write_4(sc->mlx_mem, MLX_V4_IDBR, val) 123#define MLX_V4_GET_ODBR(sc) bus_read_4 (sc->mlx_mem, MLX_V4_ODBR) 124#define MLX_V4_PUT_ODBR(sc, val) bus_write_4(sc->mlx_mem, MLX_V4_ODBR, val) 125#define MLX_V4_PUT_IER(sc, val) bus_write_4(sc->mlx_mem, MLX_V4_IER, val) 126#define MLX_V4_GET_FWERROR(sc) bus_read_1 (sc->mlx_mem, MLX_V4_FWERROR) 127#define MLX_V4_PUT_FWERROR(sc, val) bus_write_1(sc->mlx_mem, MLX_V4_FWERROR, val) 128#define MLX_V4_GET_FWERROR_PARAM1(sc) bus_read_1 (sc->mlx_mem, MLX_V4_FWERROR_PARAM1) 129#define MLX_V4_GET_FWERROR_PARAM2(sc) bus_read_1 (sc->mlx_mem, MLX_V4_FWERROR_PARAM2) |
| 130 131#define MLX_V4_IDB_FULL (1<<0) /* mailbox is full */ 132#define MLX_V4_IDB_INIT_BUSY (1<<1) /* initialisation in progress */ 133 134#define MLX_V4_IDB_HWMBOX_CMD (1<<0) /* posted hardware mailbox command */ 135#define MLX_V4_IDB_SACK (1<<1) /* acknowledge status read */ 136#define MLX_V4_IDB_MEMMBOX_CMD (1<<4) /* posted memory mailbox command */ 137 --- 17 unchanged lines hidden (view full) --- 155#define MLX_V5_STATUS 0x5e 156#define MLX_V5_IDBR 0x60 157#define MLX_V5_ODBR 0x61 158#define MLX_V5_IER 0x34 159#define MLX_V5_FWERROR 0x63 160#define MLX_V5_FWERROR_PARAM1 0x50 161#define MLX_V5_FWERROR_PARAM2 0x51 162 | 130 131#define MLX_V4_IDB_FULL (1<<0) /* mailbox is full */ 132#define MLX_V4_IDB_INIT_BUSY (1<<1) /* initialisation in progress */ 133 134#define MLX_V4_IDB_HWMBOX_CMD (1<<0) /* posted hardware mailbox command */ 135#define MLX_V4_IDB_SACK (1<<1) /* acknowledge status read */ 136#define MLX_V4_IDB_MEMMBOX_CMD (1<<4) /* posted memory mailbox command */ 137 --- 17 unchanged lines hidden (view full) --- 155#define MLX_V5_STATUS 0x5e 156#define MLX_V5_IDBR 0x60 157#define MLX_V5_ODBR 0x61 158#define MLX_V5_IER 0x34 159#define MLX_V5_FWERROR 0x63 160#define MLX_V5_FWERROR_PARAM1 0x50 161#define MLX_V5_FWERROR_PARAM2 0x51 162 |
| 163#define MLX_V5_PUT_MAILBOX(sc, idx, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V5_MAILBOX + idx, val) 164#define MLX_V5_GET_STATUS_IDENT(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_STATUS_IDENT) 165#define MLX_V5_GET_STATUS(sc) bus_space_read_2 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_STATUS) 166#define MLX_V5_GET_IDBR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_IDBR) 167#define MLX_V5_PUT_IDBR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V5_IDBR, val) 168#define MLX_V5_GET_ODBR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_ODBR) 169#define MLX_V5_PUT_ODBR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V5_ODBR, val) 170#define MLX_V5_PUT_IER(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V5_IER, val) 171#define MLX_V5_GET_FWERROR(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_FWERROR) 172#define MLX_V5_PUT_FWERROR(sc, val) bus_space_write_1(sc->mlx_btag, sc->mlx_bhandle, MLX_V5_FWERROR, val) 173#define MLX_V5_GET_FWERROR_PARAM1(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_FWERROR_PARAM1) 174#define MLX_V5_GET_FWERROR_PARAM2(sc) bus_space_read_1 (sc->mlx_btag, sc->mlx_bhandle, MLX_V5_FWERROR_PARAM2) | 163#define MLX_V5_PUT_MAILBOX(sc, idx, val) bus_write_1(sc->mlx_mem, MLX_V5_MAILBOX + idx, val) 164#define MLX_V5_GET_STATUS_IDENT(sc) bus_read_1 (sc->mlx_mem, MLX_V5_STATUS_IDENT) 165#define MLX_V5_GET_STATUS(sc) bus_read_2 (sc->mlx_mem, MLX_V5_STATUS) 166#define MLX_V5_GET_IDBR(sc) bus_read_1 (sc->mlx_mem, MLX_V5_IDBR) 167#define MLX_V5_PUT_IDBR(sc, val) bus_write_1(sc->mlx_mem, MLX_V5_IDBR, val) 168#define MLX_V5_GET_ODBR(sc) bus_read_1 (sc->mlx_mem, MLX_V5_ODBR) 169#define MLX_V5_PUT_ODBR(sc, val) bus_write_1(sc->mlx_mem, MLX_V5_ODBR, val) 170#define MLX_V5_PUT_IER(sc, val) bus_write_1(sc->mlx_mem, MLX_V5_IER, val) 171#define MLX_V5_GET_FWERROR(sc) bus_read_1 (sc->mlx_mem, MLX_V5_FWERROR) 172#define MLX_V5_PUT_FWERROR(sc, val) bus_write_1(sc->mlx_mem, MLX_V5_FWERROR, val) 173#define MLX_V5_GET_FWERROR_PARAM1(sc) bus_read_1 (sc->mlx_mem, MLX_V5_FWERROR_PARAM1) 174#define MLX_V5_GET_FWERROR_PARAM2(sc) bus_read_1 (sc->mlx_mem, MLX_V5_FWERROR_PARAM2) |
| 175 176#define MLX_V5_IDB_EMPTY (1<<0) /* mailbox is empty */ 177#define MLX_V5_IDB_INIT_DONE (1<<1) /* initialisation has completed */ 178 179#define MLX_V5_IDB_HWMBOX_CMD (1<<0) /* posted hardware mailbox command */ 180#define MLX_V5_IDB_SACK (1<<1) /* acknowledge status read */ 181#define MLX_V5_IDB_RESET (1<<3) /* reset request */ 182#define MLX_V5_IDB_MEMMBOX_CMD (1<<4) /* posted memory mailbox command */ --- 439 unchanged lines hidden --- | 175 176#define MLX_V5_IDB_EMPTY (1<<0) /* mailbox is empty */ 177#define MLX_V5_IDB_INIT_DONE (1<<1) /* initialisation has completed */ 178 179#define MLX_V5_IDB_HWMBOX_CMD (1<<0) /* posted hardware mailbox command */ 180#define MLX_V5_IDB_SACK (1<<1) /* acknowledge status read */ 181#define MLX_V5_IDB_RESET (1<<3) /* reset request */ 182#define MLX_V5_IDB_MEMMBOX_CMD (1<<4) /* posted memory mailbox command */ --- 439 unchanged lines hidden --- |