1/*-
2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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29 * SUCH DAMAGE.
30 */
31
32#ifdef HAVE_KERNEL_OPTION_HEADERS
33#include "opt_device_polling.h"
34#endif
35
36#include <sys/cdefs.h>
37__FBSDID("$FreeBSD: head/sys/dev/mge/if_mge.c 213893 2010-10-15 14:52:11Z marius $");
38
39#include <sys/param.h>
40#include <sys/systm.h>
41#include <sys/endian.h>
42#include <sys/mbuf.h>
43#include <sys/lock.h>
44#include <sys/mutex.h>
45#include <sys/kernel.h>

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74#include <dev/ofw/ofw_bus_subr.h>
75
76#include <dev/mge/if_mgevar.h>
77#include <arm/mv/mvreg.h>
78#include <arm/mv/mvvar.h>
79
80#include "miibus_if.h"
81
82/* PHY registers are in the address space of the first mge unit */
83static struct mge_softc *sc_mge0 = NULL;
84
85static int mge_probe(device_t dev);
86static int mge_attach(device_t dev);
87static int mge_detach(device_t dev);
88static int mge_shutdown(device_t dev);
89static int mge_suspend(device_t dev);
90static int mge_resume(device_t dev);
91
92static int mge_miibus_readreg(device_t dev, int phy, int reg);

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630 struct ifnet *ifp;
631 uint8_t hwaddr[ETHER_ADDR_LEN];
632 int i, error, phy;
633
634 sc = device_get_softc(dev);
635 sc->dev = dev;
636 sc->node = ofw_bus_get_node(dev);
637
638 if (device_get_unit(dev) == 0)
639 sc_mge0 = sc;
640
641 /* Set chip version-dependent parameters */
642 mge_ver_params(sc);
643
644 /* Get phy address from fdt */
645 if (fdt_get_phyaddr(sc->node, &phy) != 0)
646 return (ENXIO);
647
648 /* Initialize mutexes */
649 mtx_init(&sc->transmit_lock, device_get_nameunit(dev), "mge TX lock", MTX_DEF);
650 mtx_init(&sc->receive_lock, device_get_nameunit(dev), "mge RX lock", MTX_DEF);
651
652 /* Allocate IO and IRQ resources */
653 error = bus_alloc_resources(dev, res_spec, sc->res);

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1289static int
1290mge_miibus_readreg(device_t dev, int phy, int reg)
1291{
1292 struct mge_softc *sc;
1293 uint32_t retries;
1294
1295 sc = device_get_softc(dev);
1296
1297 MGE_WRITE(sc_mge0, MGE_REG_SMI, 0x1fffffff &
1298 (MGE_SMI_READ | (reg << 21) | (phy << 16)));
1299
1300 retries = MGE_SMI_READ_RETRIES;
1301 while (--retries && !(MGE_READ(sc_mge0, MGE_REG_SMI) & MGE_SMI_READVALID))
1302 DELAY(MGE_SMI_READ_DELAY);
1303
1304 if (retries == 0)
1305 device_printf(dev, "Timeout while reading from PHY\n");
1306
1307 return (MGE_READ(sc_mge0, MGE_REG_SMI) & 0xffff);
1308}
1309
1310static int
1311mge_miibus_writereg(device_t dev, int phy, int reg, int value)
1312{
1313 struct mge_softc *sc;
1314 uint32_t retries;
1315
1316 sc = device_get_softc(dev);
1317
1318 MGE_WRITE(sc_mge0, MGE_REG_SMI, 0x1fffffff &
1319 (MGE_SMI_WRITE | (reg << 21) | (phy << 16) | (value & 0xffff)));
1320
1321 retries = MGE_SMI_WRITE_RETRIES;
1322 while (--retries && MGE_READ(sc_mge0, MGE_REG_SMI) & MGE_SMI_BUSY)
1323 DELAY(MGE_SMI_WRITE_DELAY);
1324
1325 if (retries == 0)
1326 device_printf(dev, "Timeout while writing to PHY\n");
1327 return (0);
1328}
1329
1330static int

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