1/*-
2 * Copyright (c) 2006 IronPort Systems
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
50 * SUCH DAMAGE.
51 */
52
53#ifndef _MFIREG_H
54#define _MFIREG_H
55
56#include <sys/cdefs.h>
57__FBSDID("$FreeBSD: head/sys/dev/mfi/mfireg.h 184897 2008-11-12 22:44:50Z ambrisko $");
58
59/*
60 * MegaRAID SAS MFI firmware definitions
61 *
62 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely
63 * new firmware interface from the old AMI MegaRAID one, and there is no
64 * reason why this interface should be limited to just SAS. In any case, LSI
65 * seems to also call this interface 'MFI', so that will be used here.

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84
85/*
86 * 1078 specific related register
87 */
88#define MFI_ODR0 0x9c /* outbound doorbell register0 */
89#define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */
90#define MFI_OSP0 0xb0 /* outbound scratch pad0 */
91#define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */
92#define MFI_RMI 0x2 /* reply message interrupt */
93#define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */
94#define MFI_ODC 0x4 /* outbound doorbell change interrupt */
95
96/*
97 * GEN2 specific changes
98 */
99#define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */
100#define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */

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146 MFI_DCMD_CTRL_GETINFO = 0x01010000,
147 MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201,
148 MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202,
149 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000,
150 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000,
151 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100,
152 MFI_DCMD_CTRL_EVENT_GET = 0x01040300,
153 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500,
154 MFI_DCMD_LD_GET_LIST = 0x03010000,
155 MFI_DCMD_LD_GET_INFO = 0x03020000,
156 MFI_DCMD_LD_GET_PROP = 0x03030000,
157 MFI_DCMD_LD_SET_PROP = 0x03040000,
158 MFI_DCMD_LD_DELETE = 0x03090000,
159 MFI_DCMD_CFG_READ = 0x04010000,
160 MFI_DCMD_CFG_ADD = 0x04020000,
161 MFI_DCMD_CFG_CLEAR = 0x04030000,
162 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400,
163 MFI_DCMD_CLUSTER = 0x08000000,
164 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100,
165 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200
166} mfi_dcmd_t;
167
168/* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */
169#define MFI_FLUSHCACHE_CTRL 0x01
170#define MFI_FLUSHCACHE_DISK 0x02

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240 MFI_STAT_TIME_NOT_SET,
241 MFI_STAT_WRONG_STATE,
242 MFI_STAT_LD_OFFLINE,
243 MFI_STAT_PEER_NOTIFICATION_REJECTED,
244 MFI_STAT_PEER_NOTIFICATION_FAILED,
245 MFI_STAT_RESERVATION_IN_PROGRESS,
246 MFI_STAT_I2C_ERRORS_DETECTED,
247 MFI_STAT_PCI_ERRORS_DETECTED,
248 MFI_STAT_INVALID_STATUS = 0xFF
249} mfi_status_t;
250
251typedef enum {
252 MFI_EVT_CLASS_DEBUG = -2,
253 MFI_EVT_CLASS_PROGRESS = -1,
254 MFI_EVT_CLASS_INFO = 0,
255 MFI_EVT_CLASS_WARNING = 1,

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298 MR_LD_CACHE_WRITE_BACK = 0x01,
299 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02,
300 MR_LD_CACHE_READ_AHEAD = 0x04,
301 MR_LD_CACHE_READ_ADAPTIVE = 0x08,
302 MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10,
303 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20,
304 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40
305} mfi_ld_cache;
306
307typedef enum {
308 MR_PD_CACHE_UNCHANGED = 0,
309 MR_PD_CACHE_ENABLE = 1,
310 MR_PD_CACHE_DISABLE = 2
311} mfi_pd_cache;
312
313/*
314 * Other propertities and definitions
315 */
316#define MFI_MAX_PD_CHANNELS 2
317#define MFI_MAX_LD_CHANNELS 2
318#define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS)
319#define MFI_MAX_CHANNEL_DEVS 128
320#define MFI_DEFAULT_ID -1
321#define MFI_MAX_LUN 8
322#define MFI_MAX_LD 64
323
324#define MFI_FRAME_SIZE 64
325#define MFI_MBOX_SIZE 12
326
327/* Firmware flashing can take 40s */
328#define MFI_POLL_TIMEOUT_SECS 50
329
330/* Allow for speedier math calculations */

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861 } ddf;
862 struct {
863 uint32_t reserved;
864 } non_disk;
865 uint32_t type;
866} __packed;
867
868struct mfi_pd_progress {
869 struct {
870 uint32_t rbld : 1;
871 uint32_t patrol : 1;
872 uint32_t clear : 1;
873 uint32_t reserved: 29;
874 } active;
875 struct mfi_progress rbld;
876 struct mfi_progress patrol;
877 struct mfi_progress clear;
878 struct mfi_progress reserved[4];
879} __packed;
880
881struct mfi_pd_info {
882 union mfi_pd_ref ref;
883 uint8_t inquiry_data[96];
884 uint8_t vpd_page83[64];
885 uint8_t not_supported;
886 uint8_t scsi_dev_type;
887 uint8_t connected_port_bitmap;
888 uint8_t device_speed;
889 uint32_t media_err_count;
890 uint32_t other_err_count;
891 uint32_t pred_fail_count;
892 uint32_t last_pred_fail_event_seq_num;
893 uint16_t fw_state;
894 uint8_t disable_for_removal;
895 uint8_t link_speed;
896 union mfi_pd_ddf_type state;
897 struct {
898 uint8_t count;
899 uint8_t is_path_broken;
900 uint8_t reserved[6];
901 uint64_t sas_addr[4];
902 } path_info;

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913 uint8_t reserved[512-358];
914} __packed;
915
916struct mfi_pd_address {
917 uint16_t device_id;
918 uint16_t encl_device_id;
919 uint8_t encl_index;
920 uint8_t slot_number;
921 uint8_t scsi_dev_type;
922 uint8_t connect_port_bitmap;
923 uint64_t sas_addr[2];
924} __packed;
925
926struct mfi_pd_list {
927 uint32_t size;
928 uint32_t count;
929 uint8_t data;
930 /*
931 struct mfi_pd_address addr[];
932 */
933} __packed;
934
935union mfi_ld_ref {
936 struct {
937 uint8_t target_id;
938 uint8_t reserved;
939 uint16_t seq;
940 } v;
941 uint32_t ref;
942} __packed;

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981 uint8_t primary_raid_level;
982 uint8_t raid_level_qualifier;
983 uint8_t secondary_raid_level;
984 uint8_t stripe_size;
985 uint8_t num_drives;
986 uint8_t span_depth;
987 uint8_t state;
988 uint8_t init_state;
989 uint8_t is_consistent;
990 uint8_t reserved[23];
991} __packed;
992
993struct mfi_ld_progress {
994 uint32_t active;
995#define MFI_LD_PROGRESS_CC (1<<0)
996#define MFI_LD_PROGRESS_BGI (1<<1)
997#define MFI_LD_PROGRESS_FGI (1<<2)
998#define MFI_LD_PORGRESS_RECON (1<<3)
999 struct mfi_progress cc;
1000 struct mfi_progress bgi;
1001 struct mfi_progress fgi;
1002 struct mfi_progress recon;
1003 struct mfi_progress reserved[4];
1004} __packed;
1005
1006struct mfi_span {

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1023 struct mfi_ld_progress progress;
1024 uint16_t cluster_owner;
1025 uint8_t reconstruct_active;
1026 uint8_t reserved1[1];
1027 uint8_t vpd_page83[64];
1028 uint8_t reserved2[16];
1029} __packed;
1030
1031union mfi_spare_type {
1032 struct {
1033 uint8_t is_dedicate :1;
1034 uint8_t is_revertable :1;
1035 uint8_t is_encl_affinity :1;
1036 uint8_t reserved :5;
1037 } v;
1038 uint8_t type;
1039} __packed;
1040
1041#define MAX_ARRAYS 16
1042struct mfi_spare {
1043 union mfi_pd_ref ref;
1044 union mfi_spare_type spare_type;
1045 uint8_t reserved[2];
1046 uint8_t array_count;
1047 uint16_t array_refd[MAX_ARRAYS];
1048} __packed;
1049
1050#define MAX_ROW_SIZE 32
1051struct mfi_array {
1052 uint64_t size;
1053 uint8_t num_drives;
1054 uint8_t reserved;
1055 uint16_t array_ref;
1056 uint8_t pad[20];
1057 struct {
1058 union mfi_pd_ref ref;
1059 uint16_t fw_state;
1060 struct {
1061 uint8_t pd;
1062 uint8_t slot;
1063 } encl;
1064 } pd[MAX_ROW_SIZE];
1065} __packed;
1066
1067struct mfi_config_data {
1068 uint32_t size;
1069 uint16_t array_count;
1070 uint16_t array_size;
1071 uint16_t log_drv_count;
1072 uint16_t log_drv_size;
1073 uint16_t spares_count;
1074 uint16_t spares_size;
1075 uint8_t reserved[16];
1076 uint8_t data;
1077 /*
1078 struct mfi_array array[];
1079 struct mfi_ld_config ld[];
1080 struct mfi_spare spare[];
1081 */
1082} __packed;
1083
1084#define MFI_SCSI_MAX_TARGETS 128
1085#define MFI_SCSI_MAX_LUNS 8
1086#define MFI_SCSI_INITIATOR_ID 255
1087#define MFI_SCSI_MAX_CMDS 8
1088#define MFI_SCSI_MAX_CDB_LEN 16
1089
1090#endif /* _MFIREG_H */