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ixgbe_type.h (205720) ixgbe_type.h (215911)
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 205720 2010-03-27 00:21:40Z jfv $*/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 215911 2010-11-26 22:46:32Z jfv $*/
34
35#ifndef _IXGBE_TYPE_H_
36#define _IXGBE_TYPE_H_
37
38#include "ixgbe_osdep.h"
39
40
41/* Vendor ID */

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49#define IXGBE_DEV_ID_82598AT 0x10C8
50#define IXGBE_DEV_ID_82598AT2 0x150B
51#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
52#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
53#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
54#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
55#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
56#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
34
35#ifndef _IXGBE_TYPE_H_
36#define _IXGBE_TYPE_H_
37
38#include "ixgbe_osdep.h"
39
40
41/* Vendor ID */

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49#define IXGBE_DEV_ID_82598AT 0x10C8
50#define IXGBE_DEV_ID_82598AT2 0x150B
51#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
52#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
53#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
54#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
55#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
56#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
57#define IXGBE_DEV_ID_82599_KX4 0x10F7
58#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
59#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
60#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
61#define IXGBE_DEV_ID_82599_CX4 0x10F9
62#define IXGBE_DEV_ID_82599_SFP 0x10FB
63#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
64#define IXGBE_DEV_ID_82599_T3_LOM 0x151C
57#define IXGBE_DEV_ID_82599_KX4 0x10F7
58#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
59#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
60#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
61#define IXGBE_DEV_ID_82599_CX4 0x10F9
62#define IXGBE_DEV_ID_82599_SFP 0x10FB
63#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
64#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
65#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
66#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
67#define IXGBE_DEV_ID_82599_T3_LOM 0x151C
68#define IXGBE_DEV_ID_82599_VF 0x10ED
65
66/* General Registers */
67#define IXGBE_CTRL 0x00000
68#define IXGBE_STATUS 0x00008
69#define IXGBE_CTRL_EXT 0x00018
70#define IXGBE_ESDP 0x00020
71#define IXGBE_EODSDP 0x00028
72#define IXGBE_I2CCTL 0x00028

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85#define IXGBE_EEMNGDATA 0x10114
86#define IXGBE_FLMNGCTL 0x10118
87#define IXGBE_FLMNGDATA 0x1011C
88#define IXGBE_FLMNGCNT 0x10120
89#define IXGBE_FLOP 0x1013C
90#define IXGBE_GRC 0x10200
91
92/* General Receive Control */
69
70/* General Registers */
71#define IXGBE_CTRL 0x00000
72#define IXGBE_STATUS 0x00008
73#define IXGBE_CTRL_EXT 0x00018
74#define IXGBE_ESDP 0x00020
75#define IXGBE_EODSDP 0x00028
76#define IXGBE_I2CCTL 0x00028

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89#define IXGBE_EEMNGDATA 0x10114
90#define IXGBE_FLMNGCTL 0x10118
91#define IXGBE_FLMNGDATA 0x1011C
92#define IXGBE_FLMNGCNT 0x10120
93#define IXGBE_FLOP 0x1013C
94#define IXGBE_GRC 0x10200
95
96/* General Receive Control */
93#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
94#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
97#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
98#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
95
96#define IXGBE_VPDDIAG0 0x10204
97#define IXGBE_VPDDIAG1 0x10208
98
99/* I2CCTL Bit Masks */
99
100#define IXGBE_VPDDIAG0 0x10204
101#define IXGBE_VPDDIAG1 0x10208
102
103/* I2CCTL Bit Masks */
100#define IXGBE_I2C_CLK_IN 0x00000001
101#define IXGBE_I2C_CLK_OUT 0x00000002
102#define IXGBE_I2C_DATA_IN 0x00000004
103#define IXGBE_I2C_DATA_OUT 0x00000008
104#define IXGBE_I2C_CLK_IN 0x00000001
105#define IXGBE_I2C_CLK_OUT 0x00000002
106#define IXGBE_I2C_DATA_IN 0x00000004
107#define IXGBE_I2C_DATA_OUT 0x00000008
104
105/* Interrupt Registers */
106#define IXGBE_EICR 0x00800
107#define IXGBE_EICS 0x00808
108#define IXGBE_EIMS 0x00880
109#define IXGBE_EIMC 0x00888
110#define IXGBE_EIAC 0x00810
111#define IXGBE_EIAM 0x00890
108
109/* Interrupt Registers */
110#define IXGBE_EICR 0x00800
111#define IXGBE_EICS 0x00808
112#define IXGBE_EIMS 0x00880
113#define IXGBE_EIMC 0x00888
114#define IXGBE_EIAC 0x00810
115#define IXGBE_EIAM 0x00890
112#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
113#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
114#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
115#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
116#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
117#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
118#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
119#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
116/* 82599 EITR is only 12 bits, with the lower 3 always zero */
117/*
118 * 82598 EITR is 16 bits but set the limits based on the max
119 * supported by all ixgbe hardware
120 */
120/* 82599 EITR is only 12 bits, with the lower 3 always zero */
121/*
122 * 82598 EITR is 16 bits but set the limits based on the max
123 * supported by all ixgbe hardware
124 */
121#define IXGBE_MAX_INT_RATE 488281
122#define IXGBE_MIN_INT_RATE 956
123#define IXGBE_MAX_EITR 0x00000FF8
124#define IXGBE_MIN_EITR 8
125#define IXGBE_MAX_INT_RATE 488281
126#define IXGBE_MIN_INT_RATE 956
127#define IXGBE_MAX_EITR 0x00000FF8
128#define IXGBE_MIN_EITR 8
125#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
126 (0x012300 + (((_i) - 24) * 4)))
127#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
128#define IXGBE_EITR_LLI_MOD 0x00008000
129#define IXGBE_EITR_CNT_WDIS 0x80000000
130#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
131#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
132#define IXGBE_EITRSEL 0x00894

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226#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
227#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */
228#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
229#define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */
230#define IXGBE_RQTC 0x0EC70
231#define IXGBE_MTQC 0x08120
232#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */
233#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */
129#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
130 (0x012300 + (((_i) - 24) * 4)))
131#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
132#define IXGBE_EITR_LLI_MOD 0x00008000
133#define IXGBE_EITR_CNT_WDIS 0x80000000
134#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
135#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
136#define IXGBE_EITRSEL 0x00894

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230#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
231#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */
232#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
233#define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */
234#define IXGBE_RQTC 0x0EC70
235#define IXGBE_MTQC 0x08120
236#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */
237#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */
238#define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */
234#define IXGBE_VT_CTL 0x051B0
235#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
236#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
239#define IXGBE_VT_CTL 0x051B0
240#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
241#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
242#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
237#define IXGBE_QDE 0x2F04
238#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
239#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
240#define IXGBE_VMRCTL(_i) (0x0F600 + ((_i) * 4))
241#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
242#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
243#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
244#define IXGBE_LLITHRESH 0x0EC90

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283#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
284#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
285#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
286#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
287#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
288#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
289#define IXGBE_DTXCTL 0x07E00
290
243#define IXGBE_QDE 0x2F04
244#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
245#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
246#define IXGBE_VMRCTL(_i) (0x0F600 + ((_i) * 4))
247#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
248#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
249#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
250#define IXGBE_LLITHRESH 0x0EC90

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289#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
290#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
291#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
292#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
293#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
294#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
295#define IXGBE_DTXCTL 0x07E00
296
291#define IXGBE_DMATXCTL 0x04A80
292#define IXGBE_PFDTXGSWC 0x08220
293#define IXGBE_DTXMXSZRQ 0x08100
294#define IXGBE_DTXTCPFLGL 0x04A88
295#define IXGBE_DTXTCPFLGH 0x04A8C
296#define IXGBE_LBDRPEN 0x0CA00
297#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
297#define IXGBE_DMATXCTL 0x04A80
298#define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
299#define IXGBE_PFDTXGSWC 0x08220
300#define IXGBE_DTXMXSZRQ 0x08100
301#define IXGBE_DTXTCPFLGL 0x04A88
302#define IXGBE_DTXTCPFLGH 0x04A8C
303#define IXGBE_LBDRPEN 0x0CA00
304#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
298
299#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
300#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
301#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
302#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
303
304#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
305
306#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
307#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
308#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
309#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
310
311#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
312
313/* Anti-spoofing defines */
314#define IXGBE_SPOOF_MACAS_MASK 0xFF
315#define IXGBE_SPOOF_VLANAS_MASK 0xFF00
316#define IXGBE_SPOOF_VLANAS_SHIFT 8
317#define IXGBE_PFVFSPOOF_REG_COUNT 8
305#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
306/* Tx DCA Control register : 128 of these (0-127) */
307#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
308#define IXGBE_TIPG 0x0CB00
309#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
310#define IXGBE_MNGTXMAP 0x0CD10
311#define IXGBE_TIPG_FIBER_DEFAULT 3
312#define IXGBE_TXPBSIZE_SHIFT 10

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647#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
648 (0x08600 + ((_i) * 4)))
649#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
650
651#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
652#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
653#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
654#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
318#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
319/* Tx DCA Control register : 128 of these (0-127) */
320#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
321#define IXGBE_TIPG 0x0CB00
322#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
323#define IXGBE_MNGTXMAP 0x0CD10
324#define IXGBE_TIPG_FIBER_DEFAULT 3
325#define IXGBE_TXPBSIZE_SHIFT 10

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660#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
661 (0x08600 + ((_i) * 4)))
662#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
663
664#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
665#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
666#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
667#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
668#define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
669#define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */
655#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
656#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
657#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
658#define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */
659#define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */
660#define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */
661#define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */
662#define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */

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1014#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
1015#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
1016#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
1017#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
1018#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
1019
1020#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */
1021#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */
670#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
671#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
672#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
673#define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */
674#define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */
675#define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */
676#define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */
677#define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */

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1029#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
1030#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
1031#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
1032#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
1033#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
1034
1035#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */
1036#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */
1037#define IXGBE_MDIO_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */
1038#define IXGBE_MDIO_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */
1022#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */
1023#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */
1024#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/
1025#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/
1026#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */
1027#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */
1028#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */
1029#define IXGBE_MDIO_PHY_SPEED_100M 0x0020 /* 100M capable */

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1394#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
1395#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
1396#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
1397
1398/* VLAN pool filtering masks */
1399#define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */
1400#define IXGBE_VLVF_ENTRIES 64
1401#define IXGBE_VLVF_VLANID_MASK 0x00000FFF
1039#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */
1040#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */
1041#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/
1042#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/
1043#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */
1044#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */
1045#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */
1046#define IXGBE_MDIO_PHY_SPEED_100M 0x0020 /* 100M capable */

--- 364 unchanged lines hidden (view full) ---

1411#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
1412#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
1413#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
1414
1415/* VLAN pool filtering masks */
1416#define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */
1417#define IXGBE_VLVF_ENTRIES 64
1418#define IXGBE_VLVF_VLANID_MASK 0x00000FFF
1419/* Per VF Port VLAN insertion rules */
1420#define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
1421#define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
1402
1403#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
1404
1405/* STATUS Bit Masks */
1406#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
1407#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
1408#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
1409

--- 128 unchanged lines hidden (view full) ---

1538#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
1539#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
1540#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
1541
1542/* ANLP1 Bit Masks */
1543#define IXGBE_ANLP1_PAUSE 0x0C00
1544#define IXGBE_ANLP1_SYM_PAUSE 0x0400
1545#define IXGBE_ANLP1_ASM_PAUSE 0x0800
1422
1423#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
1424
1425/* STATUS Bit Masks */
1426#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
1427#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
1428#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
1429

--- 128 unchanged lines hidden (view full) ---

1558#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
1559#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
1560#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
1561
1562/* ANLP1 Bit Masks */
1563#define IXGBE_ANLP1_PAUSE 0x0C00
1564#define IXGBE_ANLP1_SYM_PAUSE 0x0400
1565#define IXGBE_ANLP1_ASM_PAUSE 0x0800
1566#define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000
1546
1547/* SW Semaphore Register bitmasks */
1548#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1549#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1550#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
1551#define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
1552
1553/* SW_FW_SYNC/GSSR definitions */

--- 12 unchanged lines hidden (view full) ---

1566#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */
1567#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */
1568#define IXGBE_EEC_FWE_SHIFT 4
1569#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */
1570#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */
1571#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
1572#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
1573#define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */
1567
1568/* SW Semaphore Register bitmasks */
1569#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1570#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1571#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
1572#define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
1573
1574/* SW_FW_SYNC/GSSR definitions */

--- 12 unchanged lines hidden (view full) ---

1587#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */
1588#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */
1589#define IXGBE_EEC_FWE_SHIFT 4
1590#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */
1591#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */
1592#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
1593#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
1594#define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */
1595#define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */
1574#define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */
1575/* EEPROM Addressing bits based on type (0-small, 1-large) */
1576#define IXGBE_EEC_ADDR_SIZE 0x00000400
1577#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
1578
1579#define IXGBE_EEC_SIZE_SHIFT 11
1580#define IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT 6
1581#define IXGBE_EEPROM_OPCODE_BITS 8
1582
1596#define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */
1597/* EEPROM Addressing bits based on type (0-small, 1-large) */
1598#define IXGBE_EEC_ADDR_SIZE 0x00000400
1599#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
1600
1601#define IXGBE_EEC_SIZE_SHIFT 11
1602#define IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT 6
1603#define IXGBE_EEPROM_OPCODE_BITS 8
1604
1605/* Part Number String Length */
1606#define IXGBE_PBANUM_LENGTH 11
1607
1583/* Checksum and EEPROM pointers */
1608/* Checksum and EEPROM pointers */
1609#define IXGBE_PBANUM_PTR_GUARD 0xFAFA
1584#define IXGBE_EEPROM_CHECKSUM 0x3F
1585#define IXGBE_EEPROM_SUM 0xBABA
1586#define IXGBE_PCIE_ANALOG_PTR 0x03
1587#define IXGBE_ATLAS0_CONFIG_PTR 0x04
1588#define IXGBE_PHY_PTR 0x04
1589#define IXGBE_ATLAS1_CONFIG_PTR 0x05
1590#define IXGBE_OPTION_ROM_PTR 0x05
1591#define IXGBE_PCIE_GENERAL_PTR 0x06

--- 63 unchanged lines hidden (view full) ---

1655#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */
1656#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */
1657
1658#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
1659#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
1660#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
1661#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
1662#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
1610#define IXGBE_EEPROM_CHECKSUM 0x3F
1611#define IXGBE_EEPROM_SUM 0xBABA
1612#define IXGBE_PCIE_ANALOG_PTR 0x03
1613#define IXGBE_ATLAS0_CONFIG_PTR 0x04
1614#define IXGBE_PHY_PTR 0x04
1615#define IXGBE_ATLAS1_CONFIG_PTR 0x05
1616#define IXGBE_OPTION_ROM_PTR 0x05
1617#define IXGBE_PCIE_GENERAL_PTR 0x06

--- 63 unchanged lines hidden (view full) ---

1681#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */
1682#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */
1683
1684#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
1685#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
1686#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
1687#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
1688#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
1663#define IXGBE_FW_PATCH_VERSION_4 0x7
1689#define IXGBE_FW_PATCH_VERSION_4 0x7
1690#define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */
1691#define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */
1692#define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */
1693#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */
1694#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */
1664#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */
1695#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */
1665#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */
1666#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
1667#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
1668#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */
1669#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */
1670#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */
1671#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */
1696#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */
1697#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
1698#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
1699#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */
1700#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */
1701#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */
1702#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */
1672
1673/* PCI Bus Info */
1674#define IXGBE_PCI_DEVICE_STATUS 0xAA
1675#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020
1676#define IXGBE_PCI_LINK_STATUS 0xB2
1677#define IXGBE_PCI_DEVICE_CONTROL2 0xC8
1678#define IXGBE_PCI_LINK_WIDTH 0x3F0
1679#define IXGBE_PCI_LINK_WIDTH_1 0x10

--- 376 unchanged lines hidden (view full) ---

2056#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060
2057#define IXGBE_FDIRCMD_IPV6 0x00000080
2058#define IXGBE_FDIRCMD_CLEARHT 0x00000100
2059#define IXGBE_FDIRCMD_DROP 0x00000200
2060#define IXGBE_FDIRCMD_INT 0x00000400
2061#define IXGBE_FDIRCMD_LAST 0x00000800
2062#define IXGBE_FDIRCMD_COLLISION 0x00001000
2063#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000
1703
1704/* PCI Bus Info */
1705#define IXGBE_PCI_DEVICE_STATUS 0xAA
1706#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020
1707#define IXGBE_PCI_LINK_STATUS 0xB2
1708#define IXGBE_PCI_DEVICE_CONTROL2 0xC8
1709#define IXGBE_PCI_LINK_WIDTH 0x3F0
1710#define IXGBE_PCI_LINK_WIDTH_1 0x10

--- 376 unchanged lines hidden (view full) ---

2087#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060
2088#define IXGBE_FDIRCMD_IPV6 0x00000080
2089#define IXGBE_FDIRCMD_CLEARHT 0x00000100
2090#define IXGBE_FDIRCMD_DROP 0x00000200
2091#define IXGBE_FDIRCMD_INT 0x00000400
2092#define IXGBE_FDIRCMD_LAST 0x00000800
2093#define IXGBE_FDIRCMD_COLLISION 0x00001000
2094#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000
2095#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5
2064#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16
2065#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24
2066#define IXGBE_FDIR_INIT_DONE_POLL 10
2067#define IXGBE_FDIRCMD_CMD_POLL 10
2068
2069/* Transmit Descriptor - Legacy */
2070struct ixgbe_legacy_tx_desc {
2071 u64 buffer_addr; /* Address of the descriptor's data buffer */

--- 161 unchanged lines hidden (view full) ---

2233#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
2234#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
2235#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
2236#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
2237#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
2238#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
2239#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
2240
2096#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16
2097#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24
2098#define IXGBE_FDIR_INIT_DONE_POLL 10
2099#define IXGBE_FDIRCMD_CMD_POLL 10
2100
2101/* Transmit Descriptor - Legacy */
2102struct ixgbe_legacy_tx_desc {
2103 u64 buffer_addr; /* Address of the descriptor's data buffer */

--- 161 unchanged lines hidden (view full) ---

2265#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
2266#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
2267#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
2268#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
2269#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
2270#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
2271#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
2272
2273/* Flow Control Macros */
2274#define PAUSE_RTT 8
2275#define PAUSE_MTU(MTU) ((MTU + 1024 - 1) / 1024)
2241
2276
2277#define FC_HIGH_WATER(MTU) ((((PAUSE_RTT + PAUSE_MTU(MTU)) * 144) + 99) / 100 +\
2278 PAUSE_MTU(MTU))
2279#define FC_LOW_WATER(MTU) (2 * (2 * PAUSE_MTU(MTU) + PAUSE_RTT))
2280
2242/* Software ATR hash keys */
2281/* Software ATR hash keys */
2243#define IXGBE_ATR_BUCKET_HASH_KEY 0xE214AD3D
2244#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x14364D17
2282#define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
2283#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
2245
2284
2246/* Software ATR input stream offsets and masks */
2247#define IXGBE_ATR_VLAN_OFFSET 0
2248#define IXGBE_ATR_SRC_IPV6_OFFSET 2
2249#define IXGBE_ATR_SRC_IPV4_OFFSET 14
2250#define IXGBE_ATR_DST_IPV6_OFFSET 18
2251#define IXGBE_ATR_DST_IPV4_OFFSET 30
2252#define IXGBE_ATR_SRC_PORT_OFFSET 34
2253#define IXGBE_ATR_DST_PORT_OFFSET 36
2254#define IXGBE_ATR_FLEX_BYTE_OFFSET 38
2255#define IXGBE_ATR_VM_POOL_OFFSET 40
2256#define IXGBE_ATR_L4TYPE_OFFSET 41
2257
2285/* Software ATR input stream values and masks */
2286#define IXGBE_ATR_HASH_MASK 0x7fff
2258#define IXGBE_ATR_L4TYPE_MASK 0x3
2287#define IXGBE_ATR_L4TYPE_MASK 0x3
2259#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
2260#define IXGBE_ATR_L4TYPE_UDP 0x1
2261#define IXGBE_ATR_L4TYPE_TCP 0x2
2262#define IXGBE_ATR_L4TYPE_SCTP 0x3
2288#define IXGBE_ATR_L4TYPE_UDP 0x1
2289#define IXGBE_ATR_L4TYPE_TCP 0x2
2290#define IXGBE_ATR_L4TYPE_SCTP 0x3
2263#define IXGBE_ATR_HASH_MASK 0x7fff
2291#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
2292enum ixgbe_atr_flow_type {
2293 IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0,
2294 IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1,
2295 IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2,
2296 IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
2297 IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4,
2298 IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5,
2299 IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6,
2300 IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
2301};
2264
2265/* Flow Director ATR input struct. */
2302
2303/* Flow Director ATR input struct. */
2266struct ixgbe_atr_input {
2304union ixgbe_atr_input {
2267 /* Byte layout in order, all values with MSB first:
2268 *
2305 /* Byte layout in order, all values with MSB first:
2306 *
2307 * rsvd0 - 2 bytes - space reserved must be 0.
2269 * vlan_id - 2 bytes
2270 * src_ip - 16 bytes
2271 * dst_ip - 16 bytes
2272 * src_port - 2 bytes
2273 * dst_port - 2 bytes
2274 * flex_bytes - 2 bytes
2275 * vm_pool - 1 byte
2308 * vlan_id - 2 bytes
2309 * src_ip - 16 bytes
2310 * dst_ip - 16 bytes
2311 * src_port - 2 bytes
2312 * dst_port - 2 bytes
2313 * flex_bytes - 2 bytes
2314 * vm_pool - 1 byte
2276 * l4type - 1 byte
2315 * flow_type - 1 byte
2277 */
2316 */
2278 u8 byte_stream[42];
2317 struct {
2318 __be16 rsvd0;
2319 __be16 vlan_id;
2320 __be32 dst_ip[4];
2321 __be32 src_ip[4];
2322 __be16 src_port;
2323 __be16 dst_port;
2324 __be16 flex_bytes;
2325 u8 vm_pool;
2326 u8 flow_type;
2327 } formatted;
2328 __be32 dword_stream[11];
2279};
2280
2281struct ixgbe_atr_input_masks {
2329};
2330
2331struct ixgbe_atr_input_masks {
2282 u32 src_ip_mask;
2283 u32 dst_ip_mask;
2284 u16 src_port_mask;
2285 u16 dst_port_mask;
2286 u16 vlan_id_mask;
2287 u16 data_mask;
2332 __be16 rsvd0;
2333 __be16 vlan_id_mask;
2334 __be32 dst_ip_mask[4];
2335 __be32 src_ip_mask[4];
2336 __be16 src_port_mask;
2337 __be16 dst_port_mask;
2338 __be16 flex_mask;
2288};
2289
2339};
2340
2341/*
2342 * Unavailable: The FCoE Boot Option ROM is not present in the flash.
2343 * Disabled: Present; boot order is not set for any targets on the port.
2344 * Enabled: Present; boot order is set for at least one target on the port.
2345 */
2346enum ixgbe_fcoe_boot_status {
2347 ixgbe_fcoe_bootstatus_disabled = 0,
2348 ixgbe_fcoe_bootstatus_enabled = 1,
2349 ixgbe_fcoe_bootstatus_unavailable = 0xFFFF
2350};
2351
2290enum ixgbe_eeprom_type {
2291 ixgbe_eeprom_uninitialized = 0,
2292 ixgbe_eeprom_spi,
2293 ixgbe_flash,
2294 ixgbe_eeprom_none /* No NVM support */
2295};
2296
2297enum ixgbe_mac_type {
2298 ixgbe_mac_unknown = 0,
2299 ixgbe_mac_82598EB,
2300 ixgbe_mac_82599EB,
2352enum ixgbe_eeprom_type {
2353 ixgbe_eeprom_uninitialized = 0,
2354 ixgbe_eeprom_spi,
2355 ixgbe_flash,
2356 ixgbe_eeprom_none /* No NVM support */
2357};
2358
2359enum ixgbe_mac_type {
2360 ixgbe_mac_unknown = 0,
2361 ixgbe_mac_82598EB,
2362 ixgbe_mac_82599EB,
2363 ixgbe_mac_82599_vf,
2301 ixgbe_num_macs
2302};
2303
2304enum ixgbe_phy_type {
2305 ixgbe_phy_unknown = 0,
2306 ixgbe_phy_none,
2307 ixgbe_phy_tn,
2308 ixgbe_phy_aq,

--- 31 unchanged lines hidden (view full) ---

2340 ixgbe_sfp_type_sr = 1,
2341 ixgbe_sfp_type_lr = 2,
2342 ixgbe_sfp_type_da_cu_core0 = 3,
2343 ixgbe_sfp_type_da_cu_core1 = 4,
2344 ixgbe_sfp_type_srlr_core0 = 5,
2345 ixgbe_sfp_type_srlr_core1 = 6,
2346 ixgbe_sfp_type_da_act_lmt_core0 = 7,
2347 ixgbe_sfp_type_da_act_lmt_core1 = 8,
2364 ixgbe_num_macs
2365};
2366
2367enum ixgbe_phy_type {
2368 ixgbe_phy_unknown = 0,
2369 ixgbe_phy_none,
2370 ixgbe_phy_tn,
2371 ixgbe_phy_aq,

--- 31 unchanged lines hidden (view full) ---

2403 ixgbe_sfp_type_sr = 1,
2404 ixgbe_sfp_type_lr = 2,
2405 ixgbe_sfp_type_da_cu_core0 = 3,
2406 ixgbe_sfp_type_da_cu_core1 = 4,
2407 ixgbe_sfp_type_srlr_core0 = 5,
2408 ixgbe_sfp_type_srlr_core1 = 6,
2409 ixgbe_sfp_type_da_act_lmt_core0 = 7,
2410 ixgbe_sfp_type_da_act_lmt_core1 = 8,
2411 ixgbe_sfp_type_1g_cu_core0 = 9,
2412 ixgbe_sfp_type_1g_cu_core1 = 10,
2348 ixgbe_sfp_type_not_present = 0xFFFE,
2349 ixgbe_sfp_type_unknown = 0xFFFF
2350};
2351
2352enum ixgbe_media_type {
2353 ixgbe_media_type_unknown = 0,
2354 ixgbe_media_type_fiber,
2355 ixgbe_media_type_copper,

--- 130 unchanged lines hidden (view full) ---

2486 u64 ptc127;
2487 u64 ptc255;
2488 u64 ptc511;
2489 u64 ptc1023;
2490 u64 ptc1522;
2491 u64 mptc;
2492 u64 bptc;
2493 u64 xec;
2413 ixgbe_sfp_type_not_present = 0xFFFE,
2414 ixgbe_sfp_type_unknown = 0xFFFF
2415};
2416
2417enum ixgbe_media_type {
2418 ixgbe_media_type_unknown = 0,
2419 ixgbe_media_type_fiber,
2420 ixgbe_media_type_copper,

--- 130 unchanged lines hidden (view full) ---

2551 u64 ptc127;
2552 u64 ptc255;
2553 u64 ptc511;
2554 u64 ptc1023;
2555 u64 ptc1522;
2556 u64 mptc;
2557 u64 bptc;
2558 u64 xec;
2494 u64 rqsmr[16];
2495 u64 tqsmr[8];
2496 u64 qprc[16];
2497 u64 qptc[16];
2498 u64 qbrc[16];
2499 u64 qbtc[16];
2500 u64 qprdc[16];
2501 u64 pxon2offc[8];
2502 u64 fdirustat_add;
2503 u64 fdirustat_remove;

--- 35 unchanged lines hidden (view full) ---

2539 void (*enable_relaxed_ordering)(struct ixgbe_hw *);
2540 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
2541 u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
2542 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
2543 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
2544 s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *);
2545 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
2546 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
2559 u64 qprc[16];
2560 u64 qptc[16];
2561 u64 qbrc[16];
2562 u64 qbtc[16];
2563 u64 qprdc[16];
2564 u64 pxon2offc[8];
2565 u64 fdirustat_add;
2566 u64 fdirustat_remove;

--- 35 unchanged lines hidden (view full) ---

2602 void (*enable_relaxed_ordering)(struct ixgbe_hw *);
2603 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
2604 u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
2605 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
2606 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
2607 s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *);
2608 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
2609 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
2610 s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *);
2547 s32 (*stop_adapter)(struct ixgbe_hw *);
2548 s32 (*get_bus_info)(struct ixgbe_hw *);
2549 void (*set_lan_id)(struct ixgbe_hw *);
2550 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
2551 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
2552 s32 (*setup_sfp)(struct ixgbe_hw *);
2553 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
2554 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
2555 void (*release_swfw_sync)(struct ixgbe_hw *, u16);
2556
2557 /* Link */
2611 s32 (*stop_adapter)(struct ixgbe_hw *);
2612 s32 (*get_bus_info)(struct ixgbe_hw *);
2613 void (*set_lan_id)(struct ixgbe_hw *);
2614 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
2615 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
2616 s32 (*setup_sfp)(struct ixgbe_hw *);
2617 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
2618 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
2619 void (*release_swfw_sync)(struct ixgbe_hw *, u16);
2620
2621 /* Link */
2622 void (*disable_tx_laser)(struct ixgbe_hw *);
2623 void (*enable_tx_laser)(struct ixgbe_hw *);
2624 void (*flap_tx_laser)(struct ixgbe_hw *);
2558 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);
2559 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
2560 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
2561 bool *);
2562
2563 /* LED */
2564 s32 (*led_on)(struct ixgbe_hw *, u32);
2565 s32 (*led_off)(struct ixgbe_hw *, u32);

--- 11 unchanged lines hidden (view full) ---

2577 ixgbe_mc_addr_itr);
2578 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
2579 ixgbe_mc_addr_itr);
2580 s32 (*enable_mc)(struct ixgbe_hw *);
2581 s32 (*disable_mc)(struct ixgbe_hw *);
2582 s32 (*clear_vfta)(struct ixgbe_hw *);
2583 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
2584 s32 (*init_uta_tables)(struct ixgbe_hw *);
2625 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);
2626 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
2627 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
2628 bool *);
2629
2630 /* LED */
2631 s32 (*led_on)(struct ixgbe_hw *, u32);
2632 s32 (*led_off)(struct ixgbe_hw *, u32);

--- 11 unchanged lines hidden (view full) ---

2644 ixgbe_mc_addr_itr);
2645 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
2646 ixgbe_mc_addr_itr);
2647 s32 (*enable_mc)(struct ixgbe_hw *);
2648 s32 (*disable_mc)(struct ixgbe_hw *);
2649 s32 (*clear_vfta)(struct ixgbe_hw *);
2650 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
2651 s32 (*init_uta_tables)(struct ixgbe_hw *);
2652 void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
2653 void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
2585
2586 /* Flow Control */
2587 s32 (*fc_enable)(struct ixgbe_hw *, s32);
2588};
2589
2590struct ixgbe_phy_operations {
2591 s32 (*identify)(struct ixgbe_hw *);
2592 s32 (*identify_sfp)(struct ixgbe_hw *);

--- 7 unchanged lines hidden (view full) ---

2600 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
2601 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
2602 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
2603 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
2604 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
2605 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
2606 void (*i2c_bus_clear)(struct ixgbe_hw *);
2607 s32 (*check_overtemp)(struct ixgbe_hw *);
2654
2655 /* Flow Control */
2656 s32 (*fc_enable)(struct ixgbe_hw *, s32);
2657};
2658
2659struct ixgbe_phy_operations {
2660 s32 (*identify)(struct ixgbe_hw *);
2661 s32 (*identify_sfp)(struct ixgbe_hw *);

--- 7 unchanged lines hidden (view full) ---

2669 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
2670 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
2671 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
2672 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
2673 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
2674 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
2675 void (*i2c_bus_clear)(struct ixgbe_hw *);
2676 s32 (*check_overtemp)(struct ixgbe_hw *);
2608 s32 (*set_low_power_state)(struct ixgbe_hw *);
2609};
2610
2611struct ixgbe_eeprom_info {
2612 struct ixgbe_eeprom_operations ops;
2613 enum ixgbe_eeprom_type type;
2614 u32 semaphore_delay;
2615 u16 word_size;
2616 u16 address_bits;

--- 5 unchanged lines hidden (view full) ---

2622 enum ixgbe_mac_type type;
2623 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2624 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2625 u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2626 /* prefix for World Wide Node Name (WWNN) */
2627 u16 wwnn_prefix;
2628 /* prefix for World Wide Port Name (WWPN) */
2629 u16 wwpn_prefix;
2677};
2678
2679struct ixgbe_eeprom_info {
2680 struct ixgbe_eeprom_operations ops;
2681 enum ixgbe_eeprom_type type;
2682 u32 semaphore_delay;
2683 u16 word_size;
2684 u16 address_bits;

--- 5 unchanged lines hidden (view full) ---

2690 enum ixgbe_mac_type type;
2691 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2692 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2693 u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2694 /* prefix for World Wide Node Name (WWNN) */
2695 u16 wwnn_prefix;
2696 /* prefix for World Wide Port Name (WWPN) */
2697 u16 wwpn_prefix;
2698#define IXGBE_MAX_MTA 128
2699 u32 mta_shadow[IXGBE_MAX_MTA];
2630 s32 mc_filter_type;
2631 u32 mcft_size;
2632 u32 vft_size;
2633 u32 num_rar_entries;
2634 u32 rar_highwater;
2700 s32 mc_filter_type;
2701 u32 mcft_size;
2702 u32 vft_size;
2703 u32 num_rar_entries;
2704 u32 rar_highwater;
2705 u32 rx_pb_size;
2635 u32 max_tx_queues;
2636 u32 max_rx_queues;
2637 u32 max_msix_vectors;
2638 bool msix_vectors_from_pcie;
2639 u32 orig_autoc;
2640 u32 orig_autoc2;
2641 bool orig_link_settings_stored;
2642 bool autotry_restart;

--- 9 unchanged lines hidden (view full) ---

2652 bool sfp_setup_needed;
2653 u32 revision;
2654 enum ixgbe_media_type media_type;
2655 bool reset_disable;
2656 ixgbe_autoneg_advertised autoneg_advertised;
2657 enum ixgbe_smart_speed smart_speed;
2658 bool smart_speed_active;
2659 bool multispeed_fiber;
2706 u32 max_tx_queues;
2707 u32 max_rx_queues;
2708 u32 max_msix_vectors;
2709 bool msix_vectors_from_pcie;
2710 u32 orig_autoc;
2711 u32 orig_autoc2;
2712 bool orig_link_settings_stored;
2713 bool autotry_restart;

--- 9 unchanged lines hidden (view full) ---

2723 bool sfp_setup_needed;
2724 u32 revision;
2725 enum ixgbe_media_type media_type;
2726 bool reset_disable;
2727 ixgbe_autoneg_advertised autoneg_advertised;
2728 enum ixgbe_smart_speed smart_speed;
2729 bool smart_speed_active;
2730 bool multispeed_fiber;
2731 bool reset_if_overtemp;
2660};
2661
2732};
2733
2734#include "ixgbe_mbx.h"
2735
2736struct ixgbe_mbx_operations {
2737 void (*init_params)(struct ixgbe_hw *hw);
2738 s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16);
2739 s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);
2740 s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16);
2741 s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
2742 s32 (*check_for_msg)(struct ixgbe_hw *, u16);
2743 s32 (*check_for_ack)(struct ixgbe_hw *, u16);
2744 s32 (*check_for_rst)(struct ixgbe_hw *, u16);
2745};
2746
2747struct ixgbe_mbx_stats {
2748 u32 msgs_tx;
2749 u32 msgs_rx;
2750
2751 u32 acks;
2752 u32 reqs;
2753 u32 rsts;
2754};
2755
2756struct ixgbe_mbx_info {
2757 struct ixgbe_mbx_operations ops;
2758 struct ixgbe_mbx_stats stats;
2759 u32 timeout;
2760 u32 usec_delay;
2761 u32 v2p_mailbox;
2762 u16 size;
2763};
2764
2662struct ixgbe_hw {
2663 u8 *hw_addr;
2664 void *back;
2665 struct ixgbe_mac_info mac;
2666 struct ixgbe_addr_filter_info addr_ctrl;
2667 struct ixgbe_fc_info fc;
2668 struct ixgbe_phy_info phy;
2669 struct ixgbe_eeprom_info eeprom;
2670 struct ixgbe_bus_info bus;
2765struct ixgbe_hw {
2766 u8 *hw_addr;
2767 void *back;
2768 struct ixgbe_mac_info mac;
2769 struct ixgbe_addr_filter_info addr_ctrl;
2770 struct ixgbe_fc_info fc;
2771 struct ixgbe_phy_info phy;
2772 struct ixgbe_eeprom_info eeprom;
2773 struct ixgbe_bus_info bus;
2774 struct ixgbe_mbx_info mbx;
2671 u16 device_id;
2672 u16 vendor_id;
2673 u16 subsystem_device_id;
2674 u16 subsystem_vendor_id;
2675 u8 revision_id;
2676 bool adapter_stopped;
2677};
2678

--- 24 unchanged lines hidden (view full) ---

2703#define IXGBE_ERR_SFP_NOT_SUPPORTED -19
2704#define IXGBE_ERR_SFP_NOT_PRESENT -20
2705#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
2706#define IXGBE_ERR_NO_SAN_ADDR_PTR -22
2707#define IXGBE_ERR_FDIR_REINIT_FAILED -23
2708#define IXGBE_ERR_EEPROM_VERSION -24
2709#define IXGBE_ERR_NO_SPACE -25
2710#define IXGBE_ERR_OVERTEMP -26
2775 u16 device_id;
2776 u16 vendor_id;
2777 u16 subsystem_device_id;
2778 u16 subsystem_vendor_id;
2779 u8 revision_id;
2780 bool adapter_stopped;
2781};
2782

--- 24 unchanged lines hidden (view full) ---

2807#define IXGBE_ERR_SFP_NOT_SUPPORTED -19
2808#define IXGBE_ERR_SFP_NOT_PRESENT -20
2809#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
2810#define IXGBE_ERR_NO_SAN_ADDR_PTR -22
2811#define IXGBE_ERR_FDIR_REINIT_FAILED -23
2812#define IXGBE_ERR_EEPROM_VERSION -24
2813#define IXGBE_ERR_NO_SPACE -25
2814#define IXGBE_ERR_OVERTEMP -26
2815#define IXGBE_ERR_FC_NOT_NEGOTIATED -27
2816#define IXGBE_ERR_FC_NOT_SUPPORTED -28
2817#define IXGBE_ERR_FLOW_CONTROL -29
2818#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
2819#define IXGBE_ERR_PBA_SECTION -31
2820#define IXGBE_ERR_INVALID_ARGUMENT -32
2711#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
2712
2713
2714#endif /* _IXGBE_TYPE_H_ */
2821#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
2822
2823
2824#endif /* _IXGBE_TYPE_H_ */