33c33
< /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 205720 2010-03-27 00:21:40Z jfv $*/
---
> /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 215911 2010-11-26 22:46:32Z jfv $*/
57,64c57,68
< #define IXGBE_DEV_ID_82599_KX4 0x10F7
< #define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
< #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
< #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
< #define IXGBE_DEV_ID_82599_CX4 0x10F9
< #define IXGBE_DEV_ID_82599_SFP 0x10FB
< #define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
< #define IXGBE_DEV_ID_82599_T3_LOM 0x151C
---
> #define IXGBE_DEV_ID_82599_KX4 0x10F7
> #define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
> #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
> #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
> #define IXGBE_DEV_ID_82599_CX4 0x10F9
> #define IXGBE_DEV_ID_82599_SFP 0x10FB
> #define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
> #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
> #define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
> #define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
> #define IXGBE_DEV_ID_82599_T3_LOM 0x151C
> #define IXGBE_DEV_ID_82599_VF 0x10ED
93,94c97,98
< #define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
< #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
---
> #define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
> #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
100,103c104,107
< #define IXGBE_I2C_CLK_IN 0x00000001
< #define IXGBE_I2C_CLK_OUT 0x00000002
< #define IXGBE_I2C_DATA_IN 0x00000004
< #define IXGBE_I2C_DATA_OUT 0x00000008
---
> #define IXGBE_I2C_CLK_IN 0x00000001
> #define IXGBE_I2C_CLK_OUT 0x00000002
> #define IXGBE_I2C_DATA_IN 0x00000004
> #define IXGBE_I2C_DATA_OUT 0x00000008
112,115c116,119
< #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
< #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
< #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
< #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
---
> #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
> #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
> #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
> #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
121,124c125,128
< #define IXGBE_MAX_INT_RATE 488281
< #define IXGBE_MIN_INT_RATE 956
< #define IXGBE_MAX_EITR 0x00000FF8
< #define IXGBE_MIN_EITR 8
---
> #define IXGBE_MAX_INT_RATE 488281
> #define IXGBE_MIN_INT_RATE 956
> #define IXGBE_MAX_EITR 0x00000FF8
> #define IXGBE_MIN_EITR 8
233a238
> #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */
236a242
> #define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
291,297c297,304
< #define IXGBE_DMATXCTL 0x04A80
< #define IXGBE_PFDTXGSWC 0x08220
< #define IXGBE_DTXMXSZRQ 0x08100
< #define IXGBE_DTXTCPFLGL 0x04A88
< #define IXGBE_DTXTCPFLGH 0x04A8C
< #define IXGBE_LBDRPEN 0x0CA00
< #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
---
> #define IXGBE_DMATXCTL 0x04A80
> #define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
> #define IXGBE_PFDTXGSWC 0x08220
> #define IXGBE_DTXMXSZRQ 0x08100
> #define IXGBE_DTXTCPFLGL 0x04A88
> #define IXGBE_DTXTCPFLGH 0x04A8C
> #define IXGBE_LBDRPEN 0x0CA00
> #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
304a312,317
>
> /* Anti-spoofing defines */
> #define IXGBE_SPOOF_MACAS_MASK 0xFF
> #define IXGBE_SPOOF_VLANAS_MASK 0xFF00
> #define IXGBE_SPOOF_VLANAS_SHIFT 8
> #define IXGBE_PFVFSPOOF_REG_COUNT 8
654a668,669
> #define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
> #define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */
1021a1037,1038
> #define IXGBE_MDIO_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */
> #define IXGBE_MDIO_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */
1401a1419,1421
> /* Per VF Port VLAN insertion rules */
> #define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
> #define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
1545a1566
> #define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000
1573a1595
> #define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */
1582a1605,1607
> /* Part Number String Length */
> #define IXGBE_PBANUM_LENGTH 11
>
1583a1609
> #define IXGBE_PBANUM_PTR_GUARD 0xFAFA
1663c1689,1694
< #define IXGBE_FW_PATCH_VERSION_4 0x7
---
> #define IXGBE_FW_PATCH_VERSION_4 0x7
> #define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */
> #define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */
> #define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */
> #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */
> #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */
1665,1671c1696,1702
< #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */
< #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
< #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
< #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */
< #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */
< #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */
< #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */
---
> #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */
> #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
> #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
> #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */
> #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */
> #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */
> #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */
2063a2095
> #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5
2240a2273,2275
> /* Flow Control Macros */
> #define PAUSE_RTT 8
> #define PAUSE_MTU(MTU) ((MTU + 1024 - 1) / 1024)
2241a2277,2280
> #define FC_HIGH_WATER(MTU) ((((PAUSE_RTT + PAUSE_MTU(MTU)) * 144) + 99) / 100 +\
> PAUSE_MTU(MTU))
> #define FC_LOW_WATER(MTU) (2 * (2 * PAUSE_MTU(MTU) + PAUSE_RTT))
>
2243,2244c2282,2283
< #define IXGBE_ATR_BUCKET_HASH_KEY 0xE214AD3D
< #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x14364D17
---
> #define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
> #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
2246,2257c2285,2286
< /* Software ATR input stream offsets and masks */
< #define IXGBE_ATR_VLAN_OFFSET 0
< #define IXGBE_ATR_SRC_IPV6_OFFSET 2
< #define IXGBE_ATR_SRC_IPV4_OFFSET 14
< #define IXGBE_ATR_DST_IPV6_OFFSET 18
< #define IXGBE_ATR_DST_IPV4_OFFSET 30
< #define IXGBE_ATR_SRC_PORT_OFFSET 34
< #define IXGBE_ATR_DST_PORT_OFFSET 36
< #define IXGBE_ATR_FLEX_BYTE_OFFSET 38
< #define IXGBE_ATR_VM_POOL_OFFSET 40
< #define IXGBE_ATR_L4TYPE_OFFSET 41
<
---
> /* Software ATR input stream values and masks */
> #define IXGBE_ATR_HASH_MASK 0x7fff
2259d2287
< #define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
2263c2291,2301
< #define IXGBE_ATR_HASH_MASK 0x7fff
---
> #define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
> enum ixgbe_atr_flow_type {
> IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0,
> IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1,
> IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2,
> IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
> IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4,
> IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5,
> IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6,
> IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
> };
2266c2304
< struct ixgbe_atr_input {
---
> union ixgbe_atr_input {
2268a2307
> * rsvd0 - 2 bytes - space reserved must be 0.
2276c2315
< * l4type - 1 byte
---
> * flow_type - 1 byte
2278c2317,2328
< u8 byte_stream[42];
---
> struct {
> __be16 rsvd0;
> __be16 vlan_id;
> __be32 dst_ip[4];
> __be32 src_ip[4];
> __be16 src_port;
> __be16 dst_port;
> __be16 flex_bytes;
> u8 vm_pool;
> u8 flow_type;
> } formatted;
> __be32 dword_stream[11];
2282,2287c2332,2338
< u32 src_ip_mask;
< u32 dst_ip_mask;
< u16 src_port_mask;
< u16 dst_port_mask;
< u16 vlan_id_mask;
< u16 data_mask;
---
> __be16 rsvd0;
> __be16 vlan_id_mask;
> __be32 dst_ip_mask[4];
> __be32 src_ip_mask[4];
> __be16 src_port_mask;
> __be16 dst_port_mask;
> __be16 flex_mask;
2289a2341,2351
> /*
> * Unavailable: The FCoE Boot Option ROM is not present in the flash.
> * Disabled: Present; boot order is not set for any targets on the port.
> * Enabled: Present; boot order is set for at least one target on the port.
> */
> enum ixgbe_fcoe_boot_status {
> ixgbe_fcoe_bootstatus_disabled = 0,
> ixgbe_fcoe_bootstatus_enabled = 1,
> ixgbe_fcoe_bootstatus_unavailable = 0xFFFF
> };
>
2300a2363
> ixgbe_mac_82599_vf,
2347a2411,2412
> ixgbe_sfp_type_1g_cu_core0 = 9,
> ixgbe_sfp_type_1g_cu_core1 = 10,
2494,2495d2558
< u64 rqsmr[16];
< u64 tqsmr[8];
2546a2610
> s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *);
2557a2622,2624
> void (*disable_tx_laser)(struct ixgbe_hw *);
> void (*enable_tx_laser)(struct ixgbe_hw *);
> void (*flap_tx_laser)(struct ixgbe_hw *);
2584a2652,2653
> void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
> void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
2608d2676
< s32 (*set_low_power_state)(struct ixgbe_hw *);
2629a2698,2699
> #define IXGBE_MAX_MTA 128
> u32 mta_shadow[IXGBE_MAX_MTA];
2634a2705
> u32 rx_pb_size;
2659a2731
> bool reset_if_overtemp;
2661a2734,2764
> #include "ixgbe_mbx.h"
>
> struct ixgbe_mbx_operations {
> void (*init_params)(struct ixgbe_hw *hw);
> s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16);
> s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);
> s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16);
> s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
> s32 (*check_for_msg)(struct ixgbe_hw *, u16);
> s32 (*check_for_ack)(struct ixgbe_hw *, u16);
> s32 (*check_for_rst)(struct ixgbe_hw *, u16);
> };
>
> struct ixgbe_mbx_stats {
> u32 msgs_tx;
> u32 msgs_rx;
>
> u32 acks;
> u32 reqs;
> u32 rsts;
> };
>
> struct ixgbe_mbx_info {
> struct ixgbe_mbx_operations ops;
> struct ixgbe_mbx_stats stats;
> u32 timeout;
> u32 usec_delay;
> u32 v2p_mailbox;
> u16 size;
> };
>
2670a2774
> struct ixgbe_mbx_info mbx;
2710a2815,2820
> #define IXGBE_ERR_FC_NOT_NEGOTIATED -27
> #define IXGBE_ERR_FC_NOT_SUPPORTED -28
> #define IXGBE_ERR_FLOW_CONTROL -29
> #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
> #define IXGBE_ERR_PBA_SECTION -31
> #define IXGBE_ERR_INVALID_ARGUMENT -32
< /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 205720 2010-03-27 00:21:40Z jfv $*/
---
> /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 215911 2010-11-26 22:46:32Z jfv $*/
57,64c57,68
< #define IXGBE_DEV_ID_82599_KX4 0x10F7
< #define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
< #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
< #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
< #define IXGBE_DEV_ID_82599_CX4 0x10F9
< #define IXGBE_DEV_ID_82599_SFP 0x10FB
< #define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
< #define IXGBE_DEV_ID_82599_T3_LOM 0x151C
---
> #define IXGBE_DEV_ID_82599_KX4 0x10F7
> #define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
> #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
> #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
> #define IXGBE_DEV_ID_82599_CX4 0x10F9
> #define IXGBE_DEV_ID_82599_SFP 0x10FB
> #define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
> #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
> #define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
> #define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
> #define IXGBE_DEV_ID_82599_T3_LOM 0x151C
> #define IXGBE_DEV_ID_82599_VF 0x10ED
93,94c97,98
< #define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
< #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
---
> #define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
> #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
100,103c104,107
< #define IXGBE_I2C_CLK_IN 0x00000001
< #define IXGBE_I2C_CLK_OUT 0x00000002
< #define IXGBE_I2C_DATA_IN 0x00000004
< #define IXGBE_I2C_DATA_OUT 0x00000008
---
> #define IXGBE_I2C_CLK_IN 0x00000001
> #define IXGBE_I2C_CLK_OUT 0x00000002
> #define IXGBE_I2C_DATA_IN 0x00000004
> #define IXGBE_I2C_DATA_OUT 0x00000008
112,115c116,119
< #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
< #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
< #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
< #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
---
> #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
> #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
> #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
> #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
121,124c125,128
< #define IXGBE_MAX_INT_RATE 488281
< #define IXGBE_MIN_INT_RATE 956
< #define IXGBE_MAX_EITR 0x00000FF8
< #define IXGBE_MIN_EITR 8
---
> #define IXGBE_MAX_INT_RATE 488281
> #define IXGBE_MIN_INT_RATE 956
> #define IXGBE_MAX_EITR 0x00000FF8
> #define IXGBE_MIN_EITR 8
233a238
> #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */
236a242
> #define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
291,297c297,304
< #define IXGBE_DMATXCTL 0x04A80
< #define IXGBE_PFDTXGSWC 0x08220
< #define IXGBE_DTXMXSZRQ 0x08100
< #define IXGBE_DTXTCPFLGL 0x04A88
< #define IXGBE_DTXTCPFLGH 0x04A8C
< #define IXGBE_LBDRPEN 0x0CA00
< #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
---
> #define IXGBE_DMATXCTL 0x04A80
> #define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
> #define IXGBE_PFDTXGSWC 0x08220
> #define IXGBE_DTXMXSZRQ 0x08100
> #define IXGBE_DTXTCPFLGL 0x04A88
> #define IXGBE_DTXTCPFLGH 0x04A8C
> #define IXGBE_LBDRPEN 0x0CA00
> #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
304a312,317
>
> /* Anti-spoofing defines */
> #define IXGBE_SPOOF_MACAS_MASK 0xFF
> #define IXGBE_SPOOF_VLANAS_MASK 0xFF00
> #define IXGBE_SPOOF_VLANAS_SHIFT 8
> #define IXGBE_PFVFSPOOF_REG_COUNT 8
654a668,669
> #define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
> #define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */
1021a1037,1038
> #define IXGBE_MDIO_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */
> #define IXGBE_MDIO_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */
1401a1419,1421
> /* Per VF Port VLAN insertion rules */
> #define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
> #define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
1545a1566
> #define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000
1573a1595
> #define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */
1582a1605,1607
> /* Part Number String Length */
> #define IXGBE_PBANUM_LENGTH 11
>
1583a1609
> #define IXGBE_PBANUM_PTR_GUARD 0xFAFA
1663c1689,1694
< #define IXGBE_FW_PATCH_VERSION_4 0x7
---
> #define IXGBE_FW_PATCH_VERSION_4 0x7
> #define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */
> #define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */
> #define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */
> #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */
> #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */
1665,1671c1696,1702
< #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */
< #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
< #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
< #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */
< #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */
< #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */
< #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */
---
> #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */
> #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
> #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
> #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */
> #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */
> #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */
> #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */
2063a2095
> #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5
2240a2273,2275
> /* Flow Control Macros */
> #define PAUSE_RTT 8
> #define PAUSE_MTU(MTU) ((MTU + 1024 - 1) / 1024)
2241a2277,2280
> #define FC_HIGH_WATER(MTU) ((((PAUSE_RTT + PAUSE_MTU(MTU)) * 144) + 99) / 100 +\
> PAUSE_MTU(MTU))
> #define FC_LOW_WATER(MTU) (2 * (2 * PAUSE_MTU(MTU) + PAUSE_RTT))
>
2243,2244c2282,2283
< #define IXGBE_ATR_BUCKET_HASH_KEY 0xE214AD3D
< #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x14364D17
---
> #define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
> #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
2246,2257c2285,2286
< /* Software ATR input stream offsets and masks */
< #define IXGBE_ATR_VLAN_OFFSET 0
< #define IXGBE_ATR_SRC_IPV6_OFFSET 2
< #define IXGBE_ATR_SRC_IPV4_OFFSET 14
< #define IXGBE_ATR_DST_IPV6_OFFSET 18
< #define IXGBE_ATR_DST_IPV4_OFFSET 30
< #define IXGBE_ATR_SRC_PORT_OFFSET 34
< #define IXGBE_ATR_DST_PORT_OFFSET 36
< #define IXGBE_ATR_FLEX_BYTE_OFFSET 38
< #define IXGBE_ATR_VM_POOL_OFFSET 40
< #define IXGBE_ATR_L4TYPE_OFFSET 41
<
---
> /* Software ATR input stream values and masks */
> #define IXGBE_ATR_HASH_MASK 0x7fff
2259d2287
< #define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
2263c2291,2301
< #define IXGBE_ATR_HASH_MASK 0x7fff
---
> #define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
> enum ixgbe_atr_flow_type {
> IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0,
> IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1,
> IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2,
> IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
> IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4,
> IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5,
> IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6,
> IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
> };
2266c2304
< struct ixgbe_atr_input {
---
> union ixgbe_atr_input {
2268a2307
> * rsvd0 - 2 bytes - space reserved must be 0.
2276c2315
< * l4type - 1 byte
---
> * flow_type - 1 byte
2278c2317,2328
< u8 byte_stream[42];
---
> struct {
> __be16 rsvd0;
> __be16 vlan_id;
> __be32 dst_ip[4];
> __be32 src_ip[4];
> __be16 src_port;
> __be16 dst_port;
> __be16 flex_bytes;
> u8 vm_pool;
> u8 flow_type;
> } formatted;
> __be32 dword_stream[11];
2282,2287c2332,2338
< u32 src_ip_mask;
< u32 dst_ip_mask;
< u16 src_port_mask;
< u16 dst_port_mask;
< u16 vlan_id_mask;
< u16 data_mask;
---
> __be16 rsvd0;
> __be16 vlan_id_mask;
> __be32 dst_ip_mask[4];
> __be32 src_ip_mask[4];
> __be16 src_port_mask;
> __be16 dst_port_mask;
> __be16 flex_mask;
2289a2341,2351
> /*
> * Unavailable: The FCoE Boot Option ROM is not present in the flash.
> * Disabled: Present; boot order is not set for any targets on the port.
> * Enabled: Present; boot order is set for at least one target on the port.
> */
> enum ixgbe_fcoe_boot_status {
> ixgbe_fcoe_bootstatus_disabled = 0,
> ixgbe_fcoe_bootstatus_enabled = 1,
> ixgbe_fcoe_bootstatus_unavailable = 0xFFFF
> };
>
2300a2363
> ixgbe_mac_82599_vf,
2347a2411,2412
> ixgbe_sfp_type_1g_cu_core0 = 9,
> ixgbe_sfp_type_1g_cu_core1 = 10,
2494,2495d2558
< u64 rqsmr[16];
< u64 tqsmr[8];
2546a2610
> s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *);
2557a2622,2624
> void (*disable_tx_laser)(struct ixgbe_hw *);
> void (*enable_tx_laser)(struct ixgbe_hw *);
> void (*flap_tx_laser)(struct ixgbe_hw *);
2584a2652,2653
> void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
> void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
2608d2676
< s32 (*set_low_power_state)(struct ixgbe_hw *);
2629a2698,2699
> #define IXGBE_MAX_MTA 128
> u32 mta_shadow[IXGBE_MAX_MTA];
2634a2705
> u32 rx_pb_size;
2659a2731
> bool reset_if_overtemp;
2661a2734,2764
> #include "ixgbe_mbx.h"
>
> struct ixgbe_mbx_operations {
> void (*init_params)(struct ixgbe_hw *hw);
> s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16);
> s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);
> s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16);
> s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
> s32 (*check_for_msg)(struct ixgbe_hw *, u16);
> s32 (*check_for_ack)(struct ixgbe_hw *, u16);
> s32 (*check_for_rst)(struct ixgbe_hw *, u16);
> };
>
> struct ixgbe_mbx_stats {
> u32 msgs_tx;
> u32 msgs_rx;
>
> u32 acks;
> u32 reqs;
> u32 rsts;
> };
>
> struct ixgbe_mbx_info {
> struct ixgbe_mbx_operations ops;
> struct ixgbe_mbx_stats stats;
> u32 timeout;
> u32 usec_delay;
> u32 v2p_mailbox;
> u16 size;
> };
>
2670a2774
> struct ixgbe_mbx_info mbx;
2710a2815,2820
> #define IXGBE_ERR_FC_NOT_NEGOTIATED -27
> #define IXGBE_ERR_FC_NOT_SUPPORTED -28
> #define IXGBE_ERR_FLOW_CONTROL -29
> #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
> #define IXGBE_ERR_PBA_SECTION -31
> #define IXGBE_ERR_INVALID_ARGUMENT -32