4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
| 4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
|
39#include "ixgbe_type.h"
40
41/* DCB defines */
42/* DCB credit calculation defines */
43#define IXGBE_DCB_CREDIT_QUANTUM 64
44#define IXGBE_DCB_MAX_CREDIT_REFILL 200 /* 200 * 64B = 12800B */
45#define IXGBE_DCB_MAX_TSO_SIZE (32 * 1024) /* Max TSO pkt size in DCB*/
46#define IXGBE_DCB_MAX_CREDIT (2 * IXGBE_DCB_MAX_CREDIT_REFILL)
47
48/* 513 for 32KB TSO packet */
49#define IXGBE_DCB_MIN_TSO_CREDIT \
50 ((IXGBE_DCB_MAX_TSO_SIZE / IXGBE_DCB_CREDIT_QUANTUM) + 1)
51
52/* DCB configuration defines */
53#define IXGBE_DCB_MAX_USER_PRIORITY 8
54#define IXGBE_DCB_MAX_BW_GROUP 8
55#define IXGBE_DCB_BW_PERCENT 100
56
57#define IXGBE_DCB_TX_CONFIG 0
58#define IXGBE_DCB_RX_CONFIG 1
59
60/* DCB capability defines */
61#define IXGBE_DCB_PG_SUPPORT 0x00000001
62#define IXGBE_DCB_PFC_SUPPORT 0x00000002
63#define IXGBE_DCB_BCN_SUPPORT 0x00000004
64#define IXGBE_DCB_UP2TC_SUPPORT 0x00000008
65#define IXGBE_DCB_GSP_SUPPORT 0x00000010
66
67struct ixgbe_dcb_support {
68 u32 capabilities; /* DCB capabilities */
69
70 /* Each bit represents a number of TCs configurable in the hw.
71 * If 8 traffic classes can be configured, the value is 0x80. */
72 u8 traffic_classes;
73 u8 pfc_traffic_classes;
74};
75
76enum ixgbe_dcb_tsa {
77 ixgbe_dcb_tsa_ets = 0,
78 ixgbe_dcb_tsa_group_strict_cee,
79 ixgbe_dcb_tsa_strict
80};
81
82/* Traffic class bandwidth allocation per direction */
83struct ixgbe_dcb_tc_path {
84 u8 bwg_id; /* Bandwidth Group (BWG) ID */
85 u8 bwg_percent; /* % of BWG's bandwidth */
86 u8 link_percent; /* % of link bandwidth */
87 u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */
88 u16 data_credits_refill; /* Credit refill amount in 64B granularity */
89 u16 data_credits_max; /* Max credits for a configured packet buffer
90 * in 64B granularity.*/
91 enum ixgbe_dcb_tsa tsa; /* Link or Group Strict Priority */
92};
93
94enum ixgbe_dcb_pfc {
95 ixgbe_dcb_pfc_disabled = 0,
96 ixgbe_dcb_pfc_enabled,
97 ixgbe_dcb_pfc_enabled_txonly,
98 ixgbe_dcb_pfc_enabled_rxonly
99};
100
101/* Traffic class configuration */
102struct ixgbe_dcb_tc_config {
103 struct ixgbe_dcb_tc_path path[2]; /* One each for Tx/Rx */
104 enum ixgbe_dcb_pfc pfc; /* Class based flow control setting */
105
106 u16 desc_credits_max; /* For Tx Descriptor arbitration */
107 u8 tc; /* Traffic class (TC) */
108};
109
110enum ixgbe_dcb_pba {
111 /* PBA[0-7] each use 64KB FIFO */
112 ixgbe_dcb_pba_equal = PBA_STRATEGY_EQUAL,
113 /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */
114 ixgbe_dcb_pba_80_48 = PBA_STRATEGY_WEIGHTED
115};
116
117struct ixgbe_dcb_num_tcs {
118 u8 pg_tcs;
119 u8 pfc_tcs;
120};
121
122struct ixgbe_dcb_config {
123 struct ixgbe_dcb_tc_config tc_config[IXGBE_DCB_MAX_TRAFFIC_CLASS];
124 struct ixgbe_dcb_support support;
125 struct ixgbe_dcb_num_tcs num_tcs;
126 u8 bw_percentage[2][IXGBE_DCB_MAX_BW_GROUP]; /* One each for Tx/Rx */
127 bool pfc_mode_enable;
128 bool round_robin_enable;
129
130 enum ixgbe_dcb_pba rx_pba_cfg;
131
132 u32 dcb_cfg_version; /* Not used...OS-specific? */
133 u32 link_speed; /* For bandwidth allocation validation purpose */
134 bool vt_mode;
135};
136
137/* DCB driver APIs */
138
139/* DCB rule checking */
140s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *);
141
142/* DCB credits calculation */
143s32 ixgbe_dcb_calculate_tc_credits(u8 *, u16 *, u16 *, int);
144s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *,
145 struct ixgbe_dcb_config *, u32, u8);
146
147/* DCB PFC */
148s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *, u8, u8 *);
149s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *);
150
151/* DCB stats */
152s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *);
153s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);
154s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);
155
156/* DCB config arbiters */
157s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *,
158 struct ixgbe_dcb_config *);
159s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *,
160 struct ixgbe_dcb_config *);
161s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *,
162 struct ixgbe_dcb_config *);
163
164/* DCB unpack routines */
165void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *, u8 *, u8 *);
166void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *, int, u16 *);
167void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *, u16 *);
168void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *, int, u8 *);
169void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *, int, u8 *);
170void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *, int, u8 *);
171u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *, int, u8);
172
173/* DCB initialization */
174s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, u16 *, u16 *, u8 *, u8 *, u8 *);
175s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *);
176#endif /* _IXGBE_DCB_H_ */
| 38#include "ixgbe_type.h"
39
40/* DCB defines */
41/* DCB credit calculation defines */
42#define IXGBE_DCB_CREDIT_QUANTUM 64
43#define IXGBE_DCB_MAX_CREDIT_REFILL 200 /* 200 * 64B = 12800B */
44#define IXGBE_DCB_MAX_TSO_SIZE (32 * 1024) /* Max TSO pkt size in DCB*/
45#define IXGBE_DCB_MAX_CREDIT (2 * IXGBE_DCB_MAX_CREDIT_REFILL)
46
47/* 513 for 32KB TSO packet */
48#define IXGBE_DCB_MIN_TSO_CREDIT \
49 ((IXGBE_DCB_MAX_TSO_SIZE / IXGBE_DCB_CREDIT_QUANTUM) + 1)
50
51/* DCB configuration defines */
52#define IXGBE_DCB_MAX_USER_PRIORITY 8
53#define IXGBE_DCB_MAX_BW_GROUP 8
54#define IXGBE_DCB_BW_PERCENT 100
55
56#define IXGBE_DCB_TX_CONFIG 0
57#define IXGBE_DCB_RX_CONFIG 1
58
59/* DCB capability defines */
60#define IXGBE_DCB_PG_SUPPORT 0x00000001
61#define IXGBE_DCB_PFC_SUPPORT 0x00000002
62#define IXGBE_DCB_BCN_SUPPORT 0x00000004
63#define IXGBE_DCB_UP2TC_SUPPORT 0x00000008
64#define IXGBE_DCB_GSP_SUPPORT 0x00000010
65
66struct ixgbe_dcb_support {
67 u32 capabilities; /* DCB capabilities */
68
69 /* Each bit represents a number of TCs configurable in the hw.
70 * If 8 traffic classes can be configured, the value is 0x80. */
71 u8 traffic_classes;
72 u8 pfc_traffic_classes;
73};
74
75enum ixgbe_dcb_tsa {
76 ixgbe_dcb_tsa_ets = 0,
77 ixgbe_dcb_tsa_group_strict_cee,
78 ixgbe_dcb_tsa_strict
79};
80
81/* Traffic class bandwidth allocation per direction */
82struct ixgbe_dcb_tc_path {
83 u8 bwg_id; /* Bandwidth Group (BWG) ID */
84 u8 bwg_percent; /* % of BWG's bandwidth */
85 u8 link_percent; /* % of link bandwidth */
86 u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */
87 u16 data_credits_refill; /* Credit refill amount in 64B granularity */
88 u16 data_credits_max; /* Max credits for a configured packet buffer
89 * in 64B granularity.*/
90 enum ixgbe_dcb_tsa tsa; /* Link or Group Strict Priority */
91};
92
93enum ixgbe_dcb_pfc {
94 ixgbe_dcb_pfc_disabled = 0,
95 ixgbe_dcb_pfc_enabled,
96 ixgbe_dcb_pfc_enabled_txonly,
97 ixgbe_dcb_pfc_enabled_rxonly
98};
99
100/* Traffic class configuration */
101struct ixgbe_dcb_tc_config {
102 struct ixgbe_dcb_tc_path path[2]; /* One each for Tx/Rx */
103 enum ixgbe_dcb_pfc pfc; /* Class based flow control setting */
104
105 u16 desc_credits_max; /* For Tx Descriptor arbitration */
106 u8 tc; /* Traffic class (TC) */
107};
108
109enum ixgbe_dcb_pba {
110 /* PBA[0-7] each use 64KB FIFO */
111 ixgbe_dcb_pba_equal = PBA_STRATEGY_EQUAL,
112 /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */
113 ixgbe_dcb_pba_80_48 = PBA_STRATEGY_WEIGHTED
114};
115
116struct ixgbe_dcb_num_tcs {
117 u8 pg_tcs;
118 u8 pfc_tcs;
119};
120
121struct ixgbe_dcb_config {
122 struct ixgbe_dcb_tc_config tc_config[IXGBE_DCB_MAX_TRAFFIC_CLASS];
123 struct ixgbe_dcb_support support;
124 struct ixgbe_dcb_num_tcs num_tcs;
125 u8 bw_percentage[2][IXGBE_DCB_MAX_BW_GROUP]; /* One each for Tx/Rx */
126 bool pfc_mode_enable;
127 bool round_robin_enable;
128
129 enum ixgbe_dcb_pba rx_pba_cfg;
130
131 u32 dcb_cfg_version; /* Not used...OS-specific? */
132 u32 link_speed; /* For bandwidth allocation validation purpose */
133 bool vt_mode;
134};
135
136/* DCB driver APIs */
137
138/* DCB rule checking */
139s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *);
140
141/* DCB credits calculation */
142s32 ixgbe_dcb_calculate_tc_credits(u8 *, u16 *, u16 *, int);
143s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *,
144 struct ixgbe_dcb_config *, u32, u8);
145
146/* DCB PFC */
147s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *, u8, u8 *);
148s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *);
149
150/* DCB stats */
151s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *);
152s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);
153s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);
154
155/* DCB config arbiters */
156s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *,
157 struct ixgbe_dcb_config *);
158s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *,
159 struct ixgbe_dcb_config *);
160s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *,
161 struct ixgbe_dcb_config *);
162
163/* DCB unpack routines */
164void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *, u8 *, u8 *);
165void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *, int, u16 *);
166void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *, u16 *);
167void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *, int, u8 *);
168void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *, int, u8 *);
169void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *, int, u8 *);
170u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *, int, u8);
171
172/* DCB initialization */
173s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, u16 *, u16 *, u8 *, u8 *, u8 *);
174s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *);
175#endif /* _IXGBE_DCB_H_ */
|